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[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "ilo_common.h"
32 #include "ilo_gpe_gen6.h"
33
34 /**
35 * Commands that GEN7 GPE could emit.
36 */
37 enum ilo_gpe_gen7_command {
38 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
39 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
40 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
41 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
42 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
43 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
44 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
45 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
46 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
47 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
48 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
49 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
50 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
51 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
52 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
53 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
54 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
55 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
56 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
57 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
58 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
59 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
60 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
61 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
62 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
63 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
64 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
65 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
67 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
68 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
69 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
70 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
71 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
72 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
73 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
74 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
75 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
76 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
77 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
78 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
79 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
80 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
81 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
82 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
83 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
84 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
85 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
86 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
87 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
88 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
89 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
90 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
91 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
92 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
93 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
94 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
95 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
96 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
97 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
98 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
99 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
100 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
101 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
102 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
103 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
104 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
105 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
106
107 ILO_GPE_GEN7_COMMAND_COUNT,
108 };
109
110 /**
111 * Indirect states that GEN7 GPE could emit.
112 */
113 enum ilo_gpe_gen7_state {
114 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
115 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
116 ILO_GPE_GEN7_CC_VIEWPORT,
117 ILO_GPE_GEN7_COLOR_CALC_STATE,
118 ILO_GPE_GEN7_BLEND_STATE,
119 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
120 ILO_GPE_GEN7_SCISSOR_RECT,
121 ILO_GPE_GEN7_BINDING_TABLE_STATE,
122 ILO_GPE_GEN7_SURFACE_STATE,
123 ILO_GPE_GEN7_SAMPLER_STATE,
124 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
125 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
126
127 ILO_GPE_GEN7_STATE_COUNT,
128 };
129
130 typedef ilo_gpe_gen6_STATE_BASE_ADDRESS ilo_gpe_gen7_STATE_BASE_ADDRESS;
131 typedef ilo_gpe_gen6_STATE_SIP ilo_gpe_gen7_STATE_SIP;
132 typedef ilo_gpe_gen6_3DSTATE_VF_STATISTICS ilo_gpe_gen7_3DSTATE_VF_STATISTICS;
133 typedef ilo_gpe_gen6_PIPELINE_SELECT ilo_gpe_gen7_PIPELINE_SELECT;
134 typedef ilo_gpe_gen6_MEDIA_VFE_STATE ilo_gpe_gen7_MEDIA_VFE_STATE;
135 typedef ilo_gpe_gen6_MEDIA_CURBE_LOAD ilo_gpe_gen7_MEDIA_CURBE_LOAD;
136 typedef ilo_gpe_gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD ilo_gpe_gen7_MEDIA_INTERFACE_DESCRIPTOR_LOAD;
137 typedef ilo_gpe_gen6_MEDIA_STATE_FLUSH ilo_gpe_gen7_MEDIA_STATE_FLUSH;
138
139 typedef void
140 (*ilo_gpe_gen7_GPGPU_WALKER)(const struct ilo_dev_info *dev,
141 struct ilo_cp *cp);
142
143 typedef ilo_gpe_gen6_3DSTATE_CLEAR_PARAMS ilo_gpe_gen7_3DSTATE_CLEAR_PARAMS;
144 typedef ilo_gpe_gen6_3DSTATE_DEPTH_BUFFER ilo_gpe_gen7_3DSTATE_DEPTH_BUFFER;
145 typedef ilo_gpe_gen6_3DSTATE_STENCIL_BUFFER ilo_gpe_gen7_3DSTATE_STENCIL_BUFFER;
146 typedef ilo_gpe_gen6_3DSTATE_HIER_DEPTH_BUFFER ilo_gpe_gen7_3DSTATE_HIER_DEPTH_BUFFER;
147 typedef ilo_gpe_gen6_3DSTATE_VERTEX_BUFFERS ilo_gpe_gen7_3DSTATE_VERTEX_BUFFERS;
148 typedef ilo_gpe_gen6_3DSTATE_VERTEX_ELEMENTS ilo_gpe_gen7_3DSTATE_VERTEX_ELEMENTS;
149 typedef ilo_gpe_gen6_3DSTATE_INDEX_BUFFER ilo_gpe_gen7_3DSTATE_INDEX_BUFFER;
150
151 typedef void
152 (*ilo_gpe_gen7_3DSTATE_CC_STATE_POINTERS)(const struct ilo_dev_info *dev,
153 uint32_t color_calc_state,
154 struct ilo_cp *cp);
155
156 typedef ilo_gpe_gen6_3DSTATE_SCISSOR_STATE_POINTERS ilo_gpe_gen7_3DSTATE_SCISSOR_STATE_POINTERS;
157 typedef ilo_gpe_gen6_3DSTATE_VS ilo_gpe_gen7_3DSTATE_VS;
158
159 typedef void
160 (*ilo_gpe_gen7_3DSTATE_GS)(const struct ilo_dev_info *dev,
161 const struct ilo_shader_state *gs,
162 int num_samplers,
163 struct ilo_cp *cp);
164
165 typedef ilo_gpe_gen6_3DSTATE_CLIP ilo_gpe_gen7_3DSTATE_CLIP;
166
167 typedef void
168 (*ilo_gpe_gen7_3DSTATE_SF)(const struct ilo_dev_info *dev,
169 const struct ilo_rasterizer_state *rasterizer,
170 const struct pipe_surface *zs_surf,
171 struct ilo_cp *cp);
172
173 typedef void
174 (*ilo_gpe_gen7_3DSTATE_WM)(const struct ilo_dev_info *dev,
175 const struct ilo_shader_state *fs,
176 const struct ilo_rasterizer_state *rasterizer,
177 bool cc_may_kill,
178 struct ilo_cp *cp);
179
180 typedef ilo_gpe_gen6_3DSTATE_CONSTANT_VS ilo_gpe_gen7_3DSTATE_CONSTANT_VS;
181 typedef ilo_gpe_gen6_3DSTATE_CONSTANT_GS ilo_gpe_gen7_3DSTATE_CONSTANT_GS;
182 typedef ilo_gpe_gen6_3DSTATE_CONSTANT_PS ilo_gpe_gen7_3DSTATE_CONSTANT_PS;
183
184 typedef void
185 (*ilo_gpe_gen7_3DSTATE_SAMPLE_MASK)(const struct ilo_dev_info *dev,
186 unsigned sample_mask,
187 int num_samples,
188 struct ilo_cp *cp);
189
190 typedef void
191 (*ilo_gpe_gen7_3DSTATE_CONSTANT_HS)(const struct ilo_dev_info *dev,
192 const uint32_t *bufs, const int *sizes,
193 int num_bufs,
194 struct ilo_cp *cp);
195
196 typedef void
197 (*ilo_gpe_gen7_3DSTATE_CONSTANT_DS)(const struct ilo_dev_info *dev,
198 const uint32_t *bufs, const int *sizes,
199 int num_bufs,
200 struct ilo_cp *cp);
201
202 typedef void
203 (*ilo_gpe_gen7_3DSTATE_HS)(const struct ilo_dev_info *dev,
204 const struct ilo_shader_state *hs,
205 int num_samplers,
206 struct ilo_cp *cp);
207
208 typedef void
209 (*ilo_gpe_gen7_3DSTATE_TE)(const struct ilo_dev_info *dev,
210 struct ilo_cp *cp);
211
212 typedef void
213 (*ilo_gpe_gen7_3DSTATE_DS)(const struct ilo_dev_info *dev,
214 const struct ilo_shader_state *ds,
215 int num_samplers,
216 struct ilo_cp *cp);
217
218 typedef void
219 (*ilo_gpe_gen7_3DSTATE_STREAMOUT)(const struct ilo_dev_info *dev,
220 unsigned buffer_mask,
221 int vertex_attrib_count,
222 bool rasterizer_discard,
223 struct ilo_cp *cp);
224
225 typedef void
226 (*ilo_gpe_gen7_3DSTATE_SBE)(const struct ilo_dev_info *dev,
227 const struct ilo_rasterizer_state *rasterizer,
228 const struct ilo_shader_state *fs,
229 const struct ilo_shader_state *last_sh,
230 struct ilo_cp *cp);
231
232 typedef void
233 (*ilo_gpe_gen7_3DSTATE_PS)(const struct ilo_dev_info *dev,
234 const struct ilo_shader_state *fs,
235 int num_samplers, bool dual_blend,
236 struct ilo_cp *cp);
237
238 typedef void
239 (*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP)(const struct ilo_dev_info *dev,
240 uint32_t viewport,
241 struct ilo_cp *cp);
242
243 typedef void
244 (*ilo_gpe_gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC)(const struct ilo_dev_info *dev,
245 uint32_t viewport,
246 struct ilo_cp *cp);
247
248 typedef void
249 (*ilo_gpe_gen7_3DSTATE_BLEND_STATE_POINTERS)(const struct ilo_dev_info *dev,
250 uint32_t blend,
251 struct ilo_cp *cp);
252
253 typedef void
254 (*ilo_gpe_gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS)(const struct ilo_dev_info *dev,
255 uint32_t depth_stencil,
256 struct ilo_cp *cp);
257
258 typedef void
259 (*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_VS)(const struct ilo_dev_info *dev,
260 uint32_t binding_table,
261 struct ilo_cp *cp);
262
263 typedef void
264 (*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_HS)(const struct ilo_dev_info *dev,
265 uint32_t binding_table,
266 struct ilo_cp *cp);
267
268 typedef void
269 (*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_DS)(const struct ilo_dev_info *dev,
270 uint32_t binding_table,
271 struct ilo_cp *cp);
272
273 typedef void
274 (*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_GS)(const struct ilo_dev_info *dev,
275 uint32_t binding_table,
276 struct ilo_cp *cp);
277
278 typedef void
279 (*ilo_gpe_gen7_3DSTATE_BINDING_TABLE_POINTERS_PS)(const struct ilo_dev_info *dev,
280 uint32_t binding_table,
281 struct ilo_cp *cp);
282
283 typedef void
284 (*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS)(const struct ilo_dev_info *dev,
285 uint32_t sampler_state,
286 struct ilo_cp *cp);
287
288 typedef void
289 (*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_HS)(const struct ilo_dev_info *dev,
290 uint32_t sampler_state,
291 struct ilo_cp *cp);
292
293 typedef void
294 (*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_DS)(const struct ilo_dev_info *dev,
295 uint32_t sampler_state,
296 struct ilo_cp *cp);
297
298 typedef void
299 (*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_GS)(const struct ilo_dev_info *dev,
300 uint32_t sampler_state,
301 struct ilo_cp *cp);
302
303 typedef void
304 (*ilo_gpe_gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS)(const struct ilo_dev_info *dev,
305 uint32_t sampler_state,
306 struct ilo_cp *cp);
307
308 typedef void
309 (*ilo_gpe_gen7_3DSTATE_URB_VS)(const struct ilo_dev_info *dev,
310 int offset, int size, int entry_size,
311 struct ilo_cp *cp);
312
313 typedef void
314 (*ilo_gpe_gen7_3DSTATE_URB_HS)(const struct ilo_dev_info *dev,
315 int offset, int size, int entry_size,
316 struct ilo_cp *cp);
317
318 typedef void
319 (*ilo_gpe_gen7_3DSTATE_URB_DS)(const struct ilo_dev_info *dev,
320 int offset, int size, int entry_size,
321 struct ilo_cp *cp);
322
323 typedef void
324 (*ilo_gpe_gen7_3DSTATE_URB_GS)(const struct ilo_dev_info *dev,
325 int offset, int size, int entry_size,
326 struct ilo_cp *cp);
327
328 typedef ilo_gpe_gen6_3DSTATE_DRAWING_RECTANGLE ilo_gpe_gen7_3DSTATE_DRAWING_RECTANGLE;
329 typedef ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_OFFSET ilo_gpe_gen7_3DSTATE_POLY_STIPPLE_OFFSET;
330 typedef ilo_gpe_gen6_3DSTATE_POLY_STIPPLE_PATTERN ilo_gpe_gen7_3DSTATE_POLY_STIPPLE_PATTERN;
331 typedef ilo_gpe_gen6_3DSTATE_LINE_STIPPLE ilo_gpe_gen7_3DSTATE_LINE_STIPPLE;
332 typedef ilo_gpe_gen6_3DSTATE_AA_LINE_PARAMETERS ilo_gpe_gen7_3DSTATE_AA_LINE_PARAMETERS;
333 typedef ilo_gpe_gen6_3DSTATE_MULTISAMPLE ilo_gpe_gen7_3DSTATE_MULTISAMPLE;
334
335 typedef void
336 (*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS)(const struct ilo_dev_info *dev,
337 int offset, int size,
338 struct ilo_cp *cp);
339
340 typedef void
341 (*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_HS)(const struct ilo_dev_info *dev,
342 int offset, int size,
343 struct ilo_cp *cp);
344
345 typedef void
346 (*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_DS)(const struct ilo_dev_info *dev,
347 int offset, int size,
348 struct ilo_cp *cp);
349
350 typedef void
351 (*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS)(const struct ilo_dev_info *dev,
352 int offset, int size,
353 struct ilo_cp *cp);
354
355 typedef void
356 (*ilo_gpe_gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS)(const struct ilo_dev_info *dev,
357 int offset, int size,
358 struct ilo_cp *cp);
359
360 typedef void
361 (*ilo_gpe_gen7_3DSTATE_SO_DECL_LIST)(const struct ilo_dev_info *dev,
362 const struct pipe_stream_output_info *so_info,
363 struct ilo_cp *cp);
364
365 typedef void
366 (*ilo_gpe_gen7_3DSTATE_SO_BUFFER)(const struct ilo_dev_info *dev,
367 int index, int base, int stride,
368 const struct pipe_stream_output_target *so_target,
369 struct ilo_cp *cp);
370
371 typedef ilo_gpe_gen6_PIPE_CONTROL ilo_gpe_gen7_PIPE_CONTROL;
372 typedef ilo_gpe_gen6_3DPRIMITIVE ilo_gpe_gen7_3DPRIMITIVE;
373 typedef ilo_gpe_gen6_INTERFACE_DESCRIPTOR_DATA ilo_gpe_gen7_INTERFACE_DESCRIPTOR_DATA;
374
375 typedef uint32_t
376 (*ilo_gpe_gen7_SF_CLIP_VIEWPORT)(const struct ilo_dev_info *dev,
377 const struct ilo_viewport_cso *viewports,
378 unsigned num_viewports,
379 struct ilo_cp *cp);
380
381 typedef ilo_gpe_gen6_CC_VIEWPORT ilo_gpe_gen7_CC_VIEWPORT;
382 typedef ilo_gpe_gen6_COLOR_CALC_STATE ilo_gpe_gen7_COLOR_CALC_STATE;
383 typedef ilo_gpe_gen6_BLEND_STATE ilo_gpe_gen7_BLEND_STATE;
384 typedef ilo_gpe_gen6_DEPTH_STENCIL_STATE ilo_gpe_gen7_DEPTH_STENCIL_STATE;
385 typedef ilo_gpe_gen6_SCISSOR_RECT ilo_gpe_gen7_SCISSOR_RECT;
386 typedef ilo_gpe_gen6_BINDING_TABLE_STATE ilo_gpe_gen7_BINDING_TABLE_STATE;
387 typedef ilo_gpe_gen6_SURFACE_STATE ilo_gpe_gen7_SURFACE_STATE;
388 typedef ilo_gpe_gen6_SAMPLER_STATE ilo_gpe_gen7_SAMPLER_STATE;
389 typedef ilo_gpe_gen6_SAMPLER_BORDER_COLOR_STATE ilo_gpe_gen7_SAMPLER_BORDER_COLOR_STATE;
390 typedef ilo_gpe_gen6_push_constant_buffer ilo_gpe_gen7_push_constant_buffer;
391
392 /**
393 * GEN7 graphics processing engine
394 *
395 * \see ilo_gpe_gen6
396 */
397 struct ilo_gpe_gen7 {
398 int (*estimate_command_size)(const struct ilo_dev_info *dev,
399 enum ilo_gpe_gen7_command cmd,
400 int arg);
401
402 int (*estimate_state_size)(const struct ilo_dev_info *dev,
403 enum ilo_gpe_gen7_state state,
404 int arg);
405
406 #define GEN7_EMIT(name) ilo_gpe_gen7_ ## name emit_ ## name
407 GEN7_EMIT(STATE_BASE_ADDRESS);
408 GEN7_EMIT(STATE_SIP);
409 GEN7_EMIT(3DSTATE_VF_STATISTICS);
410 GEN7_EMIT(PIPELINE_SELECT);
411 GEN7_EMIT(MEDIA_VFE_STATE);
412 GEN7_EMIT(MEDIA_CURBE_LOAD);
413 GEN7_EMIT(MEDIA_INTERFACE_DESCRIPTOR_LOAD);
414 GEN7_EMIT(MEDIA_STATE_FLUSH);
415 GEN7_EMIT(GPGPU_WALKER);
416 GEN7_EMIT(3DSTATE_CLEAR_PARAMS);
417 GEN7_EMIT(3DSTATE_DEPTH_BUFFER);
418 GEN7_EMIT(3DSTATE_STENCIL_BUFFER);
419 GEN7_EMIT(3DSTATE_HIER_DEPTH_BUFFER);
420 GEN7_EMIT(3DSTATE_VERTEX_BUFFERS);
421 GEN7_EMIT(3DSTATE_VERTEX_ELEMENTS);
422 GEN7_EMIT(3DSTATE_INDEX_BUFFER);
423 GEN7_EMIT(3DSTATE_CC_STATE_POINTERS);
424 GEN7_EMIT(3DSTATE_SCISSOR_STATE_POINTERS);
425 GEN7_EMIT(3DSTATE_VS);
426 GEN7_EMIT(3DSTATE_GS);
427 GEN7_EMIT(3DSTATE_CLIP);
428 GEN7_EMIT(3DSTATE_SF);
429 GEN7_EMIT(3DSTATE_WM);
430 GEN7_EMIT(3DSTATE_CONSTANT_VS);
431 GEN7_EMIT(3DSTATE_CONSTANT_GS);
432 GEN7_EMIT(3DSTATE_CONSTANT_PS);
433 GEN7_EMIT(3DSTATE_SAMPLE_MASK);
434 GEN7_EMIT(3DSTATE_CONSTANT_HS);
435 GEN7_EMIT(3DSTATE_CONSTANT_DS);
436 GEN7_EMIT(3DSTATE_HS);
437 GEN7_EMIT(3DSTATE_TE);
438 GEN7_EMIT(3DSTATE_DS);
439 GEN7_EMIT(3DSTATE_STREAMOUT);
440 GEN7_EMIT(3DSTATE_SBE);
441 GEN7_EMIT(3DSTATE_PS);
442 GEN7_EMIT(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
443 GEN7_EMIT(3DSTATE_VIEWPORT_STATE_POINTERS_CC);
444 GEN7_EMIT(3DSTATE_BLEND_STATE_POINTERS);
445 GEN7_EMIT(3DSTATE_DEPTH_STENCIL_STATE_POINTERS);
446 GEN7_EMIT(3DSTATE_BINDING_TABLE_POINTERS_VS);
447 GEN7_EMIT(3DSTATE_BINDING_TABLE_POINTERS_HS);
448 GEN7_EMIT(3DSTATE_BINDING_TABLE_POINTERS_DS);
449 GEN7_EMIT(3DSTATE_BINDING_TABLE_POINTERS_GS);
450 GEN7_EMIT(3DSTATE_BINDING_TABLE_POINTERS_PS);
451 GEN7_EMIT(3DSTATE_SAMPLER_STATE_POINTERS_VS);
452 GEN7_EMIT(3DSTATE_SAMPLER_STATE_POINTERS_HS);
453 GEN7_EMIT(3DSTATE_SAMPLER_STATE_POINTERS_DS);
454 GEN7_EMIT(3DSTATE_SAMPLER_STATE_POINTERS_GS);
455 GEN7_EMIT(3DSTATE_SAMPLER_STATE_POINTERS_PS);
456 GEN7_EMIT(3DSTATE_URB_VS);
457 GEN7_EMIT(3DSTATE_URB_HS);
458 GEN7_EMIT(3DSTATE_URB_DS);
459 GEN7_EMIT(3DSTATE_URB_GS);
460 GEN7_EMIT(3DSTATE_DRAWING_RECTANGLE);
461 GEN7_EMIT(3DSTATE_POLY_STIPPLE_OFFSET);
462 GEN7_EMIT(3DSTATE_POLY_STIPPLE_PATTERN);
463 GEN7_EMIT(3DSTATE_LINE_STIPPLE);
464 GEN7_EMIT(3DSTATE_AA_LINE_PARAMETERS);
465 GEN7_EMIT(3DSTATE_MULTISAMPLE);
466 GEN7_EMIT(3DSTATE_PUSH_CONSTANT_ALLOC_VS);
467 GEN7_EMIT(3DSTATE_PUSH_CONSTANT_ALLOC_HS);
468 GEN7_EMIT(3DSTATE_PUSH_CONSTANT_ALLOC_DS);
469 GEN7_EMIT(3DSTATE_PUSH_CONSTANT_ALLOC_GS);
470 GEN7_EMIT(3DSTATE_PUSH_CONSTANT_ALLOC_PS);
471 GEN7_EMIT(3DSTATE_SO_DECL_LIST);
472 GEN7_EMIT(3DSTATE_SO_BUFFER);
473 GEN7_EMIT(PIPE_CONTROL);
474 GEN7_EMIT(3DPRIMITIVE);
475 GEN7_EMIT(INTERFACE_DESCRIPTOR_DATA);
476 GEN7_EMIT(SF_CLIP_VIEWPORT);
477 GEN7_EMIT(CC_VIEWPORT);
478 GEN7_EMIT(COLOR_CALC_STATE);
479 GEN7_EMIT(BLEND_STATE);
480 GEN7_EMIT(DEPTH_STENCIL_STATE);
481 GEN7_EMIT(SCISSOR_RECT);
482 GEN7_EMIT(BINDING_TABLE_STATE);
483 GEN7_EMIT(SURFACE_STATE);
484 GEN7_EMIT(SAMPLER_STATE);
485 GEN7_EMIT(SAMPLER_BORDER_COLOR_STATE);
486 GEN7_EMIT(push_constant_buffer);
487 #undef GEN7_EMIT
488 };
489
490 const struct ilo_gpe_gen7 *
491 ilo_gpe_gen7_get(void);
492
493 static inline void
494 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
495 struct ilo_cp *cp)
496 {
497 assert(!"GPGPU_WALKER unsupported");
498 }
499
500 static inline void
501 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
502 uint32_t clear_val,
503 struct ilo_cp *cp)
504 {
505 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
506 const uint8_t cmd_len = 3;
507
508 ILO_GPE_VALID_GEN(dev, 7, 7);
509
510 ilo_cp_begin(cp, cmd_len);
511 ilo_cp_write(cp, cmd | (cmd_len - 2));
512 ilo_cp_write(cp, clear_val);
513 ilo_cp_write(cp, 1);
514 ilo_cp_end(cp);
515 }
516
517 static inline void
518 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
519 int subop, uint32_t pointer,
520 struct ilo_cp *cp)
521 {
522 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
523 const uint8_t cmd_len = 2;
524
525 ILO_GPE_VALID_GEN(dev, 7, 7);
526
527 ilo_cp_begin(cp, cmd_len);
528 ilo_cp_write(cp, cmd | (cmd_len - 2));
529 ilo_cp_write(cp, pointer);
530 ilo_cp_end(cp);
531 }
532
533 static inline void
534 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
535 uint32_t color_calc_state,
536 struct ilo_cp *cp)
537 {
538 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
539 }
540
541 static inline void
542 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
543 const struct ilo_shader_state *gs,
544 int num_samplers,
545 struct ilo_cp *cp)
546 {
547 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
548 const uint8_t cmd_len = 7;
549 const struct ilo_shader_cso *cso;
550 uint32_t dw2, dw4, dw5;
551
552 ILO_GPE_VALID_GEN(dev, 7, 7);
553
554 if (!gs) {
555 ilo_cp_begin(cp, cmd_len);
556 ilo_cp_write(cp, cmd | (cmd_len - 2));
557 ilo_cp_write(cp, 0);
558 ilo_cp_write(cp, 0);
559 ilo_cp_write(cp, 0);
560 ilo_cp_write(cp, 0);
561 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
562 ilo_cp_write(cp, 0);
563 ilo_cp_end(cp);
564 return;
565 }
566
567 cso = ilo_shader_get_kernel_cso(gs);
568 dw2 = cso->payload[0];
569 dw4 = cso->payload[1];
570 dw5 = cso->payload[2];
571
572 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
573
574 ilo_cp_begin(cp, cmd_len);
575 ilo_cp_write(cp, cmd | (cmd_len - 2));
576 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
577 ilo_cp_write(cp, dw2);
578 ilo_cp_write(cp, 0); /* scratch */
579 ilo_cp_write(cp, dw4);
580 ilo_cp_write(cp, dw5);
581 ilo_cp_write(cp, 0);
582 ilo_cp_end(cp);
583 }
584
585 static inline void
586 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
587 const struct ilo_rasterizer_state *rasterizer,
588 const struct pipe_surface *zs_surf,
589 struct ilo_cp *cp)
590 {
591 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
592 const uint8_t cmd_len = 7;
593 const int num_samples = 1;
594 uint32_t payload[6];
595
596 ILO_GPE_VALID_GEN(dev, 7, 7);
597
598 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
599 rasterizer, num_samples,
600 (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
601 payload, Elements(payload));
602
603 ilo_cp_begin(cp, cmd_len);
604 ilo_cp_write(cp, cmd | (cmd_len - 2));
605 ilo_cp_write_multi(cp, payload, 6);
606 ilo_cp_end(cp);
607 }
608
609 static inline void
610 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
611 const struct ilo_shader_state *fs,
612 const struct ilo_rasterizer_state *rasterizer,
613 bool cc_may_kill,
614 struct ilo_cp *cp)
615 {
616 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
617 const uint8_t cmd_len = 3;
618 const int num_samples = 1;
619 uint32_t dw1, dw2;
620
621 ILO_GPE_VALID_GEN(dev, 7, 7);
622
623 /* see ilo_gpe_init_rasterizer_wm() */
624 dw1 = rasterizer->wm.payload[0];
625 dw2 = rasterizer->wm.payload[1];
626
627 dw1 |= GEN7_WM_STATISTICS_ENABLE;
628
629 if (false) {
630 dw1 |= GEN7_WM_DEPTH_CLEAR;
631 dw1 |= GEN7_WM_DEPTH_RESOLVE;
632 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
633 }
634
635 if (fs) {
636 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
637
638 dw1 |= fs_cso->payload[3];
639 }
640
641 if (cc_may_kill) {
642 dw1 |= GEN7_WM_DISPATCH_ENABLE |
643 GEN7_WM_KILL_ENABLE;
644 }
645
646 if (num_samples > 1) {
647 dw1 |= rasterizer->wm.dw_msaa_rast;
648 dw2 |= rasterizer->wm.dw_msaa_disp;
649 }
650
651 ilo_cp_begin(cp, cmd_len);
652 ilo_cp_write(cp, cmd | (cmd_len - 2));
653 ilo_cp_write(cp, dw1);
654 ilo_cp_write(cp, dw2);
655 ilo_cp_end(cp);
656 }
657
658 static inline void
659 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
660 int subop,
661 const uint32_t *bufs, const int *sizes,
662 int num_bufs,
663 struct ilo_cp *cp)
664 {
665 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
666 const uint8_t cmd_len = 7;
667 uint32_t dw[6];
668 int total_read_length, i;
669
670 ILO_GPE_VALID_GEN(dev, 7, 7);
671
672 /* VS, HS, DS, GS, and PS variants */
673 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
674
675 assert(num_bufs <= 4);
676
677 dw[0] = 0;
678 dw[1] = 0;
679
680 total_read_length = 0;
681 for (i = 0; i < 4; i++) {
682 int read_len;
683
684 /*
685 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
686 *
687 * "Constant buffers must be enabled in order from Constant Buffer 0
688 * to Constant Buffer 3 within this command. For example, it is
689 * not allowed to enable Constant Buffer 1 by programming a
690 * non-zero value in the VS Constant Buffer 1 Read Length without a
691 * non-zero value in VS Constant Buffer 0 Read Length."
692 */
693 if (i >= num_bufs || !sizes[i]) {
694 for (; i < 4; i++) {
695 assert(i >= num_bufs || !sizes[i]);
696 dw[2 + i] = 0;
697 }
698 break;
699 }
700
701 /* read lengths are in 256-bit units */
702 read_len = (sizes[i] + 31) / 32;
703 /* the lower 5 bits are used for memory object control state */
704 assert(bufs[i] % 32 == 0);
705
706 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
707 dw[2 + i] = bufs[i];
708
709 total_read_length += read_len;
710 }
711
712 /*
713 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
714 *
715 * "The sum of all four read length fields must be less than or equal
716 * to the size of 64"
717 */
718 assert(total_read_length <= 64);
719
720 ilo_cp_begin(cp, cmd_len);
721 ilo_cp_write(cp, cmd | (cmd_len - 2));
722 ilo_cp_write_multi(cp, dw, 6);
723 ilo_cp_end(cp);
724 }
725
726 static inline void
727 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
728 const uint32_t *bufs, const int *sizes,
729 int num_bufs,
730 struct ilo_cp *cp)
731 {
732 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
733 }
734
735 static inline void
736 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
737 const uint32_t *bufs, const int *sizes,
738 int num_bufs,
739 struct ilo_cp *cp)
740 {
741 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
742 }
743
744 static inline void
745 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
746 const uint32_t *bufs, const int *sizes,
747 int num_bufs,
748 struct ilo_cp *cp)
749 {
750 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
751 }
752
753 static inline void
754 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
755 unsigned sample_mask,
756 int num_samples,
757 struct ilo_cp *cp)
758 {
759 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
760 const uint8_t cmd_len = 2;
761 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
762
763 ILO_GPE_VALID_GEN(dev, 7, 7);
764
765 /*
766 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
767 *
768 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
769 * (Sample Mask) must be zero.
770 *
771 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
772 * must be zero."
773 */
774 sample_mask &= valid_mask;
775
776 ilo_cp_begin(cp, cmd_len);
777 ilo_cp_write(cp, cmd | (cmd_len - 2));
778 ilo_cp_write(cp, sample_mask);
779 ilo_cp_end(cp);
780 }
781
782 static inline void
783 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
784 const uint32_t *bufs, const int *sizes,
785 int num_bufs,
786 struct ilo_cp *cp)
787 {
788 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
789 }
790
791 static inline void
792 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
793 const uint32_t *bufs, const int *sizes,
794 int num_bufs,
795 struct ilo_cp *cp)
796 {
797 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
798 }
799
800 static inline void
801 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
802 const struct ilo_shader_state *hs,
803 int num_samplers,
804 struct ilo_cp *cp)
805 {
806 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
807 const uint8_t cmd_len = 7;
808
809 ILO_GPE_VALID_GEN(dev, 7, 7);
810
811 assert(!hs);
812
813 ilo_cp_begin(cp, cmd_len);
814 ilo_cp_write(cp, cmd | (cmd_len - 2));
815 ilo_cp_write(cp, 0);
816 ilo_cp_write(cp, 0);
817 ilo_cp_write(cp, 0);
818 ilo_cp_write(cp, 0);
819 ilo_cp_write(cp, 0);
820 ilo_cp_write(cp, 0);
821 ilo_cp_end(cp);
822 }
823
824 static inline void
825 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
826 struct ilo_cp *cp)
827 {
828 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
829 const uint8_t cmd_len = 4;
830
831 ILO_GPE_VALID_GEN(dev, 7, 7);
832
833 ilo_cp_begin(cp, cmd_len);
834 ilo_cp_write(cp, cmd | (cmd_len - 2));
835 ilo_cp_write(cp, 0);
836 ilo_cp_write(cp, 0);
837 ilo_cp_write(cp, 0);
838 ilo_cp_end(cp);
839 }
840
841 static inline void
842 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
843 const struct ilo_shader_state *ds,
844 int num_samplers,
845 struct ilo_cp *cp)
846 {
847 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
848 const uint8_t cmd_len = 6;
849
850 ILO_GPE_VALID_GEN(dev, 7, 7);
851
852 assert(!ds);
853
854 ilo_cp_begin(cp, cmd_len);
855 ilo_cp_write(cp, cmd | (cmd_len - 2));
856 ilo_cp_write(cp, 0);
857 ilo_cp_write(cp, 0);
858 ilo_cp_write(cp, 0);
859 ilo_cp_write(cp, 0);
860 ilo_cp_write(cp, 0);
861 ilo_cp_end(cp);
862
863 }
864
865 static inline void
866 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
867 unsigned buffer_mask,
868 int vertex_attrib_count,
869 bool rasterizer_discard,
870 struct ilo_cp *cp)
871 {
872 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
873 const uint8_t cmd_len = 3;
874 const bool enable = (buffer_mask != 0);
875 uint32_t dw1, dw2;
876 int read_len;
877
878 ILO_GPE_VALID_GEN(dev, 7, 7);
879
880 if (!enable) {
881 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
882 if (rasterizer_discard)
883 dw1 |= SO_RENDERING_DISABLE;
884
885 dw2 = 0;
886
887 ilo_cp_begin(cp, cmd_len);
888 ilo_cp_write(cp, cmd | (cmd_len - 2));
889 ilo_cp_write(cp, dw1);
890 ilo_cp_write(cp, dw2);
891 ilo_cp_end(cp);
892 return;
893 }
894
895 read_len = (vertex_attrib_count + 1) / 2;
896 if (!read_len)
897 read_len = 1;
898
899 dw1 = SO_FUNCTION_ENABLE |
900 0 << SO_RENDER_STREAM_SELECT_SHIFT |
901 SO_STATISTICS_ENABLE |
902 buffer_mask << 8;
903
904 if (rasterizer_discard)
905 dw1 |= SO_RENDERING_DISABLE;
906
907 /* API_OPENGL */
908 if (true)
909 dw1 |= SO_REORDER_TRAILING;
910
911 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
912 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
913 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
914 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
915 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
916 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
917 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
918 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
919
920 ilo_cp_begin(cp, cmd_len);
921 ilo_cp_write(cp, cmd | (cmd_len - 2));
922 ilo_cp_write(cp, dw1);
923 ilo_cp_write(cp, dw2);
924 ilo_cp_end(cp);
925 }
926
927 static inline void
928 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
929 const struct ilo_rasterizer_state *rasterizer,
930 const struct ilo_shader_state *fs,
931 const struct ilo_shader_state *last_sh,
932 struct ilo_cp *cp)
933 {
934 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
935 const uint8_t cmd_len = 14;
936 uint32_t dw[13];
937
938 ILO_GPE_VALID_GEN(dev, 7, 7);
939
940 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer,
941 fs, last_sh, dw, Elements(dw));
942
943 ilo_cp_begin(cp, cmd_len);
944 ilo_cp_write(cp, cmd | (cmd_len - 2));
945 ilo_cp_write_multi(cp, dw, 13);
946 ilo_cp_end(cp);
947 }
948
949 static inline void
950 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
951 const struct ilo_shader_state *fs,
952 int num_samplers, bool dual_blend,
953 struct ilo_cp *cp)
954 {
955 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
956 const uint8_t cmd_len = 8;
957 const struct ilo_shader_cso *cso;
958 uint32_t dw2, dw4, dw5;
959
960 ILO_GPE_VALID_GEN(dev, 7, 7);
961
962 if (!fs) {
963 /* see brwCreateContext() */
964 const int max_threads = (dev->gt == 2) ? 172 : 48;
965
966 ilo_cp_begin(cp, cmd_len);
967 ilo_cp_write(cp, cmd | (cmd_len - 2));
968 ilo_cp_write(cp, 0);
969 ilo_cp_write(cp, 0);
970 ilo_cp_write(cp, 0);
971 /* GPU hangs if none of the dispatch enable bits is set */
972 ilo_cp_write(cp, (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
973 GEN7_PS_8_DISPATCH_ENABLE);
974 ilo_cp_write(cp, 0);
975 ilo_cp_write(cp, 0);
976 ilo_cp_write(cp, 0);
977 ilo_cp_end(cp);
978
979 return;
980 }
981
982 cso = ilo_shader_get_kernel_cso(fs);
983 dw2 = cso->payload[0];
984 dw4 = cso->payload[1];
985 dw5 = cso->payload[2];
986
987 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
988
989 if (dual_blend)
990 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
991
992 ilo_cp_begin(cp, cmd_len);
993 ilo_cp_write(cp, cmd | (cmd_len - 2));
994 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
995 ilo_cp_write(cp, dw2);
996 ilo_cp_write(cp, 0); /* scratch */
997 ilo_cp_write(cp, dw4);
998 ilo_cp_write(cp, dw5);
999 ilo_cp_write(cp, 0); /* kernel 1 */
1000 ilo_cp_write(cp, 0); /* kernel 2 */
1001 ilo_cp_end(cp);
1002 }
1003
1004 static inline void
1005 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
1006 uint32_t sf_clip_viewport,
1007 struct ilo_cp *cp)
1008 {
1009 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
1010 }
1011
1012 static inline void
1013 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
1014 uint32_t cc_viewport,
1015 struct ilo_cp *cp)
1016 {
1017 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
1018 }
1019
1020 static inline void
1021 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
1022 uint32_t blend_state,
1023 struct ilo_cp *cp)
1024 {
1025 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
1026 }
1027
1028 static inline void
1029 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
1030 uint32_t depth_stencil_state,
1031 struct ilo_cp *cp)
1032 {
1033 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
1034 }
1035
1036 static inline void
1037 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
1038 uint32_t binding_table,
1039 struct ilo_cp *cp)
1040 {
1041 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
1042 }
1043
1044 static inline void
1045 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
1046 uint32_t binding_table,
1047 struct ilo_cp *cp)
1048 {
1049 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
1050 }
1051
1052 static inline void
1053 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
1054 uint32_t binding_table,
1055 struct ilo_cp *cp)
1056 {
1057 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
1058 }
1059
1060 static inline void
1061 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
1062 uint32_t binding_table,
1063 struct ilo_cp *cp)
1064 {
1065 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
1066 }
1067
1068 static inline void
1069 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
1070 uint32_t binding_table,
1071 struct ilo_cp *cp)
1072 {
1073 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
1074 }
1075
1076 static inline void
1077 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
1078 uint32_t sampler_state,
1079 struct ilo_cp *cp)
1080 {
1081 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
1082 }
1083
1084 static inline void
1085 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
1086 uint32_t sampler_state,
1087 struct ilo_cp *cp)
1088 {
1089 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
1090 }
1091
1092 static inline void
1093 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
1094 uint32_t sampler_state,
1095 struct ilo_cp *cp)
1096 {
1097 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
1098 }
1099
1100 static inline void
1101 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
1102 uint32_t sampler_state,
1103 struct ilo_cp *cp)
1104 {
1105 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
1106 }
1107
1108 static inline void
1109 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
1110 uint32_t sampler_state,
1111 struct ilo_cp *cp)
1112 {
1113 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
1114 }
1115
1116 static inline void
1117 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
1118 int subop, int offset, int size,
1119 int entry_size,
1120 struct ilo_cp *cp)
1121 {
1122 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
1123 const uint8_t cmd_len = 2;
1124 const int row_size = 64; /* 512 bits */
1125 int alloc_size, num_entries, min_entries, max_entries;
1126
1127 ILO_GPE_VALID_GEN(dev, 7, 7);
1128
1129 /* VS, HS, DS, and GS variants */
1130 assert(subop >= 0x30 && subop <= 0x33);
1131
1132 /* in multiples of 8KB */
1133 assert(offset % 8192 == 0);
1134 offset /= 8192;
1135
1136 /* in multiple of 512-bit rows */
1137 alloc_size = (entry_size + row_size - 1) / row_size;
1138 if (!alloc_size)
1139 alloc_size = 1;
1140
1141 /*
1142 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
1143 *
1144 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
1145 * cause performance to decrease due to banking in the URB. Element
1146 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
1147 */
1148 if (subop == 0x30 && alloc_size == 5)
1149 alloc_size = 6;
1150
1151 /* in multiples of 8 */
1152 num_entries = (size / row_size / alloc_size) & ~7;
1153
1154 switch (subop) {
1155 case 0x30: /* 3DSTATE_URB_VS */
1156 min_entries = 32;
1157 max_entries = (dev->gt == 2) ? 704 : 512;
1158
1159 assert(num_entries >= min_entries);
1160 if (num_entries > max_entries)
1161 num_entries = max_entries;
1162 break;
1163 case 0x31: /* 3DSTATE_URB_HS */
1164 max_entries = (dev->gt == 2) ? 64 : 32;
1165 if (num_entries > max_entries)
1166 num_entries = max_entries;
1167 break;
1168 case 0x32: /* 3DSTATE_URB_DS */
1169 if (num_entries)
1170 assert(num_entries >= 138);
1171 break;
1172 case 0x33: /* 3DSTATE_URB_GS */
1173 max_entries = (dev->gt == 2) ? 320 : 192;
1174 if (num_entries > max_entries)
1175 num_entries = max_entries;
1176 break;
1177 default:
1178 break;
1179 }
1180
1181 ilo_cp_begin(cp, cmd_len);
1182 ilo_cp_write(cp, cmd | (cmd_len - 2));
1183 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
1184 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
1185 num_entries);
1186 ilo_cp_end(cp);
1187 }
1188
1189 static inline void
1190 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
1191 int offset, int size, int entry_size,
1192 struct ilo_cp *cp)
1193 {
1194 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
1195 }
1196
1197 static inline void
1198 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
1199 int offset, int size, int entry_size,
1200 struct ilo_cp *cp)
1201 {
1202 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
1203 }
1204
1205 static inline void
1206 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
1207 int offset, int size, int entry_size,
1208 struct ilo_cp *cp)
1209 {
1210 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
1211 }
1212
1213 static inline void
1214 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
1215 int offset, int size, int entry_size,
1216 struct ilo_cp *cp)
1217 {
1218 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
1219 }
1220
1221 static inline void
1222 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
1223 int subop, int offset, int size,
1224 struct ilo_cp *cp)
1225 {
1226 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
1227 const uint8_t cmd_len = 2;
1228 int end;
1229
1230 ILO_GPE_VALID_GEN(dev, 7, 7);
1231
1232 /* VS, HS, DS, GS, and PS variants */
1233 assert(subop >= 0x12 && subop <= 0x16);
1234
1235 /*
1236 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
1237 *
1238 * "(A table that says the maximum size of each constant buffer is
1239 * 16KB")
1240 *
1241 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
1242 *
1243 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
1244 * may not exceed the maximum value of the Constant Buffer Size."
1245 *
1246 * Thus, the valid range of buffer end is [0KB, 16KB].
1247 */
1248 end = (offset + size) / 1024;
1249 if (end > 16) {
1250 assert(!"invalid constant buffer end");
1251 end = 16;
1252 }
1253
1254 /* the valid range of buffer offset is [0KB, 15KB] */
1255 offset = (offset + 1023) / 1024;
1256 if (offset > 15) {
1257 assert(!"invalid constant buffer offset");
1258 offset = 15;
1259 }
1260
1261 if (offset > end) {
1262 assert(!size);
1263 offset = end;
1264 }
1265
1266 /* the valid range of buffer size is [0KB, 15KB] */
1267 size = end - offset;
1268 if (size > 15) {
1269 assert(!"invalid constant buffer size");
1270 size = 15;
1271 }
1272
1273 ilo_cp_begin(cp, cmd_len);
1274 ilo_cp_write(cp, cmd | (cmd_len - 2));
1275 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
1276 size);
1277 ilo_cp_end(cp);
1278 }
1279
1280 static inline void
1281 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
1282 int offset, int size,
1283 struct ilo_cp *cp)
1284 {
1285 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
1286 }
1287
1288 static inline void
1289 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
1290 int offset, int size,
1291 struct ilo_cp *cp)
1292 {
1293 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
1294 }
1295
1296 static inline void
1297 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
1298 int offset, int size,
1299 struct ilo_cp *cp)
1300 {
1301 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
1302 }
1303
1304 static inline void
1305 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
1306 int offset, int size,
1307 struct ilo_cp *cp)
1308 {
1309 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
1310 }
1311
1312 static inline void
1313 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
1314 int offset, int size,
1315 struct ilo_cp *cp)
1316 {
1317 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
1318 }
1319
1320 static inline void
1321 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
1322 const struct pipe_stream_output_info *so_info,
1323 struct ilo_cp *cp)
1324 {
1325 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
1326 uint16_t cmd_len;
1327 int buffer_selects, num_entries, i;
1328 uint16_t so_decls[128];
1329
1330 ILO_GPE_VALID_GEN(dev, 7, 7);
1331
1332 buffer_selects = 0;
1333 num_entries = 0;
1334
1335 if (so_info) {
1336 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
1337
1338 memset(buffer_offsets, 0, sizeof(buffer_offsets));
1339
1340 for (i = 0; i < so_info->num_outputs; i++) {
1341 unsigned decl, buf, reg, mask;
1342
1343 buf = so_info->output[i].output_buffer;
1344
1345 /* pad with holes */
1346 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
1347 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1348 int num_dwords;
1349
1350 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1351 if (num_dwords > 4)
1352 num_dwords = 4;
1353
1354 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1355 SO_DECL_HOLE_FLAG |
1356 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1357
1358 so_decls[num_entries++] = decl;
1359 buffer_offsets[buf] += num_dwords;
1360 }
1361
1362 reg = so_info->output[i].register_index;
1363 mask = ((1 << so_info->output[i].num_components) - 1) <<
1364 so_info->output[i].start_component;
1365
1366 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1367 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1368 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1369
1370 so_decls[num_entries++] = decl;
1371 buffer_selects |= 1 << buf;
1372 buffer_offsets[buf] += so_info->output[i].num_components;
1373 }
1374 }
1375
1376 /*
1377 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1378 *
1379 * "Errata: All 128 decls for all four streams must be included
1380 * whenever this command is issued. The "Num Entries [n]" fields still
1381 * contain the actual numbers of valid decls."
1382 *
1383 * Also note that "DWord Length" has 9 bits for this command, and the type
1384 * of cmd_len is thus uint16_t.
1385 */
1386 cmd_len = 2 * 128 + 3;
1387
1388 ilo_cp_begin(cp, cmd_len);
1389 ilo_cp_write(cp, cmd | (cmd_len - 2));
1390 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1391 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1392 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1393 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1394 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1395 0 << SO_NUM_ENTRIES_2_SHIFT |
1396 0 << SO_NUM_ENTRIES_1_SHIFT |
1397 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1398
1399 for (i = 0; i < num_entries; i++) {
1400 ilo_cp_write(cp, so_decls[i]);
1401 ilo_cp_write(cp, 0);
1402 }
1403 for (; i < 128; i++) {
1404 ilo_cp_write(cp, 0);
1405 ilo_cp_write(cp, 0);
1406 }
1407
1408 ilo_cp_end(cp);
1409 }
1410
1411 static inline void
1412 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1413 int index, int base, int stride,
1414 const struct pipe_stream_output_target *so_target,
1415 struct ilo_cp *cp)
1416 {
1417 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1418 const uint8_t cmd_len = 4;
1419 struct ilo_buffer *buf;
1420 int end;
1421
1422 ILO_GPE_VALID_GEN(dev, 7, 7);
1423
1424 if (!so_target || !so_target->buffer) {
1425 ilo_cp_begin(cp, cmd_len);
1426 ilo_cp_write(cp, cmd | (cmd_len - 2));
1427 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1428 ilo_cp_write(cp, 0);
1429 ilo_cp_write(cp, 0);
1430 ilo_cp_end(cp);
1431 return;
1432 }
1433
1434 buf = ilo_buffer(so_target->buffer);
1435
1436 /* DWord-aligned */
1437 assert(stride % 4 == 0 && base % 4 == 0);
1438 assert(so_target->buffer_offset % 4 == 0);
1439
1440 stride &= ~3;
1441 base = (base + so_target->buffer_offset) & ~3;
1442 end = (base + so_target->buffer_size) & ~3;
1443
1444 ilo_cp_begin(cp, cmd_len);
1445 ilo_cp_write(cp, cmd | (cmd_len - 2));
1446 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1447 stride);
1448 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1449 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1450 ilo_cp_end(cp);
1451 }
1452
1453 static inline void
1454 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1455 const struct pipe_draw_info *info,
1456 const struct ilo_ib_state *ib,
1457 bool rectlist,
1458 struct ilo_cp *cp)
1459 {
1460 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1461 const uint8_t cmd_len = 7;
1462 const int prim = (rectlist) ?
1463 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1464 const int vb_access = (info->indexed) ?
1465 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1466 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1467 const uint32_t vb_start = info->start +
1468 ((info->indexed) ? ib->draw_start_offset : 0);
1469
1470 ILO_GPE_VALID_GEN(dev, 7, 7);
1471
1472 ilo_cp_begin(cp, cmd_len);
1473 ilo_cp_write(cp, cmd | (cmd_len - 2));
1474 ilo_cp_write(cp, vb_access | prim);
1475 ilo_cp_write(cp, info->count);
1476 ilo_cp_write(cp, vb_start);
1477 ilo_cp_write(cp, info->instance_count);
1478 ilo_cp_write(cp, info->start_instance);
1479 ilo_cp_write(cp, info->index_bias);
1480 ilo_cp_end(cp);
1481 }
1482
1483 static inline uint32_t
1484 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1485 const struct ilo_viewport_cso *viewports,
1486 unsigned num_viewports,
1487 struct ilo_cp *cp)
1488 {
1489 const int state_align = 64 / 4;
1490 const int state_len = 16 * num_viewports;
1491 uint32_t state_offset, *dw;
1492 unsigned i;
1493
1494 ILO_GPE_VALID_GEN(dev, 7, 7);
1495
1496 /*
1497 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1498 *
1499 * "The viewport-specific state used by both the SF and CL units
1500 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1501 * of which contains the DWords described below. The start of each
1502 * element is spaced 16 DWords apart. The location of first element of
1503 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1504 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1505 */
1506 assert(num_viewports && num_viewports <= 16);
1507
1508 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1509 state_len, state_align, &state_offset);
1510
1511 for (i = 0; i < num_viewports; i++) {
1512 const struct ilo_viewport_cso *vp = &viewports[i];
1513
1514 dw[0] = fui(vp->m00);
1515 dw[1] = fui(vp->m11);
1516 dw[2] = fui(vp->m22);
1517 dw[3] = fui(vp->m30);
1518 dw[4] = fui(vp->m31);
1519 dw[5] = fui(vp->m32);
1520 dw[6] = 0;
1521 dw[7] = 0;
1522 dw[8] = fui(vp->min_gbx);
1523 dw[9] = fui(vp->max_gbx);
1524 dw[10] = fui(vp->min_gby);
1525 dw[11] = fui(vp->max_gby);
1526 dw[12] = 0;
1527 dw[13] = 0;
1528 dw[14] = 0;
1529 dw[15] = 0;
1530
1531 dw += 16;
1532 }
1533
1534 return state_offset;
1535 }
1536
1537 #endif /* ILO_GPE_GEN7_H */