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ilo: make ilo_cp based on ilo_builder
[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "intel_winsys.h"
32
33 #include "ilo_common.h"
34 #include "ilo_cp.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
38
39 static inline void
40 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
41 struct ilo_cp *cp)
42 {
43 assert(!"GPGPU_WALKER unsupported");
44 }
45
46 static inline void
47 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
48 uint32_t clear_val,
49 struct ilo_cp *cp)
50 {
51 const uint8_t cmd_len = 3;
52 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
53 (cmd_len - 2);
54
55 ILO_GPE_VALID_GEN(dev, 7, 7.5);
56
57 ilo_cp_begin(cp, cmd_len);
58 ilo_cp_write(cp, dw0);
59 ilo_cp_write(cp, clear_val);
60 ilo_cp_write(cp, 1);
61 ilo_cp_end(cp);
62 }
63
64 static inline void
65 gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev,
66 bool enable_cut_index,
67 uint32_t cut_index,
68 struct ilo_cp *cp)
69 {
70 const uint8_t cmd_len = 2;
71 uint32_t dw0 = GEN75_RENDER_CMD(3D, 3DSTATE_VF) | (cmd_len - 2);
72
73 ILO_GPE_VALID_GEN(dev, 7.5, 7.5);
74
75 if (enable_cut_index)
76 dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
77
78 ilo_cp_begin(cp, cmd_len);
79 ilo_cp_write(cp, dw0);
80 ilo_cp_write(cp, cut_index);
81 ilo_cp_end(cp);
82 }
83
84 static inline void
85 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
86 int subop, uint32_t pointer,
87 struct ilo_cp *cp)
88 {
89 const uint8_t cmd_len = 2;
90 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
91 GEN6_RENDER_SUBTYPE_3D |
92 subop | (cmd_len - 2);
93
94 ILO_GPE_VALID_GEN(dev, 7, 7.5);
95
96 ilo_cp_begin(cp, cmd_len);
97 ilo_cp_write(cp, dw0);
98 ilo_cp_write(cp, pointer);
99 ilo_cp_end(cp);
100 }
101
102 static inline void
103 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
104 uint32_t color_calc_state,
105 struct ilo_cp *cp)
106 {
107 gen7_emit_3dstate_pointer(dev,
108 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state, cp);
109 }
110
111 static inline void
112 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
113 const struct ilo_shader_state *gs,
114 int num_samplers,
115 struct ilo_cp *cp)
116 {
117 const uint8_t cmd_len = 7;
118 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
119 const struct ilo_shader_cso *cso;
120 uint32_t dw2, dw4, dw5;
121
122 ILO_GPE_VALID_GEN(dev, 7, 7.5);
123
124 if (!gs) {
125 ilo_cp_begin(cp, cmd_len);
126 ilo_cp_write(cp, dw0);
127 ilo_cp_write(cp, 0);
128 ilo_cp_write(cp, 0);
129 ilo_cp_write(cp, 0);
130 ilo_cp_write(cp, 0);
131 ilo_cp_write(cp, GEN7_GS_DW5_STATISTICS);
132 ilo_cp_write(cp, 0);
133 ilo_cp_end(cp);
134 return;
135 }
136
137 cso = ilo_shader_get_kernel_cso(gs);
138 dw2 = cso->payload[0];
139 dw4 = cso->payload[1];
140 dw5 = cso->payload[2];
141
142 dw2 |= ((num_samplers + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
143
144 ilo_cp_begin(cp, cmd_len);
145 ilo_cp_write(cp, dw0);
146 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
147 ilo_cp_write(cp, dw2);
148 ilo_cp_write(cp, 0); /* scratch */
149 ilo_cp_write(cp, dw4);
150 ilo_cp_write(cp, dw5);
151 ilo_cp_write(cp, 0);
152 ilo_cp_end(cp);
153 }
154
155 static inline void
156 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
157 const struct ilo_rasterizer_state *rasterizer,
158 enum pipe_format zs_format,
159 struct ilo_cp *cp)
160 {
161 const uint8_t cmd_len = 7;
162 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
163 const int num_samples = 1;
164 uint32_t payload[6];
165
166 ILO_GPE_VALID_GEN(dev, 7, 7.5);
167
168 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
169 rasterizer, num_samples, zs_format,
170 payload, Elements(payload));
171
172 ilo_cp_begin(cp, cmd_len);
173 ilo_cp_write(cp, dw0);
174 ilo_cp_write_multi(cp, payload, 6);
175 ilo_cp_end(cp);
176 }
177
178 static inline void
179 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
180 const struct ilo_shader_state *fs,
181 const struct ilo_rasterizer_state *rasterizer,
182 bool cc_may_kill, uint32_t hiz_op,
183 struct ilo_cp *cp)
184 {
185 const uint8_t cmd_len = 3;
186 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
187 const int num_samples = 1;
188 uint32_t dw1, dw2;
189
190 ILO_GPE_VALID_GEN(dev, 7, 7.5);
191
192 /* see ilo_gpe_init_rasterizer_wm() */
193 if (rasterizer) {
194 dw1 = rasterizer->wm.payload[0];
195 dw2 = rasterizer->wm.payload[1];
196
197 assert(!hiz_op);
198 dw1 |= GEN7_WM_DW1_STATISTICS;
199 }
200 else {
201 dw1 = hiz_op;
202 dw2 = 0;
203 }
204
205 if (fs) {
206 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
207
208 dw1 |= fs_cso->payload[3];
209 }
210
211 if (cc_may_kill)
212 dw1 |= GEN7_WM_DW1_PS_ENABLE | GEN7_WM_DW1_PS_KILL;
213
214 if (num_samples > 1) {
215 dw1 |= rasterizer->wm.dw_msaa_rast;
216 dw2 |= rasterizer->wm.dw_msaa_disp;
217 }
218
219 ilo_cp_begin(cp, cmd_len);
220 ilo_cp_write(cp, dw0);
221 ilo_cp_write(cp, dw1);
222 ilo_cp_write(cp, dw2);
223 ilo_cp_end(cp);
224 }
225
226 static inline void
227 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
228 int subop,
229 const uint32_t *bufs, const int *sizes,
230 int num_bufs,
231 struct ilo_cp *cp)
232 {
233 const uint8_t cmd_len = 7;
234 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
235 GEN6_RENDER_SUBTYPE_3D |
236 subop | (cmd_len - 2);
237 uint32_t dw[6];
238 int total_read_length, i;
239
240 ILO_GPE_VALID_GEN(dev, 7, 7.5);
241
242 /* VS, HS, DS, GS, and PS variants */
243 assert(subop >= GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS &&
244 subop <= GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS &&
245 subop != GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK);
246
247 assert(num_bufs <= 4);
248
249 dw[0] = 0;
250 dw[1] = 0;
251
252 total_read_length = 0;
253 for (i = 0; i < 4; i++) {
254 int read_len;
255
256 /*
257 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
258 *
259 * "Constant buffers must be enabled in order from Constant Buffer 0
260 * to Constant Buffer 3 within this command. For example, it is
261 * not allowed to enable Constant Buffer 1 by programming a
262 * non-zero value in the VS Constant Buffer 1 Read Length without a
263 * non-zero value in VS Constant Buffer 0 Read Length."
264 */
265 if (i >= num_bufs || !sizes[i]) {
266 for (; i < 4; i++) {
267 assert(i >= num_bufs || !sizes[i]);
268 dw[2 + i] = 0;
269 }
270 break;
271 }
272
273 /* read lengths are in 256-bit units */
274 read_len = (sizes[i] + 31) / 32;
275 /* the lower 5 bits are used for memory object control state */
276 assert(bufs[i] % 32 == 0);
277
278 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
279 dw[2 + i] = bufs[i];
280
281 total_read_length += read_len;
282 }
283
284 /*
285 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
286 *
287 * "The sum of all four read length fields must be less than or equal
288 * to the size of 64"
289 */
290 assert(total_read_length <= 64);
291
292 ilo_cp_begin(cp, cmd_len);
293 ilo_cp_write(cp, dw0);
294 ilo_cp_write_multi(cp, dw, 6);
295 ilo_cp_end(cp);
296 }
297
298 static inline void
299 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
300 const uint32_t *bufs, const int *sizes,
301 int num_bufs,
302 struct ilo_cp *cp)
303 {
304 gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
305 bufs, sizes, num_bufs, cp);
306 }
307
308 static inline void
309 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
310 const uint32_t *bufs, const int *sizes,
311 int num_bufs,
312 struct ilo_cp *cp)
313 {
314 gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
315 bufs, sizes, num_bufs, cp);
316 }
317
318 static inline void
319 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
320 const uint32_t *bufs, const int *sizes,
321 int num_bufs,
322 struct ilo_cp *cp)
323 {
324 gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
325 bufs, sizes, num_bufs, cp);
326 }
327
328 static inline void
329 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
330 unsigned sample_mask,
331 int num_samples,
332 struct ilo_cp *cp)
333 {
334 const uint8_t cmd_len = 2;
335 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
336 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) |
337 (cmd_len - 2);
338
339 ILO_GPE_VALID_GEN(dev, 7, 7.5);
340
341 /*
342 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
343 *
344 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
345 * (Sample Mask) must be zero.
346 *
347 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
348 * must be zero."
349 */
350 sample_mask &= valid_mask;
351
352 ilo_cp_begin(cp, cmd_len);
353 ilo_cp_write(cp, dw0);
354 ilo_cp_write(cp, sample_mask);
355 ilo_cp_end(cp);
356 }
357
358 static inline void
359 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
360 const uint32_t *bufs, const int *sizes,
361 int num_bufs,
362 struct ilo_cp *cp)
363 {
364 gen7_emit_3dstate_constant(dev, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS,
365 bufs, sizes, num_bufs, cp);
366 }
367
368 static inline void
369 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
370 const uint32_t *bufs, const int *sizes,
371 int num_bufs,
372 struct ilo_cp *cp)
373 {
374 gen7_emit_3dstate_constant(dev, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS,
375 bufs, sizes, num_bufs, cp);
376 }
377
378 static inline void
379 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
380 const struct ilo_shader_state *hs,
381 int num_samplers,
382 struct ilo_cp *cp)
383 {
384 const uint8_t cmd_len = 7;
385 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
386
387 ILO_GPE_VALID_GEN(dev, 7, 7.5);
388
389 assert(!hs);
390
391 ilo_cp_begin(cp, cmd_len);
392 ilo_cp_write(cp, dw0);
393 ilo_cp_write(cp, 0);
394 ilo_cp_write(cp, 0);
395 ilo_cp_write(cp, 0);
396 ilo_cp_write(cp, 0);
397 ilo_cp_write(cp, 0);
398 ilo_cp_write(cp, 0);
399 ilo_cp_end(cp);
400 }
401
402 static inline void
403 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
404 struct ilo_cp *cp)
405 {
406 const uint8_t cmd_len = 4;
407 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (cmd_len - 2);
408
409 ILO_GPE_VALID_GEN(dev, 7, 7.5);
410
411 ilo_cp_begin(cp, cmd_len);
412 ilo_cp_write(cp, dw0);
413 ilo_cp_write(cp, 0);
414 ilo_cp_write(cp, 0);
415 ilo_cp_write(cp, 0);
416 ilo_cp_end(cp);
417 }
418
419 static inline void
420 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
421 const struct ilo_shader_state *ds,
422 int num_samplers,
423 struct ilo_cp *cp)
424 {
425 const uint8_t cmd_len = 6;
426 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
427
428 ILO_GPE_VALID_GEN(dev, 7, 7.5);
429
430 assert(!ds);
431
432 ilo_cp_begin(cp, cmd_len);
433 ilo_cp_write(cp, dw0);
434 ilo_cp_write(cp, 0);
435 ilo_cp_write(cp, 0);
436 ilo_cp_write(cp, 0);
437 ilo_cp_write(cp, 0);
438 ilo_cp_write(cp, 0);
439 ilo_cp_end(cp);
440
441 }
442
443 static inline void
444 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
445 unsigned buffer_mask,
446 int vertex_attrib_count,
447 bool rasterizer_discard,
448 struct ilo_cp *cp)
449 {
450 const uint8_t cmd_len = 3;
451 const bool enable = (buffer_mask != 0);
452 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT) |
453 (cmd_len - 2);
454 uint32_t dw1, dw2;
455 int read_len;
456
457 ILO_GPE_VALID_GEN(dev, 7, 7.5);
458
459 if (!enable) {
460 dw1 = 0 << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT;
461 if (rasterizer_discard)
462 dw1 |= GEN7_SO_DW1_RENDER_DISABLE;
463
464 dw2 = 0;
465
466 ilo_cp_begin(cp, cmd_len);
467 ilo_cp_write(cp, dw0);
468 ilo_cp_write(cp, dw1);
469 ilo_cp_write(cp, dw2);
470 ilo_cp_end(cp);
471 return;
472 }
473
474 read_len = (vertex_attrib_count + 1) / 2;
475 if (!read_len)
476 read_len = 1;
477
478 dw1 = GEN7_SO_DW1_SO_ENABLE |
479 0 << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT |
480 GEN7_SO_DW1_STATISTICS |
481 buffer_mask << 8;
482
483 if (rasterizer_discard)
484 dw1 |= GEN7_SO_DW1_RENDER_DISABLE;
485
486 /* API_OPENGL */
487 if (true)
488 dw1 |= GEN7_SO_DW1_REORDER_TRAILING;
489
490 dw2 = 0 << GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT |
491 0 << GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT |
492 0 << GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT |
493 0 << GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT |
494 0 << GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT |
495 0 << GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT |
496 0 << GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT |
497 (read_len - 1) << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT;
498
499 ilo_cp_begin(cp, cmd_len);
500 ilo_cp_write(cp, dw0);
501 ilo_cp_write(cp, dw1);
502 ilo_cp_write(cp, dw2);
503 ilo_cp_end(cp);
504 }
505
506 static inline void
507 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
508 const struct ilo_rasterizer_state *rasterizer,
509 const struct ilo_shader_state *fs,
510 struct ilo_cp *cp)
511 {
512 const uint8_t cmd_len = 14;
513 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
514 uint32_t dw[13];
515
516 ILO_GPE_VALID_GEN(dev, 7, 7.5);
517
518 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer, fs, dw, Elements(dw));
519
520 ilo_cp_begin(cp, cmd_len);
521 ilo_cp_write(cp, dw0);
522 ilo_cp_write_multi(cp, dw, 13);
523 ilo_cp_end(cp);
524 }
525
526 static inline void
527 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
528 const struct ilo_shader_state *fs,
529 int num_samplers, bool dual_blend,
530 struct ilo_cp *cp)
531 {
532 const uint8_t cmd_len = 8;
533 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
534 const struct ilo_shader_cso *cso;
535 uint32_t dw2, dw4, dw5;
536
537 ILO_GPE_VALID_GEN(dev, 7, 7.5);
538
539 if (!fs) {
540 int max_threads;
541
542 /* GPU hangs if none of the dispatch enable bits is set */
543 dw4 = GEN7_PS_DW4_8_PIXEL_DISPATCH;
544
545 /* see brwCreateContext() */
546 switch (dev->gen) {
547 case ILO_GEN(7.5):
548 max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
549 dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
550 break;
551 case ILO_GEN(7):
552 default:
553 max_threads = (dev->gt == 2) ? 172 : 48;
554 dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
555 break;
556 }
557
558 ilo_cp_begin(cp, cmd_len);
559 ilo_cp_write(cp, dw0);
560 ilo_cp_write(cp, 0);
561 ilo_cp_write(cp, 0);
562 ilo_cp_write(cp, 0);
563 ilo_cp_write(cp, dw4);
564 ilo_cp_write(cp, 0);
565 ilo_cp_write(cp, 0);
566 ilo_cp_write(cp, 0);
567 ilo_cp_end(cp);
568
569 return;
570 }
571
572 cso = ilo_shader_get_kernel_cso(fs);
573 dw2 = cso->payload[0];
574 dw4 = cso->payload[1];
575 dw5 = cso->payload[2];
576
577 dw2 |= (num_samplers + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
578
579 if (dual_blend)
580 dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
581
582 ilo_cp_begin(cp, cmd_len);
583 ilo_cp_write(cp, dw0);
584 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
585 ilo_cp_write(cp, dw2);
586 ilo_cp_write(cp, 0); /* scratch */
587 ilo_cp_write(cp, dw4);
588 ilo_cp_write(cp, dw5);
589 ilo_cp_write(cp, 0); /* kernel 1 */
590 ilo_cp_write(cp, 0); /* kernel 2 */
591 ilo_cp_end(cp);
592 }
593
594 static inline void
595 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
596 uint32_t sf_clip_viewport,
597 struct ilo_cp *cp)
598 {
599 gen7_emit_3dstate_pointer(dev,
600 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
601 sf_clip_viewport, cp);
602 }
603
604 static inline void
605 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
606 uint32_t cc_viewport,
607 struct ilo_cp *cp)
608 {
609 gen7_emit_3dstate_pointer(dev,
610 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
611 cc_viewport, cp);
612 }
613
614 static inline void
615 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
616 uint32_t blend_state,
617 struct ilo_cp *cp)
618 {
619 gen7_emit_3dstate_pointer(dev,
620 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
621 blend_state, cp);
622 }
623
624 static inline void
625 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
626 uint32_t depth_stencil_state,
627 struct ilo_cp *cp)
628 {
629 gen7_emit_3dstate_pointer(dev,
630 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
631 depth_stencil_state, cp);
632 }
633
634 static inline void
635 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
636 uint32_t binding_table,
637 struct ilo_cp *cp)
638 {
639 gen7_emit_3dstate_pointer(dev,
640 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS,
641 binding_table, cp);
642 }
643
644 static inline void
645 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
646 uint32_t binding_table,
647 struct ilo_cp *cp)
648 {
649 gen7_emit_3dstate_pointer(dev,
650 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS,
651 binding_table, cp);
652 }
653
654 static inline void
655 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
656 uint32_t binding_table,
657 struct ilo_cp *cp)
658 {
659 gen7_emit_3dstate_pointer(dev,
660 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS,
661 binding_table, cp);
662 }
663
664 static inline void
665 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
666 uint32_t binding_table,
667 struct ilo_cp *cp)
668 {
669 gen7_emit_3dstate_pointer(dev,
670 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS,
671 binding_table, cp);
672 }
673
674 static inline void
675 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
676 uint32_t binding_table,
677 struct ilo_cp *cp)
678 {
679 gen7_emit_3dstate_pointer(dev,
680 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
681 binding_table, cp);
682 }
683
684 static inline void
685 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
686 uint32_t sampler_state,
687 struct ilo_cp *cp)
688 {
689 gen7_emit_3dstate_pointer(dev,
690 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS,
691 sampler_state, cp);
692 }
693
694 static inline void
695 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
696 uint32_t sampler_state,
697 struct ilo_cp *cp)
698 {
699 gen7_emit_3dstate_pointer(dev,
700 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS,
701 sampler_state, cp);
702 }
703
704 static inline void
705 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
706 uint32_t sampler_state,
707 struct ilo_cp *cp)
708 {
709 gen7_emit_3dstate_pointer(dev,
710 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS,
711 sampler_state, cp);
712 }
713
714 static inline void
715 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
716 uint32_t sampler_state,
717 struct ilo_cp *cp)
718 {
719 gen7_emit_3dstate_pointer(dev,
720 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS,
721 sampler_state, cp);
722 }
723
724 static inline void
725 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
726 uint32_t sampler_state,
727 struct ilo_cp *cp)
728 {
729 gen7_emit_3dstate_pointer(dev,
730 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
731 sampler_state, cp);
732 }
733
734 static inline void
735 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
736 int subop, int offset, int size,
737 int entry_size,
738 struct ilo_cp *cp)
739 {
740 const uint8_t cmd_len = 2;
741 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
742 GEN6_RENDER_SUBTYPE_3D |
743 subop | (cmd_len - 2);
744 const int row_size = 64; /* 512 bits */
745 int alloc_size, num_entries, min_entries, max_entries;
746
747 ILO_GPE_VALID_GEN(dev, 7, 7.5);
748
749 /* VS, HS, DS, and GS variants */
750 assert(subop >= GEN7_RENDER_OPCODE_3DSTATE_URB_VS &&
751 subop <= GEN7_RENDER_OPCODE_3DSTATE_URB_GS);
752
753 /* in multiples of 8KB */
754 assert(offset % 8192 == 0);
755 offset /= 8192;
756
757 /* in multiple of 512-bit rows */
758 alloc_size = (entry_size + row_size - 1) / row_size;
759 if (!alloc_size)
760 alloc_size = 1;
761
762 /*
763 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
764 *
765 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
766 * cause performance to decrease due to banking in the URB. Element
767 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
768 */
769 if (subop == GEN7_RENDER_OPCODE_3DSTATE_URB_VS && alloc_size == 5)
770 alloc_size = 6;
771
772 /* in multiples of 8 */
773 num_entries = (size / row_size / alloc_size) & ~7;
774
775 switch (subop) {
776 case GEN7_RENDER_OPCODE_3DSTATE_URB_VS:
777 switch (dev->gen) {
778 case ILO_GEN(7.5):
779 max_entries = (dev->gt >= 2) ? 1664 : 640;
780 min_entries = (dev->gt >= 2) ? 64 : 32;
781 break;
782 case ILO_GEN(7):
783 default:
784 max_entries = (dev->gt == 2) ? 704 : 512;
785 min_entries = 32;
786 break;
787 }
788
789 assert(num_entries >= min_entries);
790 if (num_entries > max_entries)
791 num_entries = max_entries;
792 break;
793 case GEN7_RENDER_OPCODE_3DSTATE_URB_HS:
794 max_entries = (dev->gt == 2) ? 64 : 32;
795 if (num_entries > max_entries)
796 num_entries = max_entries;
797 break;
798 case GEN7_RENDER_OPCODE_3DSTATE_URB_DS:
799 if (num_entries)
800 assert(num_entries >= 138);
801 break;
802 case GEN7_RENDER_OPCODE_3DSTATE_URB_GS:
803 switch (dev->gen) {
804 case ILO_GEN(7.5):
805 max_entries = (dev->gt >= 2) ? 640 : 256;
806 break;
807 case ILO_GEN(7):
808 default:
809 max_entries = (dev->gt == 2) ? 320 : 192;
810 break;
811 }
812
813 if (num_entries > max_entries)
814 num_entries = max_entries;
815 break;
816 default:
817 break;
818 }
819
820 ilo_cp_begin(cp, cmd_len);
821 ilo_cp_write(cp, dw0);
822 ilo_cp_write(cp, offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT |
823 (alloc_size - 1) << GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT |
824 num_entries);
825 ilo_cp_end(cp);
826 }
827
828 static inline void
829 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
830 int offset, int size, int entry_size,
831 struct ilo_cp *cp)
832 {
833 gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_VS,
834 offset, size, entry_size, cp);
835 }
836
837 static inline void
838 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
839 int offset, int size, int entry_size,
840 struct ilo_cp *cp)
841 {
842 gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_HS,
843 offset, size, entry_size, cp);
844 }
845
846 static inline void
847 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
848 int offset, int size, int entry_size,
849 struct ilo_cp *cp)
850 {
851 gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_DS,
852 offset, size, entry_size, cp);
853 }
854
855 static inline void
856 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
857 int offset, int size, int entry_size,
858 struct ilo_cp *cp)
859 {
860 gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_GS,
861 offset, size, entry_size, cp);
862 }
863
864 static inline void
865 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
866 int subop, int offset, int size,
867 struct ilo_cp *cp)
868 {
869 const uint8_t cmd_len = 2;
870 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
871 GEN6_RENDER_SUBTYPE_3D |
872 subop | (cmd_len - 2);
873 int end;
874
875 ILO_GPE_VALID_GEN(dev, 7, 7.5);
876
877 /* VS, HS, DS, GS, and PS variants */
878 assert(subop >= GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS &&
879 subop <= GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS);
880
881 /*
882 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
883 *
884 * "(A table that says the maximum size of each constant buffer is
885 * 16KB")
886 *
887 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
888 *
889 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
890 * may not exceed the maximum value of the Constant Buffer Size."
891 *
892 * Thus, the valid range of buffer end is [0KB, 16KB].
893 */
894 end = (offset + size) / 1024;
895 if (end > 16) {
896 assert(!"invalid constant buffer end");
897 end = 16;
898 }
899
900 /* the valid range of buffer offset is [0KB, 15KB] */
901 offset = (offset + 1023) / 1024;
902 if (offset > 15) {
903 assert(!"invalid constant buffer offset");
904 offset = 15;
905 }
906
907 if (offset > end) {
908 assert(!size);
909 offset = end;
910 }
911
912 /* the valid range of buffer size is [0KB, 15KB] */
913 size = end - offset;
914 if (size > 15) {
915 assert(!"invalid constant buffer size");
916 size = 15;
917 }
918
919 ilo_cp_begin(cp, cmd_len);
920 ilo_cp_write(cp, dw0);
921 ilo_cp_write(cp, offset << GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT |
922 size);
923 ilo_cp_end(cp);
924 }
925
926 static inline void
927 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
928 int offset, int size,
929 struct ilo_cp *cp)
930 {
931 gen7_emit_3dstate_push_constant_alloc(dev,
932 GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS, offset, size, cp);
933 }
934
935 static inline void
936 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
937 int offset, int size,
938 struct ilo_cp *cp)
939 {
940 gen7_emit_3dstate_push_constant_alloc(dev,
941 GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS, offset, size, cp);
942 }
943
944 static inline void
945 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
946 int offset, int size,
947 struct ilo_cp *cp)
948 {
949 gen7_emit_3dstate_push_constant_alloc(dev,
950 GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS, offset, size, cp);
951 }
952
953 static inline void
954 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
955 int offset, int size,
956 struct ilo_cp *cp)
957 {
958 gen7_emit_3dstate_push_constant_alloc(dev,
959 GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS, offset, size, cp);
960 }
961
962 static inline void
963 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
964 int offset, int size,
965 struct ilo_cp *cp)
966 {
967 gen7_emit_3dstate_push_constant_alloc(dev,
968 GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS, offset, size, cp);
969 }
970
971 static inline void
972 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
973 const struct pipe_stream_output_info *so_info,
974 struct ilo_cp *cp)
975 {
976 uint16_t cmd_len;
977 uint32_t dw0;
978 int buffer_selects, num_entries, i;
979 uint16_t so_decls[128];
980
981 ILO_GPE_VALID_GEN(dev, 7, 7.5);
982
983 buffer_selects = 0;
984 num_entries = 0;
985
986 if (so_info) {
987 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
988
989 memset(buffer_offsets, 0, sizeof(buffer_offsets));
990
991 for (i = 0; i < so_info->num_outputs; i++) {
992 unsigned decl, buf, reg, mask;
993
994 buf = so_info->output[i].output_buffer;
995
996 /* pad with holes */
997 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
998 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
999 int num_dwords;
1000
1001 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1002 if (num_dwords > 4)
1003 num_dwords = 4;
1004
1005 decl = buf << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT |
1006 GEN7_SO_DECL_HOLE_FLAG |
1007 ((1 << num_dwords) - 1) << GEN7_SO_DECL_COMPONENT_MASK__SHIFT;
1008
1009 so_decls[num_entries++] = decl;
1010 buffer_offsets[buf] += num_dwords;
1011 }
1012
1013 reg = so_info->output[i].register_index;
1014 mask = ((1 << so_info->output[i].num_components) - 1) <<
1015 so_info->output[i].start_component;
1016
1017 decl = buf << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT |
1018 reg << GEN7_SO_DECL_REG_INDEX__SHIFT |
1019 mask << GEN7_SO_DECL_COMPONENT_MASK__SHIFT;
1020
1021 so_decls[num_entries++] = decl;
1022 buffer_selects |= 1 << buf;
1023 buffer_offsets[buf] += so_info->output[i].num_components;
1024 }
1025 }
1026
1027 /*
1028 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1029 *
1030 * "Errata: All 128 decls for all four streams must be included
1031 * whenever this command is issued. The "Num Entries [n]" fields still
1032 * contain the actual numbers of valid decls."
1033 *
1034 * Also note that "DWord Length" has 9 bits for this command, and the type
1035 * of cmd_len is thus uint16_t.
1036 */
1037 cmd_len = 2 * 128 + 3;
1038 dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST) | (cmd_len - 2);
1039
1040 ilo_cp_begin(cp, cmd_len);
1041 ilo_cp_write(cp, dw0);
1042 ilo_cp_write(cp, 0 << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT |
1043 0 << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT |
1044 0 << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT |
1045 buffer_selects << GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT);
1046 ilo_cp_write(cp, 0 << GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT |
1047 0 << GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT |
1048 0 << GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT |
1049 num_entries << GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT);
1050
1051 for (i = 0; i < num_entries; i++) {
1052 ilo_cp_write(cp, so_decls[i]);
1053 ilo_cp_write(cp, 0);
1054 }
1055 for (; i < 128; i++) {
1056 ilo_cp_write(cp, 0);
1057 ilo_cp_write(cp, 0);
1058 }
1059
1060 ilo_cp_end(cp);
1061 }
1062
1063 static inline void
1064 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1065 int index, int base, int stride,
1066 const struct pipe_stream_output_target *so_target,
1067 struct ilo_cp *cp)
1068 {
1069 const uint8_t cmd_len = 4;
1070 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) |
1071 (cmd_len - 2);
1072 struct ilo_buffer *buf;
1073 int end;
1074
1075 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1076
1077 if (!so_target || !so_target->buffer) {
1078 ilo_cp_begin(cp, cmd_len);
1079 ilo_cp_write(cp, dw0);
1080 ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT);
1081 ilo_cp_write(cp, 0);
1082 ilo_cp_write(cp, 0);
1083 ilo_cp_end(cp);
1084 return;
1085 }
1086
1087 buf = ilo_buffer(so_target->buffer);
1088
1089 /* DWord-aligned */
1090 assert(stride % 4 == 0 && base % 4 == 0);
1091 assert(so_target->buffer_offset % 4 == 0);
1092
1093 stride &= ~3;
1094 base = (base + so_target->buffer_offset) & ~3;
1095 end = (base + so_target->buffer_size) & ~3;
1096
1097 ilo_cp_begin(cp, cmd_len);
1098 ilo_cp_write(cp, dw0);
1099 ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT |
1100 stride);
1101 ilo_cp_write_bo(cp, base, buf->bo, INTEL_RELOC_WRITE);
1102 ilo_cp_write_bo(cp, end, buf->bo, INTEL_RELOC_WRITE);
1103 ilo_cp_end(cp);
1104 }
1105
1106 static inline void
1107 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1108 const struct pipe_draw_info *info,
1109 const struct ilo_ib_state *ib,
1110 bool rectlist,
1111 struct ilo_cp *cp)
1112 {
1113 const uint8_t cmd_len = 7;
1114 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
1115 const int prim = (rectlist) ?
1116 GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1117 const int vb_access = (info->indexed) ?
1118 GEN7_3DPRIM_DW1_ACCESS_RANDOM :
1119 GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL;
1120 const uint32_t vb_start = info->start +
1121 ((info->indexed) ? ib->draw_start_offset : 0);
1122
1123 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1124
1125 ilo_cp_begin(cp, cmd_len);
1126 ilo_cp_write(cp, dw0);
1127 ilo_cp_write(cp, vb_access | prim);
1128 ilo_cp_write(cp, info->count);
1129 ilo_cp_write(cp, vb_start);
1130 ilo_cp_write(cp, info->instance_count);
1131 ilo_cp_write(cp, info->start_instance);
1132 ilo_cp_write(cp, info->index_bias);
1133 ilo_cp_end(cp);
1134 }
1135
1136 static inline uint32_t
1137 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1138 const struct ilo_viewport_cso *viewports,
1139 unsigned num_viewports,
1140 struct ilo_cp *cp)
1141 {
1142 const int state_align = 64 / 4;
1143 const int state_len = 16 * num_viewports;
1144 uint32_t state_offset, *dw;
1145 unsigned i;
1146
1147 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1148
1149 /*
1150 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1151 *
1152 * "The viewport-specific state used by both the SF and CL units
1153 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1154 * of which contains the DWords described below. The start of each
1155 * element is spaced 16 DWords apart. The location of first element of
1156 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1157 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1158 */
1159 assert(num_viewports && num_viewports <= 16);
1160
1161 dw = ilo_cp_steal_ptr(cp, ILO_BUILDER_ITEM_SF_VIEWPORT,
1162 state_len, state_align, &state_offset);
1163
1164 for (i = 0; i < num_viewports; i++) {
1165 const struct ilo_viewport_cso *vp = &viewports[i];
1166
1167 dw[0] = fui(vp->m00);
1168 dw[1] = fui(vp->m11);
1169 dw[2] = fui(vp->m22);
1170 dw[3] = fui(vp->m30);
1171 dw[4] = fui(vp->m31);
1172 dw[5] = fui(vp->m32);
1173 dw[6] = 0;
1174 dw[7] = 0;
1175 dw[8] = fui(vp->min_gbx);
1176 dw[9] = fui(vp->max_gbx);
1177 dw[10] = fui(vp->min_gby);
1178 dw[11] = fui(vp->max_gby);
1179 dw[12] = 0;
1180 dw[13] = 0;
1181 dw[14] = 0;
1182 dw[15] = 0;
1183
1184 dw += 16;
1185 }
1186
1187 return state_offset;
1188 }
1189
1190 #endif /* ILO_GPE_GEN7_H */