2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
31 #include "intel_winsys.h"
33 #include "ilo_common.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
40 * Commands that GEN7 GPE could emit.
42 enum ilo_gpe_gen7_command
{
43 ILO_GPE_GEN7_STATE_BASE_ADDRESS
, /* (0x0, 0x1, 0x01) */
44 ILO_GPE_GEN7_STATE_SIP
, /* (0x0, 0x1, 0x02) */
45 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS
, /* (0x1, 0x0, 0x0b) */
46 ILO_GPE_GEN7_PIPELINE_SELECT
, /* (0x1, 0x1, 0x04) */
47 ILO_GPE_GEN7_MEDIA_VFE_STATE
, /* (0x2, 0x0, 0x00) */
48 ILO_GPE_GEN7_MEDIA_CURBE_LOAD
, /* (0x2, 0x0, 0x01) */
49 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD
, /* (0x2, 0x0, 0x02) */
50 ILO_GPE_GEN7_MEDIA_STATE_FLUSH
, /* (0x2, 0x0, 0x04) */
51 ILO_GPE_GEN7_GPGPU_WALKER
, /* (0x2, 0x1, 0x05) */
52 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS
, /* (0x3, 0x0, 0x04) */
53 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER
, /* (0x3, 0x0, 0x05) */
54 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER
, /* (0x3, 0x0, 0x06) */
55 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER
, /* (0x3, 0x0, 0x07) */
56 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS
, /* (0x3, 0x0, 0x08) */
57 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS
, /* (0x3, 0x0, 0x09) */
58 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER
, /* (0x3, 0x0, 0x0a) */
59 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS
, /* (0x3, 0x0, 0x0e) */
60 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS
, /* (0x3, 0x0, 0x0f) */
61 ILO_GPE_GEN7_3DSTATE_VS
, /* (0x3, 0x0, 0x10) */
62 ILO_GPE_GEN7_3DSTATE_GS
, /* (0x3, 0x0, 0x11) */
63 ILO_GPE_GEN7_3DSTATE_CLIP
, /* (0x3, 0x0, 0x12) */
64 ILO_GPE_GEN7_3DSTATE_SF
, /* (0x3, 0x0, 0x13) */
65 ILO_GPE_GEN7_3DSTATE_WM
, /* (0x3, 0x0, 0x14) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS
, /* (0x3, 0x0, 0x15) */
67 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS
, /* (0x3, 0x0, 0x16) */
68 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS
, /* (0x3, 0x0, 0x17) */
69 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK
, /* (0x3, 0x0, 0x18) */
70 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS
, /* (0x3, 0x0, 0x19) */
71 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS
, /* (0x3, 0x0, 0x1a) */
72 ILO_GPE_GEN7_3DSTATE_HS
, /* (0x3, 0x0, 0x1b) */
73 ILO_GPE_GEN7_3DSTATE_TE
, /* (0x3, 0x0, 0x1c) */
74 ILO_GPE_GEN7_3DSTATE_DS
, /* (0x3, 0x0, 0x1d) */
75 ILO_GPE_GEN7_3DSTATE_STREAMOUT
, /* (0x3, 0x0, 0x1e) */
76 ILO_GPE_GEN7_3DSTATE_SBE
, /* (0x3, 0x0, 0x1f) */
77 ILO_GPE_GEN7_3DSTATE_PS
, /* (0x3, 0x0, 0x20) */
78 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
, /* (0x3, 0x0, 0x21) */
79 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC
, /* (0x3, 0x0, 0x23) */
80 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS
, /* (0x3, 0x0, 0x24) */
81 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
, /* (0x3, 0x0, 0x25) */
82 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS
, /* (0x3, 0x0, 0x26) */
83 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS
, /* (0x3, 0x0, 0x27) */
84 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS
, /* (0x3, 0x0, 0x28) */
85 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS
, /* (0x3, 0x0, 0x29) */
86 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS
, /* (0x3, 0x0, 0x2a) */
87 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS
, /* (0x3, 0x0, 0x2b) */
88 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS
, /* (0x3, 0x0, 0x2c) */
89 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS
, /* (0x3, 0x0, 0x2d) */
90 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS
, /* (0x3, 0x0, 0x2e) */
91 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS
, /* (0x3, 0x0, 0x2f) */
92 ILO_GPE_GEN7_3DSTATE_URB_VS
, /* (0x3, 0x0, 0x30) */
93 ILO_GPE_GEN7_3DSTATE_URB_HS
, /* (0x3, 0x0, 0x31) */
94 ILO_GPE_GEN7_3DSTATE_URB_DS
, /* (0x3, 0x0, 0x32) */
95 ILO_GPE_GEN7_3DSTATE_URB_GS
, /* (0x3, 0x0, 0x33) */
96 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE
, /* (0x3, 0x1, 0x00) */
97 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET
, /* (0x3, 0x1, 0x06) */
98 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN
, /* (0x3, 0x1, 0x07) */
99 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE
, /* (0x3, 0x1, 0x08) */
100 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS
, /* (0x3, 0x1, 0x0a) */
101 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE
, /* (0x3, 0x1, 0x0d) */
102 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
, /* (0x3, 0x1, 0x12) */
103 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS
, /* (0x3, 0x1, 0x13) */
104 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS
, /* (0x3, 0x1, 0x14) */
105 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
, /* (0x3, 0x1, 0x15) */
106 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
, /* (0x3, 0x1, 0x16) */
107 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST
, /* (0x3, 0x1, 0x17) */
108 ILO_GPE_GEN7_3DSTATE_SO_BUFFER
, /* (0x3, 0x1, 0x18) */
109 ILO_GPE_GEN7_PIPE_CONTROL
, /* (0x3, 0x2, 0x00) */
110 ILO_GPE_GEN7_3DPRIMITIVE
, /* (0x3, 0x3, 0x00) */
112 ILO_GPE_GEN7_COMMAND_COUNT
,
116 * Indirect states that GEN7 GPE could emit.
118 enum ilo_gpe_gen7_state
{
119 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA
,
120 ILO_GPE_GEN7_SF_CLIP_VIEWPORT
,
121 ILO_GPE_GEN7_CC_VIEWPORT
,
122 ILO_GPE_GEN7_COLOR_CALC_STATE
,
123 ILO_GPE_GEN7_BLEND_STATE
,
124 ILO_GPE_GEN7_DEPTH_STENCIL_STATE
,
125 ILO_GPE_GEN7_SCISSOR_RECT
,
126 ILO_GPE_GEN7_BINDING_TABLE_STATE
,
127 ILO_GPE_GEN7_SURFACE_STATE
,
128 ILO_GPE_GEN7_SAMPLER_STATE
,
129 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE
,
130 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER
,
132 ILO_GPE_GEN7_STATE_COUNT
,
136 * GEN7 graphics processing engine
140 struct ilo_gpe_gen7
{
141 int (*estimate_command_size
)(const struct ilo_dev_info
*dev
,
142 enum ilo_gpe_gen7_command cmd
,
145 int (*estimate_state_size
)(const struct ilo_dev_info
*dev
,
146 enum ilo_gpe_gen7_state state
,
150 const struct ilo_gpe_gen7
*
151 ilo_gpe_gen7_get(void);
154 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info
*dev
,
157 assert(!"GPGPU_WALKER unsupported");
161 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info
*dev
,
165 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x04);
166 const uint8_t cmd_len
= 3;
168 ILO_GPE_VALID_GEN(dev
, 7, 7);
170 ilo_cp_begin(cp
, cmd_len
);
171 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
172 ilo_cp_write(cp
, clear_val
);
178 gen7_emit_3dstate_pointer(const struct ilo_dev_info
*dev
,
179 int subop
, uint32_t pointer
,
182 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
183 const uint8_t cmd_len
= 2;
185 ILO_GPE_VALID_GEN(dev
, 7, 7);
187 ilo_cp_begin(cp
, cmd_len
);
188 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
189 ilo_cp_write(cp
, pointer
);
194 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info
*dev
,
195 uint32_t color_calc_state
,
198 gen7_emit_3dstate_pointer(dev
, 0x0e, color_calc_state
, cp
);
202 gen7_emit_3DSTATE_GS(const struct ilo_dev_info
*dev
,
203 const struct ilo_shader_state
*gs
,
207 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x11);
208 const uint8_t cmd_len
= 7;
209 const struct ilo_shader_cso
*cso
;
210 uint32_t dw2
, dw4
, dw5
;
212 ILO_GPE_VALID_GEN(dev
, 7, 7);
215 ilo_cp_begin(cp
, cmd_len
);
216 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
221 ilo_cp_write(cp
, GEN6_GS_STATISTICS_ENABLE
);
227 cso
= ilo_shader_get_kernel_cso(gs
);
228 dw2
= cso
->payload
[0];
229 dw4
= cso
->payload
[1];
230 dw5
= cso
->payload
[2];
232 dw2
|= ((num_samplers
+ 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT
;
234 ilo_cp_begin(cp
, cmd_len
);
235 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
236 ilo_cp_write(cp
, ilo_shader_get_kernel_offset(gs
));
237 ilo_cp_write(cp
, dw2
);
238 ilo_cp_write(cp
, 0); /* scratch */
239 ilo_cp_write(cp
, dw4
);
240 ilo_cp_write(cp
, dw5
);
246 gen7_emit_3DSTATE_SF(const struct ilo_dev_info
*dev
,
247 const struct ilo_rasterizer_state
*rasterizer
,
248 const struct pipe_surface
*zs_surf
,
251 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x13);
252 const uint8_t cmd_len
= 7;
253 const int num_samples
= 1;
256 ILO_GPE_VALID_GEN(dev
, 7, 7);
258 ilo_gpe_gen6_fill_3dstate_sf_raster(dev
,
259 rasterizer
, num_samples
,
260 (zs_surf
) ? zs_surf
->format
: PIPE_FORMAT_NONE
,
261 payload
, Elements(payload
));
263 ilo_cp_begin(cp
, cmd_len
);
264 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
265 ilo_cp_write_multi(cp
, payload
, 6);
270 gen7_emit_3DSTATE_WM(const struct ilo_dev_info
*dev
,
271 const struct ilo_shader_state
*fs
,
272 const struct ilo_rasterizer_state
*rasterizer
,
276 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x14);
277 const uint8_t cmd_len
= 3;
278 const int num_samples
= 1;
281 ILO_GPE_VALID_GEN(dev
, 7, 7);
283 /* see ilo_gpe_init_rasterizer_wm() */
284 dw1
= rasterizer
->wm
.payload
[0];
285 dw2
= rasterizer
->wm
.payload
[1];
287 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
290 dw1
|= GEN7_WM_DEPTH_CLEAR
;
291 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
292 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
296 const struct ilo_shader_cso
*fs_cso
= ilo_shader_get_kernel_cso(fs
);
298 dw1
|= fs_cso
->payload
[3];
302 dw1
|= GEN7_WM_DISPATCH_ENABLE
|
306 if (num_samples
> 1) {
307 dw1
|= rasterizer
->wm
.dw_msaa_rast
;
308 dw2
|= rasterizer
->wm
.dw_msaa_disp
;
311 ilo_cp_begin(cp
, cmd_len
);
312 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
313 ilo_cp_write(cp
, dw1
);
314 ilo_cp_write(cp
, dw2
);
319 gen7_emit_3dstate_constant(const struct ilo_dev_info
*dev
,
321 const uint32_t *bufs
, const int *sizes
,
325 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
326 const uint8_t cmd_len
= 7;
328 int total_read_length
, i
;
330 ILO_GPE_VALID_GEN(dev
, 7, 7);
332 /* VS, HS, DS, GS, and PS variants */
333 assert(subop
>= 0x15 && subop
<= 0x1a && subop
!= 0x18);
335 assert(num_bufs
<= 4);
340 total_read_length
= 0;
341 for (i
= 0; i
< 4; i
++) {
345 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
347 * "Constant buffers must be enabled in order from Constant Buffer 0
348 * to Constant Buffer 3 within this command. For example, it is
349 * not allowed to enable Constant Buffer 1 by programming a
350 * non-zero value in the VS Constant Buffer 1 Read Length without a
351 * non-zero value in VS Constant Buffer 0 Read Length."
353 if (i
>= num_bufs
|| !sizes
[i
]) {
355 assert(i
>= num_bufs
|| !sizes
[i
]);
361 /* read lengths are in 256-bit units */
362 read_len
= (sizes
[i
] + 31) / 32;
363 /* the lower 5 bits are used for memory object control state */
364 assert(bufs
[i
] % 32 == 0);
366 dw
[i
/ 2] |= read_len
<< ((i
% 2) ? 16 : 0);
369 total_read_length
+= read_len
;
373 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
375 * "The sum of all four read length fields must be less than or equal
378 assert(total_read_length
<= 64);
380 ilo_cp_begin(cp
, cmd_len
);
381 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
382 ilo_cp_write_multi(cp
, dw
, 6);
387 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info
*dev
,
388 const uint32_t *bufs
, const int *sizes
,
392 gen7_emit_3dstate_constant(dev
, 0x15, bufs
, sizes
, num_bufs
, cp
);
396 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info
*dev
,
397 const uint32_t *bufs
, const int *sizes
,
401 gen7_emit_3dstate_constant(dev
, 0x16, bufs
, sizes
, num_bufs
, cp
);
405 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info
*dev
,
406 const uint32_t *bufs
, const int *sizes
,
410 gen7_emit_3dstate_constant(dev
, 0x17, bufs
, sizes
, num_bufs
, cp
);
414 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info
*dev
,
415 unsigned sample_mask
,
419 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x18);
420 const uint8_t cmd_len
= 2;
421 const unsigned valid_mask
= ((1 << num_samples
) - 1) | 0x1;
423 ILO_GPE_VALID_GEN(dev
, 7, 7);
426 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
428 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
429 * (Sample Mask) must be zero.
431 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
434 sample_mask
&= valid_mask
;
436 ilo_cp_begin(cp
, cmd_len
);
437 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
438 ilo_cp_write(cp
, sample_mask
);
443 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info
*dev
,
444 const uint32_t *bufs
, const int *sizes
,
448 gen7_emit_3dstate_constant(dev
, 0x19, bufs
, sizes
, num_bufs
, cp
);
452 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info
*dev
,
453 const uint32_t *bufs
, const int *sizes
,
457 gen7_emit_3dstate_constant(dev
, 0x1a, bufs
, sizes
, num_bufs
, cp
);
461 gen7_emit_3DSTATE_HS(const struct ilo_dev_info
*dev
,
462 const struct ilo_shader_state
*hs
,
466 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1b);
467 const uint8_t cmd_len
= 7;
469 ILO_GPE_VALID_GEN(dev
, 7, 7);
473 ilo_cp_begin(cp
, cmd_len
);
474 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
485 gen7_emit_3DSTATE_TE(const struct ilo_dev_info
*dev
,
488 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1c);
489 const uint8_t cmd_len
= 4;
491 ILO_GPE_VALID_GEN(dev
, 7, 7);
493 ilo_cp_begin(cp
, cmd_len
);
494 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
502 gen7_emit_3DSTATE_DS(const struct ilo_dev_info
*dev
,
503 const struct ilo_shader_state
*ds
,
507 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1d);
508 const uint8_t cmd_len
= 6;
510 ILO_GPE_VALID_GEN(dev
, 7, 7);
514 ilo_cp_begin(cp
, cmd_len
);
515 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
526 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info
*dev
,
527 unsigned buffer_mask
,
528 int vertex_attrib_count
,
529 bool rasterizer_discard
,
532 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1e);
533 const uint8_t cmd_len
= 3;
534 const bool enable
= (buffer_mask
!= 0);
538 ILO_GPE_VALID_GEN(dev
, 7, 7);
541 dw1
= 0 << SO_RENDER_STREAM_SELECT_SHIFT
;
542 if (rasterizer_discard
)
543 dw1
|= SO_RENDERING_DISABLE
;
547 ilo_cp_begin(cp
, cmd_len
);
548 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
549 ilo_cp_write(cp
, dw1
);
550 ilo_cp_write(cp
, dw2
);
555 read_len
= (vertex_attrib_count
+ 1) / 2;
559 dw1
= SO_FUNCTION_ENABLE
|
560 0 << SO_RENDER_STREAM_SELECT_SHIFT
|
561 SO_STATISTICS_ENABLE
|
564 if (rasterizer_discard
)
565 dw1
|= SO_RENDERING_DISABLE
;
569 dw1
|= SO_REORDER_TRAILING
;
571 dw2
= 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT
|
572 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT
|
573 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT
|
574 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT
|
575 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT
|
576 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT
|
577 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT
|
578 (read_len
- 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT
;
580 ilo_cp_begin(cp
, cmd_len
);
581 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
582 ilo_cp_write(cp
, dw1
);
583 ilo_cp_write(cp
, dw2
);
588 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info
*dev
,
589 const struct ilo_rasterizer_state
*rasterizer
,
590 const struct ilo_shader_state
*fs
,
591 const struct ilo_shader_state
*last_sh
,
594 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x1f);
595 const uint8_t cmd_len
= 14;
598 ILO_GPE_VALID_GEN(dev
, 7, 7);
600 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev
, rasterizer
,
601 fs
, last_sh
, dw
, Elements(dw
));
603 ilo_cp_begin(cp
, cmd_len
);
604 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
605 ilo_cp_write_multi(cp
, dw
, 13);
610 gen7_emit_3DSTATE_PS(const struct ilo_dev_info
*dev
,
611 const struct ilo_shader_state
*fs
,
612 int num_samplers
, bool dual_blend
,
615 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, 0x20);
616 const uint8_t cmd_len
= 8;
617 const struct ilo_shader_cso
*cso
;
618 uint32_t dw2
, dw4
, dw5
;
620 ILO_GPE_VALID_GEN(dev
, 7, 7);
623 /* see brwCreateContext() */
624 const int max_threads
= (dev
->gt
== 2) ? 172 : 48;
626 ilo_cp_begin(cp
, cmd_len
);
627 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
631 /* GPU hangs if none of the dispatch enable bits is set */
632 ilo_cp_write(cp
, (max_threads
- 1) << IVB_PS_MAX_THREADS_SHIFT
|
633 GEN7_PS_8_DISPATCH_ENABLE
);
642 cso
= ilo_shader_get_kernel_cso(fs
);
643 dw2
= cso
->payload
[0];
644 dw4
= cso
->payload
[1];
645 dw5
= cso
->payload
[2];
647 dw2
|= (num_samplers
+ 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT
;
650 dw4
|= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE
;
652 ilo_cp_begin(cp
, cmd_len
);
653 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
654 ilo_cp_write(cp
, ilo_shader_get_kernel_offset(fs
));
655 ilo_cp_write(cp
, dw2
);
656 ilo_cp_write(cp
, 0); /* scratch */
657 ilo_cp_write(cp
, dw4
);
658 ilo_cp_write(cp
, dw5
);
659 ilo_cp_write(cp
, 0); /* kernel 1 */
660 ilo_cp_write(cp
, 0); /* kernel 2 */
665 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info
*dev
,
666 uint32_t sf_clip_viewport
,
669 gen7_emit_3dstate_pointer(dev
, 0x21, sf_clip_viewport
, cp
);
673 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info
*dev
,
674 uint32_t cc_viewport
,
677 gen7_emit_3dstate_pointer(dev
, 0x23, cc_viewport
, cp
);
681 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info
*dev
,
682 uint32_t blend_state
,
685 gen7_emit_3dstate_pointer(dev
, 0x24, blend_state
, cp
);
689 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info
*dev
,
690 uint32_t depth_stencil_state
,
693 gen7_emit_3dstate_pointer(dev
, 0x25, depth_stencil_state
, cp
);
697 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info
*dev
,
698 uint32_t binding_table
,
701 gen7_emit_3dstate_pointer(dev
, 0x26, binding_table
, cp
);
705 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info
*dev
,
706 uint32_t binding_table
,
709 gen7_emit_3dstate_pointer(dev
, 0x27, binding_table
, cp
);
713 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info
*dev
,
714 uint32_t binding_table
,
717 gen7_emit_3dstate_pointer(dev
, 0x28, binding_table
, cp
);
721 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info
*dev
,
722 uint32_t binding_table
,
725 gen7_emit_3dstate_pointer(dev
, 0x29, binding_table
, cp
);
729 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info
*dev
,
730 uint32_t binding_table
,
733 gen7_emit_3dstate_pointer(dev
, 0x2a, binding_table
, cp
);
737 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info
*dev
,
738 uint32_t sampler_state
,
741 gen7_emit_3dstate_pointer(dev
, 0x2b, sampler_state
, cp
);
745 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info
*dev
,
746 uint32_t sampler_state
,
749 gen7_emit_3dstate_pointer(dev
, 0x2c, sampler_state
, cp
);
753 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info
*dev
,
754 uint32_t sampler_state
,
757 gen7_emit_3dstate_pointer(dev
, 0x2d, sampler_state
, cp
);
761 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info
*dev
,
762 uint32_t sampler_state
,
765 gen7_emit_3dstate_pointer(dev
, 0x2e, sampler_state
, cp
);
769 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info
*dev
,
770 uint32_t sampler_state
,
773 gen7_emit_3dstate_pointer(dev
, 0x2f, sampler_state
, cp
);
777 gen7_emit_3dstate_urb(const struct ilo_dev_info
*dev
,
778 int subop
, int offset
, int size
,
782 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x0, subop
);
783 const uint8_t cmd_len
= 2;
784 const int row_size
= 64; /* 512 bits */
785 int alloc_size
, num_entries
, min_entries
, max_entries
;
787 ILO_GPE_VALID_GEN(dev
, 7, 7);
789 /* VS, HS, DS, and GS variants */
790 assert(subop
>= 0x30 && subop
<= 0x33);
792 /* in multiples of 8KB */
793 assert(offset
% 8192 == 0);
796 /* in multiple of 512-bit rows */
797 alloc_size
= (entry_size
+ row_size
- 1) / row_size
;
802 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
804 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
805 * cause performance to decrease due to banking in the URB. Element
806 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
808 if (subop
== 0x30 && alloc_size
== 5)
811 /* in multiples of 8 */
812 num_entries
= (size
/ row_size
/ alloc_size
) & ~7;
815 case 0x30: /* 3DSTATE_URB_VS */
817 max_entries
= (dev
->gt
== 2) ? 704 : 512;
819 assert(num_entries
>= min_entries
);
820 if (num_entries
> max_entries
)
821 num_entries
= max_entries
;
823 case 0x31: /* 3DSTATE_URB_HS */
824 max_entries
= (dev
->gt
== 2) ? 64 : 32;
825 if (num_entries
> max_entries
)
826 num_entries
= max_entries
;
828 case 0x32: /* 3DSTATE_URB_DS */
830 assert(num_entries
>= 138);
832 case 0x33: /* 3DSTATE_URB_GS */
833 max_entries
= (dev
->gt
== 2) ? 320 : 192;
834 if (num_entries
> max_entries
)
835 num_entries
= max_entries
;
841 ilo_cp_begin(cp
, cmd_len
);
842 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
843 ilo_cp_write(cp
, offset
<< GEN7_URB_STARTING_ADDRESS_SHIFT
|
844 (alloc_size
- 1) << GEN7_URB_ENTRY_SIZE_SHIFT
|
850 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info
*dev
,
851 int offset
, int size
, int entry_size
,
854 gen7_emit_3dstate_urb(dev
, 0x30, offset
, size
, entry_size
, cp
);
858 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info
*dev
,
859 int offset
, int size
, int entry_size
,
862 gen7_emit_3dstate_urb(dev
, 0x31, offset
, size
, entry_size
, cp
);
866 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info
*dev
,
867 int offset
, int size
, int entry_size
,
870 gen7_emit_3dstate_urb(dev
, 0x32, offset
, size
, entry_size
, cp
);
874 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info
*dev
,
875 int offset
, int size
, int entry_size
,
878 gen7_emit_3dstate_urb(dev
, 0x33, offset
, size
, entry_size
, cp
);
882 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info
*dev
,
883 int subop
, int offset
, int size
,
886 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, subop
);
887 const uint8_t cmd_len
= 2;
890 ILO_GPE_VALID_GEN(dev
, 7, 7);
892 /* VS, HS, DS, GS, and PS variants */
893 assert(subop
>= 0x12 && subop
<= 0x16);
896 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
898 * "(A table that says the maximum size of each constant buffer is
901 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
903 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
904 * may not exceed the maximum value of the Constant Buffer Size."
906 * Thus, the valid range of buffer end is [0KB, 16KB].
908 end
= (offset
+ size
) / 1024;
910 assert(!"invalid constant buffer end");
914 /* the valid range of buffer offset is [0KB, 15KB] */
915 offset
= (offset
+ 1023) / 1024;
917 assert(!"invalid constant buffer offset");
926 /* the valid range of buffer size is [0KB, 15KB] */
929 assert(!"invalid constant buffer size");
933 ilo_cp_begin(cp
, cmd_len
);
934 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
935 ilo_cp_write(cp
, offset
<< GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT
|
941 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info
*dev
,
942 int offset
, int size
,
945 gen7_emit_3dstate_push_constant_alloc(dev
, 0x12, offset
, size
, cp
);
949 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info
*dev
,
950 int offset
, int size
,
953 gen7_emit_3dstate_push_constant_alloc(dev
, 0x13, offset
, size
, cp
);
957 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info
*dev
,
958 int offset
, int size
,
961 gen7_emit_3dstate_push_constant_alloc(dev
, 0x14, offset
, size
, cp
);
965 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info
*dev
,
966 int offset
, int size
,
969 gen7_emit_3dstate_push_constant_alloc(dev
, 0x15, offset
, size
, cp
);
973 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info
*dev
,
974 int offset
, int size
,
977 gen7_emit_3dstate_push_constant_alloc(dev
, 0x16, offset
, size
, cp
);
981 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info
*dev
,
982 const struct pipe_stream_output_info
*so_info
,
985 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, 0x17);
987 int buffer_selects
, num_entries
, i
;
988 uint16_t so_decls
[128];
990 ILO_GPE_VALID_GEN(dev
, 7, 7);
996 int buffer_offsets
[PIPE_MAX_SO_BUFFERS
];
998 memset(buffer_offsets
, 0, sizeof(buffer_offsets
));
1000 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
1001 unsigned decl
, buf
, reg
, mask
;
1003 buf
= so_info
->output
[i
].output_buffer
;
1005 /* pad with holes */
1006 assert(buffer_offsets
[buf
] <= so_info
->output
[i
].dst_offset
);
1007 while (buffer_offsets
[buf
] < so_info
->output
[i
].dst_offset
) {
1010 num_dwords
= so_info
->output
[i
].dst_offset
- buffer_offsets
[buf
];
1014 decl
= buf
<< SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT
|
1016 ((1 << num_dwords
) - 1) << SO_DECL_COMPONENT_MASK_SHIFT
;
1018 so_decls
[num_entries
++] = decl
;
1019 buffer_offsets
[buf
] += num_dwords
;
1022 reg
= so_info
->output
[i
].register_index
;
1023 mask
= ((1 << so_info
->output
[i
].num_components
) - 1) <<
1024 so_info
->output
[i
].start_component
;
1026 decl
= buf
<< SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT
|
1027 reg
<< SO_DECL_REGISTER_INDEX_SHIFT
|
1028 mask
<< SO_DECL_COMPONENT_MASK_SHIFT
;
1030 so_decls
[num_entries
++] = decl
;
1031 buffer_selects
|= 1 << buf
;
1032 buffer_offsets
[buf
] += so_info
->output
[i
].num_components
;
1037 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1039 * "Errata: All 128 decls for all four streams must be included
1040 * whenever this command is issued. The "Num Entries [n]" fields still
1041 * contain the actual numbers of valid decls."
1043 * Also note that "DWord Length" has 9 bits for this command, and the type
1044 * of cmd_len is thus uint16_t.
1046 cmd_len
= 2 * 128 + 3;
1048 ilo_cp_begin(cp
, cmd_len
);
1049 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1050 ilo_cp_write(cp
, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT
|
1051 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT
|
1052 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT
|
1053 buffer_selects
<< SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT
);
1054 ilo_cp_write(cp
, 0 << SO_NUM_ENTRIES_3_SHIFT
|
1055 0 << SO_NUM_ENTRIES_2_SHIFT
|
1056 0 << SO_NUM_ENTRIES_1_SHIFT
|
1057 num_entries
<< SO_NUM_ENTRIES_0_SHIFT
);
1059 for (i
= 0; i
< num_entries
; i
++) {
1060 ilo_cp_write(cp
, so_decls
[i
]);
1061 ilo_cp_write(cp
, 0);
1063 for (; i
< 128; i
++) {
1064 ilo_cp_write(cp
, 0);
1065 ilo_cp_write(cp
, 0);
1072 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info
*dev
,
1073 int index
, int base
, int stride
,
1074 const struct pipe_stream_output_target
*so_target
,
1077 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x1, 0x18);
1078 const uint8_t cmd_len
= 4;
1079 struct ilo_buffer
*buf
;
1082 ILO_GPE_VALID_GEN(dev
, 7, 7);
1084 if (!so_target
|| !so_target
->buffer
) {
1085 ilo_cp_begin(cp
, cmd_len
);
1086 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1087 ilo_cp_write(cp
, index
<< SO_BUFFER_INDEX_SHIFT
);
1088 ilo_cp_write(cp
, 0);
1089 ilo_cp_write(cp
, 0);
1094 buf
= ilo_buffer(so_target
->buffer
);
1097 assert(stride
% 4 == 0 && base
% 4 == 0);
1098 assert(so_target
->buffer_offset
% 4 == 0);
1101 base
= (base
+ so_target
->buffer_offset
) & ~3;
1102 end
= (base
+ so_target
->buffer_size
) & ~3;
1104 ilo_cp_begin(cp
, cmd_len
);
1105 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1106 ilo_cp_write(cp
, index
<< SO_BUFFER_INDEX_SHIFT
|
1108 ilo_cp_write_bo(cp
, base
, buf
->bo
, INTEL_DOMAIN_RENDER
, INTEL_DOMAIN_RENDER
);
1109 ilo_cp_write_bo(cp
, end
, buf
->bo
, INTEL_DOMAIN_RENDER
, INTEL_DOMAIN_RENDER
);
1114 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info
*dev
,
1115 const struct pipe_draw_info
*info
,
1116 const struct ilo_ib_state
*ib
,
1120 const uint32_t cmd
= ILO_GPE_CMD(0x3, 0x3, 0x00);
1121 const uint8_t cmd_len
= 7;
1122 const int prim
= (rectlist
) ?
1123 _3DPRIM_RECTLIST
: ilo_gpe_gen6_translate_pipe_prim(info
->mode
);
1124 const int vb_access
= (info
->indexed
) ?
1125 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
1126 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
1127 const uint32_t vb_start
= info
->start
+
1128 ((info
->indexed
) ? ib
->draw_start_offset
: 0);
1130 ILO_GPE_VALID_GEN(dev
, 7, 7);
1132 ilo_cp_begin(cp
, cmd_len
);
1133 ilo_cp_write(cp
, cmd
| (cmd_len
- 2));
1134 ilo_cp_write(cp
, vb_access
| prim
);
1135 ilo_cp_write(cp
, info
->count
);
1136 ilo_cp_write(cp
, vb_start
);
1137 ilo_cp_write(cp
, info
->instance_count
);
1138 ilo_cp_write(cp
, info
->start_instance
);
1139 ilo_cp_write(cp
, info
->index_bias
);
1143 static inline uint32_t
1144 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info
*dev
,
1145 const struct ilo_viewport_cso
*viewports
,
1146 unsigned num_viewports
,
1149 const int state_align
= 64 / 4;
1150 const int state_len
= 16 * num_viewports
;
1151 uint32_t state_offset
, *dw
;
1154 ILO_GPE_VALID_GEN(dev
, 7, 7);
1157 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1159 * "The viewport-specific state used by both the SF and CL units
1160 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1161 * of which contains the DWords described below. The start of each
1162 * element is spaced 16 DWords apart. The location of first element of
1163 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1164 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1166 assert(num_viewports
&& num_viewports
<= 16);
1168 dw
= ilo_cp_steal_ptr(cp
, "SF_CLIP_VIEWPORT",
1169 state_len
, state_align
, &state_offset
);
1171 for (i
= 0; i
< num_viewports
; i
++) {
1172 const struct ilo_viewport_cso
*vp
= &viewports
[i
];
1174 dw
[0] = fui(vp
->m00
);
1175 dw
[1] = fui(vp
->m11
);
1176 dw
[2] = fui(vp
->m22
);
1177 dw
[3] = fui(vp
->m30
);
1178 dw
[4] = fui(vp
->m31
);
1179 dw
[5] = fui(vp
->m32
);
1182 dw
[8] = fui(vp
->min_gbx
);
1183 dw
[9] = fui(vp
->max_gbx
);
1184 dw
[10] = fui(vp
->min_gby
);
1185 dw
[11] = fui(vp
->max_gby
);
1194 return state_offset
;
1197 #endif /* ILO_GPE_GEN7_H */