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ilo: Call GPE emit functions directly.
[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "ilo_common.h"
32 #include "ilo_gpe_gen6.h"
33
34 /**
35 * Commands that GEN7 GPE could emit.
36 */
37 enum ilo_gpe_gen7_command {
38 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
39 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
40 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
41 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
42 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
43 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
44 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
45 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
46 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
47 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
48 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
49 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
50 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
51 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
52 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
53 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
54 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
55 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
56 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
57 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
58 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
59 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
60 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
61 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
62 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
63 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
64 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
65 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
66 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
67 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
68 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
69 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
70 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
71 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
72 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
73 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
74 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
75 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
76 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
77 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
78 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
79 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
80 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
81 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
82 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
83 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
84 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
85 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
86 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
87 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
88 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
89 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
90 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
91 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
92 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
93 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
94 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
95 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
96 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
97 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
98 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
99 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
100 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
101 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
102 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
103 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
104 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
105 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
106
107 ILO_GPE_GEN7_COMMAND_COUNT,
108 };
109
110 /**
111 * Indirect states that GEN7 GPE could emit.
112 */
113 enum ilo_gpe_gen7_state {
114 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
115 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
116 ILO_GPE_GEN7_CC_VIEWPORT,
117 ILO_GPE_GEN7_COLOR_CALC_STATE,
118 ILO_GPE_GEN7_BLEND_STATE,
119 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
120 ILO_GPE_GEN7_SCISSOR_RECT,
121 ILO_GPE_GEN7_BINDING_TABLE_STATE,
122 ILO_GPE_GEN7_SURFACE_STATE,
123 ILO_GPE_GEN7_SAMPLER_STATE,
124 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
125 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
126
127 ILO_GPE_GEN7_STATE_COUNT,
128 };
129
130 /**
131 * GEN7 graphics processing engine
132 *
133 * \see ilo_gpe_gen6
134 */
135 struct ilo_gpe_gen7 {
136 int (*estimate_command_size)(const struct ilo_dev_info *dev,
137 enum ilo_gpe_gen7_command cmd,
138 int arg);
139
140 int (*estimate_state_size)(const struct ilo_dev_info *dev,
141 enum ilo_gpe_gen7_state state,
142 int arg);
143 };
144
145 const struct ilo_gpe_gen7 *
146 ilo_gpe_gen7_get(void);
147
148 static inline void
149 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
150 struct ilo_cp *cp)
151 {
152 assert(!"GPGPU_WALKER unsupported");
153 }
154
155 static inline void
156 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
157 uint32_t clear_val,
158 struct ilo_cp *cp)
159 {
160 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
161 const uint8_t cmd_len = 3;
162
163 ILO_GPE_VALID_GEN(dev, 7, 7);
164
165 ilo_cp_begin(cp, cmd_len);
166 ilo_cp_write(cp, cmd | (cmd_len - 2));
167 ilo_cp_write(cp, clear_val);
168 ilo_cp_write(cp, 1);
169 ilo_cp_end(cp);
170 }
171
172 static inline void
173 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
174 int subop, uint32_t pointer,
175 struct ilo_cp *cp)
176 {
177 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
178 const uint8_t cmd_len = 2;
179
180 ILO_GPE_VALID_GEN(dev, 7, 7);
181
182 ilo_cp_begin(cp, cmd_len);
183 ilo_cp_write(cp, cmd | (cmd_len - 2));
184 ilo_cp_write(cp, pointer);
185 ilo_cp_end(cp);
186 }
187
188 static inline void
189 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
190 uint32_t color_calc_state,
191 struct ilo_cp *cp)
192 {
193 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
194 }
195
196 static inline void
197 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
198 const struct ilo_shader_state *gs,
199 int num_samplers,
200 struct ilo_cp *cp)
201 {
202 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
203 const uint8_t cmd_len = 7;
204 const struct ilo_shader_cso *cso;
205 uint32_t dw2, dw4, dw5;
206
207 ILO_GPE_VALID_GEN(dev, 7, 7);
208
209 if (!gs) {
210 ilo_cp_begin(cp, cmd_len);
211 ilo_cp_write(cp, cmd | (cmd_len - 2));
212 ilo_cp_write(cp, 0);
213 ilo_cp_write(cp, 0);
214 ilo_cp_write(cp, 0);
215 ilo_cp_write(cp, 0);
216 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
217 ilo_cp_write(cp, 0);
218 ilo_cp_end(cp);
219 return;
220 }
221
222 cso = ilo_shader_get_kernel_cso(gs);
223 dw2 = cso->payload[0];
224 dw4 = cso->payload[1];
225 dw5 = cso->payload[2];
226
227 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
228
229 ilo_cp_begin(cp, cmd_len);
230 ilo_cp_write(cp, cmd | (cmd_len - 2));
231 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
232 ilo_cp_write(cp, dw2);
233 ilo_cp_write(cp, 0); /* scratch */
234 ilo_cp_write(cp, dw4);
235 ilo_cp_write(cp, dw5);
236 ilo_cp_write(cp, 0);
237 ilo_cp_end(cp);
238 }
239
240 static inline void
241 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
242 const struct ilo_rasterizer_state *rasterizer,
243 const struct pipe_surface *zs_surf,
244 struct ilo_cp *cp)
245 {
246 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
247 const uint8_t cmd_len = 7;
248 const int num_samples = 1;
249 uint32_t payload[6];
250
251 ILO_GPE_VALID_GEN(dev, 7, 7);
252
253 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
254 rasterizer, num_samples,
255 (zs_surf) ? zs_surf->format : PIPE_FORMAT_NONE,
256 payload, Elements(payload));
257
258 ilo_cp_begin(cp, cmd_len);
259 ilo_cp_write(cp, cmd | (cmd_len - 2));
260 ilo_cp_write_multi(cp, payload, 6);
261 ilo_cp_end(cp);
262 }
263
264 static inline void
265 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
266 const struct ilo_shader_state *fs,
267 const struct ilo_rasterizer_state *rasterizer,
268 bool cc_may_kill,
269 struct ilo_cp *cp)
270 {
271 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
272 const uint8_t cmd_len = 3;
273 const int num_samples = 1;
274 uint32_t dw1, dw2;
275
276 ILO_GPE_VALID_GEN(dev, 7, 7);
277
278 /* see ilo_gpe_init_rasterizer_wm() */
279 dw1 = rasterizer->wm.payload[0];
280 dw2 = rasterizer->wm.payload[1];
281
282 dw1 |= GEN7_WM_STATISTICS_ENABLE;
283
284 if (false) {
285 dw1 |= GEN7_WM_DEPTH_CLEAR;
286 dw1 |= GEN7_WM_DEPTH_RESOLVE;
287 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
288 }
289
290 if (fs) {
291 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
292
293 dw1 |= fs_cso->payload[3];
294 }
295
296 if (cc_may_kill) {
297 dw1 |= GEN7_WM_DISPATCH_ENABLE |
298 GEN7_WM_KILL_ENABLE;
299 }
300
301 if (num_samples > 1) {
302 dw1 |= rasterizer->wm.dw_msaa_rast;
303 dw2 |= rasterizer->wm.dw_msaa_disp;
304 }
305
306 ilo_cp_begin(cp, cmd_len);
307 ilo_cp_write(cp, cmd | (cmd_len - 2));
308 ilo_cp_write(cp, dw1);
309 ilo_cp_write(cp, dw2);
310 ilo_cp_end(cp);
311 }
312
313 static inline void
314 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
315 int subop,
316 const uint32_t *bufs, const int *sizes,
317 int num_bufs,
318 struct ilo_cp *cp)
319 {
320 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
321 const uint8_t cmd_len = 7;
322 uint32_t dw[6];
323 int total_read_length, i;
324
325 ILO_GPE_VALID_GEN(dev, 7, 7);
326
327 /* VS, HS, DS, GS, and PS variants */
328 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
329
330 assert(num_bufs <= 4);
331
332 dw[0] = 0;
333 dw[1] = 0;
334
335 total_read_length = 0;
336 for (i = 0; i < 4; i++) {
337 int read_len;
338
339 /*
340 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
341 *
342 * "Constant buffers must be enabled in order from Constant Buffer 0
343 * to Constant Buffer 3 within this command. For example, it is
344 * not allowed to enable Constant Buffer 1 by programming a
345 * non-zero value in the VS Constant Buffer 1 Read Length without a
346 * non-zero value in VS Constant Buffer 0 Read Length."
347 */
348 if (i >= num_bufs || !sizes[i]) {
349 for (; i < 4; i++) {
350 assert(i >= num_bufs || !sizes[i]);
351 dw[2 + i] = 0;
352 }
353 break;
354 }
355
356 /* read lengths are in 256-bit units */
357 read_len = (sizes[i] + 31) / 32;
358 /* the lower 5 bits are used for memory object control state */
359 assert(bufs[i] % 32 == 0);
360
361 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
362 dw[2 + i] = bufs[i];
363
364 total_read_length += read_len;
365 }
366
367 /*
368 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
369 *
370 * "The sum of all four read length fields must be less than or equal
371 * to the size of 64"
372 */
373 assert(total_read_length <= 64);
374
375 ilo_cp_begin(cp, cmd_len);
376 ilo_cp_write(cp, cmd | (cmd_len - 2));
377 ilo_cp_write_multi(cp, dw, 6);
378 ilo_cp_end(cp);
379 }
380
381 static inline void
382 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
383 const uint32_t *bufs, const int *sizes,
384 int num_bufs,
385 struct ilo_cp *cp)
386 {
387 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
388 }
389
390 static inline void
391 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
392 const uint32_t *bufs, const int *sizes,
393 int num_bufs,
394 struct ilo_cp *cp)
395 {
396 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
397 }
398
399 static inline void
400 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
401 const uint32_t *bufs, const int *sizes,
402 int num_bufs,
403 struct ilo_cp *cp)
404 {
405 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
406 }
407
408 static inline void
409 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
410 unsigned sample_mask,
411 int num_samples,
412 struct ilo_cp *cp)
413 {
414 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
415 const uint8_t cmd_len = 2;
416 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
417
418 ILO_GPE_VALID_GEN(dev, 7, 7);
419
420 /*
421 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
422 *
423 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
424 * (Sample Mask) must be zero.
425 *
426 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
427 * must be zero."
428 */
429 sample_mask &= valid_mask;
430
431 ilo_cp_begin(cp, cmd_len);
432 ilo_cp_write(cp, cmd | (cmd_len - 2));
433 ilo_cp_write(cp, sample_mask);
434 ilo_cp_end(cp);
435 }
436
437 static inline void
438 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
439 const uint32_t *bufs, const int *sizes,
440 int num_bufs,
441 struct ilo_cp *cp)
442 {
443 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
444 }
445
446 static inline void
447 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
448 const uint32_t *bufs, const int *sizes,
449 int num_bufs,
450 struct ilo_cp *cp)
451 {
452 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
453 }
454
455 static inline void
456 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
457 const struct ilo_shader_state *hs,
458 int num_samplers,
459 struct ilo_cp *cp)
460 {
461 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
462 const uint8_t cmd_len = 7;
463
464 ILO_GPE_VALID_GEN(dev, 7, 7);
465
466 assert(!hs);
467
468 ilo_cp_begin(cp, cmd_len);
469 ilo_cp_write(cp, cmd | (cmd_len - 2));
470 ilo_cp_write(cp, 0);
471 ilo_cp_write(cp, 0);
472 ilo_cp_write(cp, 0);
473 ilo_cp_write(cp, 0);
474 ilo_cp_write(cp, 0);
475 ilo_cp_write(cp, 0);
476 ilo_cp_end(cp);
477 }
478
479 static inline void
480 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
481 struct ilo_cp *cp)
482 {
483 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
484 const uint8_t cmd_len = 4;
485
486 ILO_GPE_VALID_GEN(dev, 7, 7);
487
488 ilo_cp_begin(cp, cmd_len);
489 ilo_cp_write(cp, cmd | (cmd_len - 2));
490 ilo_cp_write(cp, 0);
491 ilo_cp_write(cp, 0);
492 ilo_cp_write(cp, 0);
493 ilo_cp_end(cp);
494 }
495
496 static inline void
497 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
498 const struct ilo_shader_state *ds,
499 int num_samplers,
500 struct ilo_cp *cp)
501 {
502 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
503 const uint8_t cmd_len = 6;
504
505 ILO_GPE_VALID_GEN(dev, 7, 7);
506
507 assert(!ds);
508
509 ilo_cp_begin(cp, cmd_len);
510 ilo_cp_write(cp, cmd | (cmd_len - 2));
511 ilo_cp_write(cp, 0);
512 ilo_cp_write(cp, 0);
513 ilo_cp_write(cp, 0);
514 ilo_cp_write(cp, 0);
515 ilo_cp_write(cp, 0);
516 ilo_cp_end(cp);
517
518 }
519
520 static inline void
521 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
522 unsigned buffer_mask,
523 int vertex_attrib_count,
524 bool rasterizer_discard,
525 struct ilo_cp *cp)
526 {
527 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
528 const uint8_t cmd_len = 3;
529 const bool enable = (buffer_mask != 0);
530 uint32_t dw1, dw2;
531 int read_len;
532
533 ILO_GPE_VALID_GEN(dev, 7, 7);
534
535 if (!enable) {
536 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
537 if (rasterizer_discard)
538 dw1 |= SO_RENDERING_DISABLE;
539
540 dw2 = 0;
541
542 ilo_cp_begin(cp, cmd_len);
543 ilo_cp_write(cp, cmd | (cmd_len - 2));
544 ilo_cp_write(cp, dw1);
545 ilo_cp_write(cp, dw2);
546 ilo_cp_end(cp);
547 return;
548 }
549
550 read_len = (vertex_attrib_count + 1) / 2;
551 if (!read_len)
552 read_len = 1;
553
554 dw1 = SO_FUNCTION_ENABLE |
555 0 << SO_RENDER_STREAM_SELECT_SHIFT |
556 SO_STATISTICS_ENABLE |
557 buffer_mask << 8;
558
559 if (rasterizer_discard)
560 dw1 |= SO_RENDERING_DISABLE;
561
562 /* API_OPENGL */
563 if (true)
564 dw1 |= SO_REORDER_TRAILING;
565
566 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
567 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
568 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
569 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
570 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
571 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
572 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
573 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
574
575 ilo_cp_begin(cp, cmd_len);
576 ilo_cp_write(cp, cmd | (cmd_len - 2));
577 ilo_cp_write(cp, dw1);
578 ilo_cp_write(cp, dw2);
579 ilo_cp_end(cp);
580 }
581
582 static inline void
583 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
584 const struct ilo_rasterizer_state *rasterizer,
585 const struct ilo_shader_state *fs,
586 const struct ilo_shader_state *last_sh,
587 struct ilo_cp *cp)
588 {
589 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
590 const uint8_t cmd_len = 14;
591 uint32_t dw[13];
592
593 ILO_GPE_VALID_GEN(dev, 7, 7);
594
595 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer,
596 fs, last_sh, dw, Elements(dw));
597
598 ilo_cp_begin(cp, cmd_len);
599 ilo_cp_write(cp, cmd | (cmd_len - 2));
600 ilo_cp_write_multi(cp, dw, 13);
601 ilo_cp_end(cp);
602 }
603
604 static inline void
605 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
606 const struct ilo_shader_state *fs,
607 int num_samplers, bool dual_blend,
608 struct ilo_cp *cp)
609 {
610 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
611 const uint8_t cmd_len = 8;
612 const struct ilo_shader_cso *cso;
613 uint32_t dw2, dw4, dw5;
614
615 ILO_GPE_VALID_GEN(dev, 7, 7);
616
617 if (!fs) {
618 /* see brwCreateContext() */
619 const int max_threads = (dev->gt == 2) ? 172 : 48;
620
621 ilo_cp_begin(cp, cmd_len);
622 ilo_cp_write(cp, cmd | (cmd_len - 2));
623 ilo_cp_write(cp, 0);
624 ilo_cp_write(cp, 0);
625 ilo_cp_write(cp, 0);
626 /* GPU hangs if none of the dispatch enable bits is set */
627 ilo_cp_write(cp, (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT |
628 GEN7_PS_8_DISPATCH_ENABLE);
629 ilo_cp_write(cp, 0);
630 ilo_cp_write(cp, 0);
631 ilo_cp_write(cp, 0);
632 ilo_cp_end(cp);
633
634 return;
635 }
636
637 cso = ilo_shader_get_kernel_cso(fs);
638 dw2 = cso->payload[0];
639 dw4 = cso->payload[1];
640 dw5 = cso->payload[2];
641
642 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
643
644 if (dual_blend)
645 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
646
647 ilo_cp_begin(cp, cmd_len);
648 ilo_cp_write(cp, cmd | (cmd_len - 2));
649 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
650 ilo_cp_write(cp, dw2);
651 ilo_cp_write(cp, 0); /* scratch */
652 ilo_cp_write(cp, dw4);
653 ilo_cp_write(cp, dw5);
654 ilo_cp_write(cp, 0); /* kernel 1 */
655 ilo_cp_write(cp, 0); /* kernel 2 */
656 ilo_cp_end(cp);
657 }
658
659 static inline void
660 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
661 uint32_t sf_clip_viewport,
662 struct ilo_cp *cp)
663 {
664 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
665 }
666
667 static inline void
668 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
669 uint32_t cc_viewport,
670 struct ilo_cp *cp)
671 {
672 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
673 }
674
675 static inline void
676 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
677 uint32_t blend_state,
678 struct ilo_cp *cp)
679 {
680 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
681 }
682
683 static inline void
684 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
685 uint32_t depth_stencil_state,
686 struct ilo_cp *cp)
687 {
688 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
689 }
690
691 static inline void
692 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
693 uint32_t binding_table,
694 struct ilo_cp *cp)
695 {
696 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
697 }
698
699 static inline void
700 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
701 uint32_t binding_table,
702 struct ilo_cp *cp)
703 {
704 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
705 }
706
707 static inline void
708 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
709 uint32_t binding_table,
710 struct ilo_cp *cp)
711 {
712 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
713 }
714
715 static inline void
716 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
717 uint32_t binding_table,
718 struct ilo_cp *cp)
719 {
720 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
721 }
722
723 static inline void
724 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
725 uint32_t binding_table,
726 struct ilo_cp *cp)
727 {
728 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
729 }
730
731 static inline void
732 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
733 uint32_t sampler_state,
734 struct ilo_cp *cp)
735 {
736 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
737 }
738
739 static inline void
740 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
741 uint32_t sampler_state,
742 struct ilo_cp *cp)
743 {
744 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
745 }
746
747 static inline void
748 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
749 uint32_t sampler_state,
750 struct ilo_cp *cp)
751 {
752 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
753 }
754
755 static inline void
756 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
757 uint32_t sampler_state,
758 struct ilo_cp *cp)
759 {
760 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
761 }
762
763 static inline void
764 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
765 uint32_t sampler_state,
766 struct ilo_cp *cp)
767 {
768 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
769 }
770
771 static inline void
772 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
773 int subop, int offset, int size,
774 int entry_size,
775 struct ilo_cp *cp)
776 {
777 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
778 const uint8_t cmd_len = 2;
779 const int row_size = 64; /* 512 bits */
780 int alloc_size, num_entries, min_entries, max_entries;
781
782 ILO_GPE_VALID_GEN(dev, 7, 7);
783
784 /* VS, HS, DS, and GS variants */
785 assert(subop >= 0x30 && subop <= 0x33);
786
787 /* in multiples of 8KB */
788 assert(offset % 8192 == 0);
789 offset /= 8192;
790
791 /* in multiple of 512-bit rows */
792 alloc_size = (entry_size + row_size - 1) / row_size;
793 if (!alloc_size)
794 alloc_size = 1;
795
796 /*
797 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
798 *
799 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
800 * cause performance to decrease due to banking in the URB. Element
801 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
802 */
803 if (subop == 0x30 && alloc_size == 5)
804 alloc_size = 6;
805
806 /* in multiples of 8 */
807 num_entries = (size / row_size / alloc_size) & ~7;
808
809 switch (subop) {
810 case 0x30: /* 3DSTATE_URB_VS */
811 min_entries = 32;
812 max_entries = (dev->gt == 2) ? 704 : 512;
813
814 assert(num_entries >= min_entries);
815 if (num_entries > max_entries)
816 num_entries = max_entries;
817 break;
818 case 0x31: /* 3DSTATE_URB_HS */
819 max_entries = (dev->gt == 2) ? 64 : 32;
820 if (num_entries > max_entries)
821 num_entries = max_entries;
822 break;
823 case 0x32: /* 3DSTATE_URB_DS */
824 if (num_entries)
825 assert(num_entries >= 138);
826 break;
827 case 0x33: /* 3DSTATE_URB_GS */
828 max_entries = (dev->gt == 2) ? 320 : 192;
829 if (num_entries > max_entries)
830 num_entries = max_entries;
831 break;
832 default:
833 break;
834 }
835
836 ilo_cp_begin(cp, cmd_len);
837 ilo_cp_write(cp, cmd | (cmd_len - 2));
838 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
839 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
840 num_entries);
841 ilo_cp_end(cp);
842 }
843
844 static inline void
845 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
846 int offset, int size, int entry_size,
847 struct ilo_cp *cp)
848 {
849 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
850 }
851
852 static inline void
853 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
854 int offset, int size, int entry_size,
855 struct ilo_cp *cp)
856 {
857 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
858 }
859
860 static inline void
861 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
862 int offset, int size, int entry_size,
863 struct ilo_cp *cp)
864 {
865 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
866 }
867
868 static inline void
869 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
870 int offset, int size, int entry_size,
871 struct ilo_cp *cp)
872 {
873 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
874 }
875
876 static inline void
877 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
878 int subop, int offset, int size,
879 struct ilo_cp *cp)
880 {
881 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
882 const uint8_t cmd_len = 2;
883 int end;
884
885 ILO_GPE_VALID_GEN(dev, 7, 7);
886
887 /* VS, HS, DS, GS, and PS variants */
888 assert(subop >= 0x12 && subop <= 0x16);
889
890 /*
891 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
892 *
893 * "(A table that says the maximum size of each constant buffer is
894 * 16KB")
895 *
896 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
897 *
898 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
899 * may not exceed the maximum value of the Constant Buffer Size."
900 *
901 * Thus, the valid range of buffer end is [0KB, 16KB].
902 */
903 end = (offset + size) / 1024;
904 if (end > 16) {
905 assert(!"invalid constant buffer end");
906 end = 16;
907 }
908
909 /* the valid range of buffer offset is [0KB, 15KB] */
910 offset = (offset + 1023) / 1024;
911 if (offset > 15) {
912 assert(!"invalid constant buffer offset");
913 offset = 15;
914 }
915
916 if (offset > end) {
917 assert(!size);
918 offset = end;
919 }
920
921 /* the valid range of buffer size is [0KB, 15KB] */
922 size = end - offset;
923 if (size > 15) {
924 assert(!"invalid constant buffer size");
925 size = 15;
926 }
927
928 ilo_cp_begin(cp, cmd_len);
929 ilo_cp_write(cp, cmd | (cmd_len - 2));
930 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
931 size);
932 ilo_cp_end(cp);
933 }
934
935 static inline void
936 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
937 int offset, int size,
938 struct ilo_cp *cp)
939 {
940 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
941 }
942
943 static inline void
944 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
945 int offset, int size,
946 struct ilo_cp *cp)
947 {
948 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
949 }
950
951 static inline void
952 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
953 int offset, int size,
954 struct ilo_cp *cp)
955 {
956 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
957 }
958
959 static inline void
960 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
961 int offset, int size,
962 struct ilo_cp *cp)
963 {
964 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
965 }
966
967 static inline void
968 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
969 int offset, int size,
970 struct ilo_cp *cp)
971 {
972 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
973 }
974
975 static inline void
976 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
977 const struct pipe_stream_output_info *so_info,
978 struct ilo_cp *cp)
979 {
980 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
981 uint16_t cmd_len;
982 int buffer_selects, num_entries, i;
983 uint16_t so_decls[128];
984
985 ILO_GPE_VALID_GEN(dev, 7, 7);
986
987 buffer_selects = 0;
988 num_entries = 0;
989
990 if (so_info) {
991 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
992
993 memset(buffer_offsets, 0, sizeof(buffer_offsets));
994
995 for (i = 0; i < so_info->num_outputs; i++) {
996 unsigned decl, buf, reg, mask;
997
998 buf = so_info->output[i].output_buffer;
999
1000 /* pad with holes */
1001 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
1002 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1003 int num_dwords;
1004
1005 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1006 if (num_dwords > 4)
1007 num_dwords = 4;
1008
1009 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1010 SO_DECL_HOLE_FLAG |
1011 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1012
1013 so_decls[num_entries++] = decl;
1014 buffer_offsets[buf] += num_dwords;
1015 }
1016
1017 reg = so_info->output[i].register_index;
1018 mask = ((1 << so_info->output[i].num_components) - 1) <<
1019 so_info->output[i].start_component;
1020
1021 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1022 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1023 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1024
1025 so_decls[num_entries++] = decl;
1026 buffer_selects |= 1 << buf;
1027 buffer_offsets[buf] += so_info->output[i].num_components;
1028 }
1029 }
1030
1031 /*
1032 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1033 *
1034 * "Errata: All 128 decls for all four streams must be included
1035 * whenever this command is issued. The "Num Entries [n]" fields still
1036 * contain the actual numbers of valid decls."
1037 *
1038 * Also note that "DWord Length" has 9 bits for this command, and the type
1039 * of cmd_len is thus uint16_t.
1040 */
1041 cmd_len = 2 * 128 + 3;
1042
1043 ilo_cp_begin(cp, cmd_len);
1044 ilo_cp_write(cp, cmd | (cmd_len - 2));
1045 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1046 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1047 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1048 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1049 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1050 0 << SO_NUM_ENTRIES_2_SHIFT |
1051 0 << SO_NUM_ENTRIES_1_SHIFT |
1052 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1053
1054 for (i = 0; i < num_entries; i++) {
1055 ilo_cp_write(cp, so_decls[i]);
1056 ilo_cp_write(cp, 0);
1057 }
1058 for (; i < 128; i++) {
1059 ilo_cp_write(cp, 0);
1060 ilo_cp_write(cp, 0);
1061 }
1062
1063 ilo_cp_end(cp);
1064 }
1065
1066 static inline void
1067 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1068 int index, int base, int stride,
1069 const struct pipe_stream_output_target *so_target,
1070 struct ilo_cp *cp)
1071 {
1072 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1073 const uint8_t cmd_len = 4;
1074 struct ilo_buffer *buf;
1075 int end;
1076
1077 ILO_GPE_VALID_GEN(dev, 7, 7);
1078
1079 if (!so_target || !so_target->buffer) {
1080 ilo_cp_begin(cp, cmd_len);
1081 ilo_cp_write(cp, cmd | (cmd_len - 2));
1082 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1083 ilo_cp_write(cp, 0);
1084 ilo_cp_write(cp, 0);
1085 ilo_cp_end(cp);
1086 return;
1087 }
1088
1089 buf = ilo_buffer(so_target->buffer);
1090
1091 /* DWord-aligned */
1092 assert(stride % 4 == 0 && base % 4 == 0);
1093 assert(so_target->buffer_offset % 4 == 0);
1094
1095 stride &= ~3;
1096 base = (base + so_target->buffer_offset) & ~3;
1097 end = (base + so_target->buffer_size) & ~3;
1098
1099 ilo_cp_begin(cp, cmd_len);
1100 ilo_cp_write(cp, cmd | (cmd_len - 2));
1101 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1102 stride);
1103 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1104 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1105 ilo_cp_end(cp);
1106 }
1107
1108 static inline void
1109 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1110 const struct pipe_draw_info *info,
1111 const struct ilo_ib_state *ib,
1112 bool rectlist,
1113 struct ilo_cp *cp)
1114 {
1115 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1116 const uint8_t cmd_len = 7;
1117 const int prim = (rectlist) ?
1118 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1119 const int vb_access = (info->indexed) ?
1120 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1121 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1122 const uint32_t vb_start = info->start +
1123 ((info->indexed) ? ib->draw_start_offset : 0);
1124
1125 ILO_GPE_VALID_GEN(dev, 7, 7);
1126
1127 ilo_cp_begin(cp, cmd_len);
1128 ilo_cp_write(cp, cmd | (cmd_len - 2));
1129 ilo_cp_write(cp, vb_access | prim);
1130 ilo_cp_write(cp, info->count);
1131 ilo_cp_write(cp, vb_start);
1132 ilo_cp_write(cp, info->instance_count);
1133 ilo_cp_write(cp, info->start_instance);
1134 ilo_cp_write(cp, info->index_bias);
1135 ilo_cp_end(cp);
1136 }
1137
1138 static inline uint32_t
1139 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1140 const struct ilo_viewport_cso *viewports,
1141 unsigned num_viewports,
1142 struct ilo_cp *cp)
1143 {
1144 const int state_align = 64 / 4;
1145 const int state_len = 16 * num_viewports;
1146 uint32_t state_offset, *dw;
1147 unsigned i;
1148
1149 ILO_GPE_VALID_GEN(dev, 7, 7);
1150
1151 /*
1152 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1153 *
1154 * "The viewport-specific state used by both the SF and CL units
1155 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1156 * of which contains the DWords described below. The start of each
1157 * element is spaced 16 DWords apart. The location of first element of
1158 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1159 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1160 */
1161 assert(num_viewports && num_viewports <= 16);
1162
1163 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1164 state_len, state_align, &state_offset);
1165
1166 for (i = 0; i < num_viewports; i++) {
1167 const struct ilo_viewport_cso *vp = &viewports[i];
1168
1169 dw[0] = fui(vp->m00);
1170 dw[1] = fui(vp->m11);
1171 dw[2] = fui(vp->m22);
1172 dw[3] = fui(vp->m30);
1173 dw[4] = fui(vp->m31);
1174 dw[5] = fui(vp->m32);
1175 dw[6] = 0;
1176 dw[7] = 0;
1177 dw[8] = fui(vp->min_gbx);
1178 dw[9] = fui(vp->max_gbx);
1179 dw[10] = fui(vp->min_gby);
1180 dw[11] = fui(vp->max_gby);
1181 dw[12] = 0;
1182 dw[13] = 0;
1183 dw[14] = 0;
1184 dw[15] = 0;
1185
1186 dw += 16;
1187 }
1188
1189 return state_offset;
1190 }
1191
1192 #endif /* ILO_GPE_GEN7_H */