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ilo: add some MI commands to GPE
[mesa.git] / src / gallium / drivers / ilo / ilo_gpe_gen7.h
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #ifndef ILO_GPE_GEN7_H
29 #define ILO_GPE_GEN7_H
30
31 #include "intel_winsys.h"
32
33 #include "ilo_common.h"
34 #include "ilo_cp.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_gpe_gen6.h"
38
39 /**
40 * Commands that GEN7 GPE could emit.
41 */
42 enum ilo_gpe_gen7_command {
43 ILO_GPE_GEN7_MI_STORE_DATA_IMM, /* ILO_GPE_MI(0x20) */
44 ILO_GPE_GEN7_MI_LOAD_REGISTER_IMM, /* ILO_GPE_MI(0x22) */
45 ILO_GPE_GEN7_MI_STORE_REGISTER_MEM, /* ILO_GPE_MI(0x24) */
46 ILO_GPE_GEN7_MI_REPORT_PERF_COUNT, /* ILO_GPE_MI(0x28) */
47 ILO_GPE_GEN7_STATE_BASE_ADDRESS, /* (0x0, 0x1, 0x01) */
48 ILO_GPE_GEN7_STATE_SIP, /* (0x0, 0x1, 0x02) */
49 ILO_GPE_GEN7_3DSTATE_VF_STATISTICS, /* (0x1, 0x0, 0x0b) */
50 ILO_GPE_GEN7_PIPELINE_SELECT, /* (0x1, 0x1, 0x04) */
51 ILO_GPE_GEN7_MEDIA_VFE_STATE, /* (0x2, 0x0, 0x00) */
52 ILO_GPE_GEN7_MEDIA_CURBE_LOAD, /* (0x2, 0x0, 0x01) */
53 ILO_GPE_GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD, /* (0x2, 0x0, 0x02) */
54 ILO_GPE_GEN7_MEDIA_STATE_FLUSH, /* (0x2, 0x0, 0x04) */
55 ILO_GPE_GEN7_GPGPU_WALKER, /* (0x2, 0x1, 0x05) */
56 ILO_GPE_GEN7_3DSTATE_CLEAR_PARAMS, /* (0x3, 0x0, 0x04) */
57 ILO_GPE_GEN7_3DSTATE_DEPTH_BUFFER, /* (0x3, 0x0, 0x05) */
58 ILO_GPE_GEN7_3DSTATE_STENCIL_BUFFER, /* (0x3, 0x0, 0x06) */
59 ILO_GPE_GEN7_3DSTATE_HIER_DEPTH_BUFFER, /* (0x3, 0x0, 0x07) */
60 ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS, /* (0x3, 0x0, 0x08) */
61 ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS, /* (0x3, 0x0, 0x09) */
62 ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER, /* (0x3, 0x0, 0x0a) */
63 ILO_GPE_GEN7_3DSTATE_VF, /* (0x3, 0x0, 0x0c) */
64 ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS, /* (0x3, 0x0, 0x0e) */
65 ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS, /* (0x3, 0x0, 0x0f) */
66 ILO_GPE_GEN7_3DSTATE_VS, /* (0x3, 0x0, 0x10) */
67 ILO_GPE_GEN7_3DSTATE_GS, /* (0x3, 0x0, 0x11) */
68 ILO_GPE_GEN7_3DSTATE_CLIP, /* (0x3, 0x0, 0x12) */
69 ILO_GPE_GEN7_3DSTATE_SF, /* (0x3, 0x0, 0x13) */
70 ILO_GPE_GEN7_3DSTATE_WM, /* (0x3, 0x0, 0x14) */
71 ILO_GPE_GEN7_3DSTATE_CONSTANT_VS, /* (0x3, 0x0, 0x15) */
72 ILO_GPE_GEN7_3DSTATE_CONSTANT_GS, /* (0x3, 0x0, 0x16) */
73 ILO_GPE_GEN7_3DSTATE_CONSTANT_PS, /* (0x3, 0x0, 0x17) */
74 ILO_GPE_GEN7_3DSTATE_SAMPLE_MASK, /* (0x3, 0x0, 0x18) */
75 ILO_GPE_GEN7_3DSTATE_CONSTANT_HS, /* (0x3, 0x0, 0x19) */
76 ILO_GPE_GEN7_3DSTATE_CONSTANT_DS, /* (0x3, 0x0, 0x1a) */
77 ILO_GPE_GEN7_3DSTATE_HS, /* (0x3, 0x0, 0x1b) */
78 ILO_GPE_GEN7_3DSTATE_TE, /* (0x3, 0x0, 0x1c) */
79 ILO_GPE_GEN7_3DSTATE_DS, /* (0x3, 0x0, 0x1d) */
80 ILO_GPE_GEN7_3DSTATE_STREAMOUT, /* (0x3, 0x0, 0x1e) */
81 ILO_GPE_GEN7_3DSTATE_SBE, /* (0x3, 0x0, 0x1f) */
82 ILO_GPE_GEN7_3DSTATE_PS, /* (0x3, 0x0, 0x20) */
83 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, /* (0x3, 0x0, 0x21) */
84 ILO_GPE_GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC, /* (0x3, 0x0, 0x23) */
85 ILO_GPE_GEN7_3DSTATE_BLEND_STATE_POINTERS, /* (0x3, 0x0, 0x24) */
86 ILO_GPE_GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, /* (0x3, 0x0, 0x25) */
87 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, /* (0x3, 0x0, 0x26) */
88 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, /* (0x3, 0x0, 0x27) */
89 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, /* (0x3, 0x0, 0x28) */
90 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, /* (0x3, 0x0, 0x29) */
91 ILO_GPE_GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, /* (0x3, 0x0, 0x2a) */
92 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, /* (0x3, 0x0, 0x2b) */
93 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, /* (0x3, 0x0, 0x2c) */
94 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, /* (0x3, 0x0, 0x2d) */
95 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, /* (0x3, 0x0, 0x2e) */
96 ILO_GPE_GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, /* (0x3, 0x0, 0x2f) */
97 ILO_GPE_GEN7_3DSTATE_URB_VS, /* (0x3, 0x0, 0x30) */
98 ILO_GPE_GEN7_3DSTATE_URB_HS, /* (0x3, 0x0, 0x31) */
99 ILO_GPE_GEN7_3DSTATE_URB_DS, /* (0x3, 0x0, 0x32) */
100 ILO_GPE_GEN7_3DSTATE_URB_GS, /* (0x3, 0x0, 0x33) */
101 ILO_GPE_GEN7_3DSTATE_DRAWING_RECTANGLE, /* (0x3, 0x1, 0x00) */
102 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_OFFSET, /* (0x3, 0x1, 0x06) */
103 ILO_GPE_GEN7_3DSTATE_POLY_STIPPLE_PATTERN, /* (0x3, 0x1, 0x07) */
104 ILO_GPE_GEN7_3DSTATE_LINE_STIPPLE, /* (0x3, 0x1, 0x08) */
105 ILO_GPE_GEN7_3DSTATE_AA_LINE_PARAMETERS, /* (0x3, 0x1, 0x0a) */
106 ILO_GPE_GEN7_3DSTATE_MULTISAMPLE, /* (0x3, 0x1, 0x0d) */
107 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, /* (0x3, 0x1, 0x12) */
108 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, /* (0x3, 0x1, 0x13) */
109 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, /* (0x3, 0x1, 0x14) */
110 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, /* (0x3, 0x1, 0x15) */
111 ILO_GPE_GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, /* (0x3, 0x1, 0x16) */
112 ILO_GPE_GEN7_3DSTATE_SO_DECL_LIST, /* (0x3, 0x1, 0x17) */
113 ILO_GPE_GEN7_3DSTATE_SO_BUFFER, /* (0x3, 0x1, 0x18) */
114 ILO_GPE_GEN7_PIPE_CONTROL, /* (0x3, 0x2, 0x00) */
115 ILO_GPE_GEN7_3DPRIMITIVE, /* (0x3, 0x3, 0x00) */
116
117 ILO_GPE_GEN7_COMMAND_COUNT,
118 };
119
120 /**
121 * Indirect states that GEN7 GPE could emit.
122 */
123 enum ilo_gpe_gen7_state {
124 ILO_GPE_GEN7_INTERFACE_DESCRIPTOR_DATA,
125 ILO_GPE_GEN7_SF_CLIP_VIEWPORT,
126 ILO_GPE_GEN7_CC_VIEWPORT,
127 ILO_GPE_GEN7_COLOR_CALC_STATE,
128 ILO_GPE_GEN7_BLEND_STATE,
129 ILO_GPE_GEN7_DEPTH_STENCIL_STATE,
130 ILO_GPE_GEN7_SCISSOR_RECT,
131 ILO_GPE_GEN7_BINDING_TABLE_STATE,
132 ILO_GPE_GEN7_SURFACE_STATE,
133 ILO_GPE_GEN7_SAMPLER_STATE,
134 ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE,
135 ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER,
136
137 ILO_GPE_GEN7_STATE_COUNT,
138 };
139
140 int
141 ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
142 enum ilo_gpe_gen7_command cmd,
143 int arg);
144
145 int
146 ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
147 enum ilo_gpe_gen7_state state,
148 int arg);
149
150 static inline void
151 gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,
152 struct ilo_cp *cp)
153 {
154 assert(!"GPGPU_WALKER unsupported");
155 }
156
157 static inline void
158 gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
159 uint32_t clear_val,
160 struct ilo_cp *cp)
161 {
162 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
163 const uint8_t cmd_len = 3;
164
165 ILO_GPE_VALID_GEN(dev, 7, 7.5);
166
167 ilo_cp_begin(cp, cmd_len);
168 ilo_cp_write(cp, cmd | (cmd_len - 2));
169 ilo_cp_write(cp, clear_val);
170 ilo_cp_write(cp, 1);
171 ilo_cp_end(cp);
172 }
173
174 static inline void
175 gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev,
176 bool enable_cut_index,
177 uint32_t cut_index,
178 struct ilo_cp *cp)
179 {
180 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0c);
181 const uint8_t cmd_len = 2;
182
183 ILO_GPE_VALID_GEN(dev, 7.5, 7.5);
184
185 ilo_cp_begin(cp, cmd_len);
186 ilo_cp_write(cp, cmd | (cmd_len - 2) |
187 ((enable_cut_index) ? HSW_CUT_INDEX_ENABLE : 0));
188 ilo_cp_write(cp, cut_index);
189 ilo_cp_end(cp);
190 }
191
192 static inline void
193 gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
194 int subop, uint32_t pointer,
195 struct ilo_cp *cp)
196 {
197 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
198 const uint8_t cmd_len = 2;
199
200 ILO_GPE_VALID_GEN(dev, 7, 7.5);
201
202 ilo_cp_begin(cp, cmd_len);
203 ilo_cp_write(cp, cmd | (cmd_len - 2));
204 ilo_cp_write(cp, pointer);
205 ilo_cp_end(cp);
206 }
207
208 static inline void
209 gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
210 uint32_t color_calc_state,
211 struct ilo_cp *cp)
212 {
213 gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
214 }
215
216 static inline void
217 gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
218 const struct ilo_shader_state *gs,
219 int num_samplers,
220 struct ilo_cp *cp)
221 {
222 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
223 const uint8_t cmd_len = 7;
224 const struct ilo_shader_cso *cso;
225 uint32_t dw2, dw4, dw5;
226
227 ILO_GPE_VALID_GEN(dev, 7, 7.5);
228
229 if (!gs) {
230 ilo_cp_begin(cp, cmd_len);
231 ilo_cp_write(cp, cmd | (cmd_len - 2));
232 ilo_cp_write(cp, 0);
233 ilo_cp_write(cp, 0);
234 ilo_cp_write(cp, 0);
235 ilo_cp_write(cp, 0);
236 ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE);
237 ilo_cp_write(cp, 0);
238 ilo_cp_end(cp);
239 return;
240 }
241
242 cso = ilo_shader_get_kernel_cso(gs);
243 dw2 = cso->payload[0];
244 dw4 = cso->payload[1];
245 dw5 = cso->payload[2];
246
247 dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT;
248
249 ilo_cp_begin(cp, cmd_len);
250 ilo_cp_write(cp, cmd | (cmd_len - 2));
251 ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
252 ilo_cp_write(cp, dw2);
253 ilo_cp_write(cp, 0); /* scratch */
254 ilo_cp_write(cp, dw4);
255 ilo_cp_write(cp, dw5);
256 ilo_cp_write(cp, 0);
257 ilo_cp_end(cp);
258 }
259
260 static inline void
261 gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
262 const struct ilo_rasterizer_state *rasterizer,
263 enum pipe_format zs_format,
264 struct ilo_cp *cp)
265 {
266 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
267 const uint8_t cmd_len = 7;
268 const int num_samples = 1;
269 uint32_t payload[6];
270
271 ILO_GPE_VALID_GEN(dev, 7, 7.5);
272
273 ilo_gpe_gen6_fill_3dstate_sf_raster(dev,
274 rasterizer, num_samples, zs_format,
275 payload, Elements(payload));
276
277 ilo_cp_begin(cp, cmd_len);
278 ilo_cp_write(cp, cmd | (cmd_len - 2));
279 ilo_cp_write_multi(cp, payload, 6);
280 ilo_cp_end(cp);
281 }
282
283 static inline void
284 gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
285 const struct ilo_shader_state *fs,
286 const struct ilo_rasterizer_state *rasterizer,
287 bool cc_may_kill, uint32_t hiz_op,
288 struct ilo_cp *cp)
289 {
290 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
291 const uint8_t cmd_len = 3;
292 const int num_samples = 1;
293 uint32_t dw1, dw2;
294
295 ILO_GPE_VALID_GEN(dev, 7, 7.5);
296
297 /* see ilo_gpe_init_rasterizer_wm() */
298 if (rasterizer) {
299 dw1 = rasterizer->wm.payload[0];
300 dw2 = rasterizer->wm.payload[1];
301
302 assert(!hiz_op);
303 dw1 |= GEN7_WM_STATISTICS_ENABLE;
304 }
305 else {
306 dw1 = hiz_op;
307 dw2 = 0;
308 }
309
310 if (fs) {
311 const struct ilo_shader_cso *fs_cso = ilo_shader_get_kernel_cso(fs);
312
313 dw1 |= fs_cso->payload[3];
314 }
315
316 if (cc_may_kill) {
317 dw1 |= GEN7_WM_DISPATCH_ENABLE |
318 GEN7_WM_KILL_ENABLE;
319 }
320
321 if (num_samples > 1) {
322 dw1 |= rasterizer->wm.dw_msaa_rast;
323 dw2 |= rasterizer->wm.dw_msaa_disp;
324 }
325
326 ilo_cp_begin(cp, cmd_len);
327 ilo_cp_write(cp, cmd | (cmd_len - 2));
328 ilo_cp_write(cp, dw1);
329 ilo_cp_write(cp, dw2);
330 ilo_cp_end(cp);
331 }
332
333 static inline void
334 gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
335 int subop,
336 const uint32_t *bufs, const int *sizes,
337 int num_bufs,
338 struct ilo_cp *cp)
339 {
340 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
341 const uint8_t cmd_len = 7;
342 uint32_t dw[6];
343 int total_read_length, i;
344
345 ILO_GPE_VALID_GEN(dev, 7, 7.5);
346
347 /* VS, HS, DS, GS, and PS variants */
348 assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
349
350 assert(num_bufs <= 4);
351
352 dw[0] = 0;
353 dw[1] = 0;
354
355 total_read_length = 0;
356 for (i = 0; i < 4; i++) {
357 int read_len;
358
359 /*
360 * From the Ivy Bridge PRM, volume 2 part 1, page 112:
361 *
362 * "Constant buffers must be enabled in order from Constant Buffer 0
363 * to Constant Buffer 3 within this command. For example, it is
364 * not allowed to enable Constant Buffer 1 by programming a
365 * non-zero value in the VS Constant Buffer 1 Read Length without a
366 * non-zero value in VS Constant Buffer 0 Read Length."
367 */
368 if (i >= num_bufs || !sizes[i]) {
369 for (; i < 4; i++) {
370 assert(i >= num_bufs || !sizes[i]);
371 dw[2 + i] = 0;
372 }
373 break;
374 }
375
376 /* read lengths are in 256-bit units */
377 read_len = (sizes[i] + 31) / 32;
378 /* the lower 5 bits are used for memory object control state */
379 assert(bufs[i] % 32 == 0);
380
381 dw[i / 2] |= read_len << ((i % 2) ? 16 : 0);
382 dw[2 + i] = bufs[i];
383
384 total_read_length += read_len;
385 }
386
387 /*
388 * From the Ivy Bridge PRM, volume 2 part 1, page 113:
389 *
390 * "The sum of all four read length fields must be less than or equal
391 * to the size of 64"
392 */
393 assert(total_read_length <= 64);
394
395 ilo_cp_begin(cp, cmd_len);
396 ilo_cp_write(cp, cmd | (cmd_len - 2));
397 ilo_cp_write_multi(cp, dw, 6);
398 ilo_cp_end(cp);
399 }
400
401 static inline void
402 gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
403 const uint32_t *bufs, const int *sizes,
404 int num_bufs,
405 struct ilo_cp *cp)
406 {
407 gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
408 }
409
410 static inline void
411 gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
412 const uint32_t *bufs, const int *sizes,
413 int num_bufs,
414 struct ilo_cp *cp)
415 {
416 gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
417 }
418
419 static inline void
420 gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
421 const uint32_t *bufs, const int *sizes,
422 int num_bufs,
423 struct ilo_cp *cp)
424 {
425 gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
426 }
427
428 static inline void
429 gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
430 unsigned sample_mask,
431 int num_samples,
432 struct ilo_cp *cp)
433 {
434 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
435 const uint8_t cmd_len = 2;
436 const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
437
438 ILO_GPE_VALID_GEN(dev, 7, 7.5);
439
440 /*
441 * From the Ivy Bridge PRM, volume 2 part 1, page 294:
442 *
443 * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
444 * (Sample Mask) must be zero.
445 *
446 * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
447 * must be zero."
448 */
449 sample_mask &= valid_mask;
450
451 ilo_cp_begin(cp, cmd_len);
452 ilo_cp_write(cp, cmd | (cmd_len - 2));
453 ilo_cp_write(cp, sample_mask);
454 ilo_cp_end(cp);
455 }
456
457 static inline void
458 gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
459 const uint32_t *bufs, const int *sizes,
460 int num_bufs,
461 struct ilo_cp *cp)
462 {
463 gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
464 }
465
466 static inline void
467 gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
468 const uint32_t *bufs, const int *sizes,
469 int num_bufs,
470 struct ilo_cp *cp)
471 {
472 gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
473 }
474
475 static inline void
476 gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
477 const struct ilo_shader_state *hs,
478 int num_samplers,
479 struct ilo_cp *cp)
480 {
481 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
482 const uint8_t cmd_len = 7;
483
484 ILO_GPE_VALID_GEN(dev, 7, 7.5);
485
486 assert(!hs);
487
488 ilo_cp_begin(cp, cmd_len);
489 ilo_cp_write(cp, cmd | (cmd_len - 2));
490 ilo_cp_write(cp, 0);
491 ilo_cp_write(cp, 0);
492 ilo_cp_write(cp, 0);
493 ilo_cp_write(cp, 0);
494 ilo_cp_write(cp, 0);
495 ilo_cp_write(cp, 0);
496 ilo_cp_end(cp);
497 }
498
499 static inline void
500 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
501 struct ilo_cp *cp)
502 {
503 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
504 const uint8_t cmd_len = 4;
505
506 ILO_GPE_VALID_GEN(dev, 7, 7.5);
507
508 ilo_cp_begin(cp, cmd_len);
509 ilo_cp_write(cp, cmd | (cmd_len - 2));
510 ilo_cp_write(cp, 0);
511 ilo_cp_write(cp, 0);
512 ilo_cp_write(cp, 0);
513 ilo_cp_end(cp);
514 }
515
516 static inline void
517 gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
518 const struct ilo_shader_state *ds,
519 int num_samplers,
520 struct ilo_cp *cp)
521 {
522 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
523 const uint8_t cmd_len = 6;
524
525 ILO_GPE_VALID_GEN(dev, 7, 7.5);
526
527 assert(!ds);
528
529 ilo_cp_begin(cp, cmd_len);
530 ilo_cp_write(cp, cmd | (cmd_len - 2));
531 ilo_cp_write(cp, 0);
532 ilo_cp_write(cp, 0);
533 ilo_cp_write(cp, 0);
534 ilo_cp_write(cp, 0);
535 ilo_cp_write(cp, 0);
536 ilo_cp_end(cp);
537
538 }
539
540 static inline void
541 gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
542 unsigned buffer_mask,
543 int vertex_attrib_count,
544 bool rasterizer_discard,
545 struct ilo_cp *cp)
546 {
547 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
548 const uint8_t cmd_len = 3;
549 const bool enable = (buffer_mask != 0);
550 uint32_t dw1, dw2;
551 int read_len;
552
553 ILO_GPE_VALID_GEN(dev, 7, 7.5);
554
555 if (!enable) {
556 dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT;
557 if (rasterizer_discard)
558 dw1 |= SO_RENDERING_DISABLE;
559
560 dw2 = 0;
561
562 ilo_cp_begin(cp, cmd_len);
563 ilo_cp_write(cp, cmd | (cmd_len - 2));
564 ilo_cp_write(cp, dw1);
565 ilo_cp_write(cp, dw2);
566 ilo_cp_end(cp);
567 return;
568 }
569
570 read_len = (vertex_attrib_count + 1) / 2;
571 if (!read_len)
572 read_len = 1;
573
574 dw1 = SO_FUNCTION_ENABLE |
575 0 << SO_RENDER_STREAM_SELECT_SHIFT |
576 SO_STATISTICS_ENABLE |
577 buffer_mask << 8;
578
579 if (rasterizer_discard)
580 dw1 |= SO_RENDERING_DISABLE;
581
582 /* API_OPENGL */
583 if (true)
584 dw1 |= SO_REORDER_TRAILING;
585
586 dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT |
587 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT |
588 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT |
589 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT |
590 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT |
591 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT |
592 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT |
593 (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
594
595 ilo_cp_begin(cp, cmd_len);
596 ilo_cp_write(cp, cmd | (cmd_len - 2));
597 ilo_cp_write(cp, dw1);
598 ilo_cp_write(cp, dw2);
599 ilo_cp_end(cp);
600 }
601
602 static inline void
603 gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
604 const struct ilo_rasterizer_state *rasterizer,
605 const struct ilo_shader_state *fs,
606 struct ilo_cp *cp)
607 {
608 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
609 const uint8_t cmd_len = 14;
610 uint32_t dw[13];
611
612 ILO_GPE_VALID_GEN(dev, 7, 7.5);
613
614 ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer, fs, dw, Elements(dw));
615
616 ilo_cp_begin(cp, cmd_len);
617 ilo_cp_write(cp, cmd | (cmd_len - 2));
618 ilo_cp_write_multi(cp, dw, 13);
619 ilo_cp_end(cp);
620 }
621
622 static inline void
623 gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
624 const struct ilo_shader_state *fs,
625 int num_samplers, bool dual_blend,
626 struct ilo_cp *cp)
627 {
628 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
629 const uint8_t cmd_len = 8;
630 const struct ilo_shader_cso *cso;
631 uint32_t dw2, dw4, dw5;
632
633 ILO_GPE_VALID_GEN(dev, 7, 7.5);
634
635 if (!fs) {
636 int max_threads;
637
638 /* GPU hangs if none of the dispatch enable bits is set */
639 dw4 = GEN7_PS_8_DISPATCH_ENABLE;
640
641 /* see brwCreateContext() */
642 switch (dev->gen) {
643 case ILO_GEN(7.5):
644 max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
645 dw4 |= (max_threads - 1) << HSW_PS_MAX_THREADS_SHIFT;
646 break;
647 case ILO_GEN(7):
648 default:
649 max_threads = (dev->gt == 2) ? 172 : 48;
650 dw4 |= (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT;
651 break;
652 }
653
654 ilo_cp_begin(cp, cmd_len);
655 ilo_cp_write(cp, cmd | (cmd_len - 2));
656 ilo_cp_write(cp, 0);
657 ilo_cp_write(cp, 0);
658 ilo_cp_write(cp, 0);
659 ilo_cp_write(cp, dw4);
660 ilo_cp_write(cp, 0);
661 ilo_cp_write(cp, 0);
662 ilo_cp_write(cp, 0);
663 ilo_cp_end(cp);
664
665 return;
666 }
667
668 cso = ilo_shader_get_kernel_cso(fs);
669 dw2 = cso->payload[0];
670 dw4 = cso->payload[1];
671 dw5 = cso->payload[2];
672
673 dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT;
674
675 if (dual_blend)
676 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
677
678 ilo_cp_begin(cp, cmd_len);
679 ilo_cp_write(cp, cmd | (cmd_len - 2));
680 ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
681 ilo_cp_write(cp, dw2);
682 ilo_cp_write(cp, 0); /* scratch */
683 ilo_cp_write(cp, dw4);
684 ilo_cp_write(cp, dw5);
685 ilo_cp_write(cp, 0); /* kernel 1 */
686 ilo_cp_write(cp, 0); /* kernel 2 */
687 ilo_cp_end(cp);
688 }
689
690 static inline void
691 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev,
692 uint32_t sf_clip_viewport,
693 struct ilo_cp *cp)
694 {
695 gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
696 }
697
698 static inline void
699 gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
700 uint32_t cc_viewport,
701 struct ilo_cp *cp)
702 {
703 gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
704 }
705
706 static inline void
707 gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
708 uint32_t blend_state,
709 struct ilo_cp *cp)
710 {
711 gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
712 }
713
714 static inline void
715 gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
716 uint32_t depth_stencil_state,
717 struct ilo_cp *cp)
718 {
719 gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
720 }
721
722 static inline void
723 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
724 uint32_t binding_table,
725 struct ilo_cp *cp)
726 {
727 gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
728 }
729
730 static inline void
731 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
732 uint32_t binding_table,
733 struct ilo_cp *cp)
734 {
735 gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
736 }
737
738 static inline void
739 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
740 uint32_t binding_table,
741 struct ilo_cp *cp)
742 {
743 gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
744 }
745
746 static inline void
747 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
748 uint32_t binding_table,
749 struct ilo_cp *cp)
750 {
751 gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
752 }
753
754 static inline void
755 gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
756 uint32_t binding_table,
757 struct ilo_cp *cp)
758 {
759 gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
760 }
761
762 static inline void
763 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
764 uint32_t sampler_state,
765 struct ilo_cp *cp)
766 {
767 gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
768 }
769
770 static inline void
771 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
772 uint32_t sampler_state,
773 struct ilo_cp *cp)
774 {
775 gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
776 }
777
778 static inline void
779 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
780 uint32_t sampler_state,
781 struct ilo_cp *cp)
782 {
783 gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
784 }
785
786 static inline void
787 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
788 uint32_t sampler_state,
789 struct ilo_cp *cp)
790 {
791 gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
792 }
793
794 static inline void
795 gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
796 uint32_t sampler_state,
797 struct ilo_cp *cp)
798 {
799 gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
800 }
801
802 static inline void
803 gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
804 int subop, int offset, int size,
805 int entry_size,
806 struct ilo_cp *cp)
807 {
808 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
809 const uint8_t cmd_len = 2;
810 const int row_size = 64; /* 512 bits */
811 int alloc_size, num_entries, min_entries, max_entries;
812
813 ILO_GPE_VALID_GEN(dev, 7, 7.5);
814
815 /* VS, HS, DS, and GS variants */
816 assert(subop >= 0x30 && subop <= 0x33);
817
818 /* in multiples of 8KB */
819 assert(offset % 8192 == 0);
820 offset /= 8192;
821
822 /* in multiple of 512-bit rows */
823 alloc_size = (entry_size + row_size - 1) / row_size;
824 if (!alloc_size)
825 alloc_size = 1;
826
827 /*
828 * From the Ivy Bridge PRM, volume 2 part 1, page 34:
829 *
830 * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
831 * cause performance to decrease due to banking in the URB. Element
832 * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
833 */
834 if (subop == 0x30 && alloc_size == 5)
835 alloc_size = 6;
836
837 /* in multiples of 8 */
838 num_entries = (size / row_size / alloc_size) & ~7;
839
840 switch (subop) {
841 case 0x30: /* 3DSTATE_URB_VS */
842 min_entries = 32;
843
844 switch (dev->gen) {
845 case ILO_GEN(7.5):
846 max_entries = (dev->gt >= 2) ? 1644 : 640;
847 break;
848 case ILO_GEN(7):
849 default:
850 max_entries = (dev->gt == 2) ? 704 : 512;
851 break;
852 }
853
854 assert(num_entries >= min_entries);
855 if (num_entries > max_entries)
856 num_entries = max_entries;
857 break;
858 case 0x31: /* 3DSTATE_URB_HS */
859 max_entries = (dev->gt == 2) ? 64 : 32;
860 if (num_entries > max_entries)
861 num_entries = max_entries;
862 break;
863 case 0x32: /* 3DSTATE_URB_DS */
864 if (num_entries)
865 assert(num_entries >= 138);
866 break;
867 case 0x33: /* 3DSTATE_URB_GS */
868 switch (dev->gen) {
869 case ILO_GEN(7.5):
870 max_entries = (dev->gt >= 2) ? 640 : 256;
871 break;
872 case ILO_GEN(7):
873 default:
874 max_entries = (dev->gt == 2) ? 320 : 192;
875 break;
876 }
877
878 if (num_entries > max_entries)
879 num_entries = max_entries;
880 break;
881 default:
882 break;
883 }
884
885 ilo_cp_begin(cp, cmd_len);
886 ilo_cp_write(cp, cmd | (cmd_len - 2));
887 ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT |
888 (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
889 num_entries);
890 ilo_cp_end(cp);
891 }
892
893 static inline void
894 gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
895 int offset, int size, int entry_size,
896 struct ilo_cp *cp)
897 {
898 gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
899 }
900
901 static inline void
902 gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
903 int offset, int size, int entry_size,
904 struct ilo_cp *cp)
905 {
906 gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
907 }
908
909 static inline void
910 gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
911 int offset, int size, int entry_size,
912 struct ilo_cp *cp)
913 {
914 gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
915 }
916
917 static inline void
918 gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
919 int offset, int size, int entry_size,
920 struct ilo_cp *cp)
921 {
922 gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
923 }
924
925 static inline void
926 gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
927 int subop, int offset, int size,
928 struct ilo_cp *cp)
929 {
930 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
931 const uint8_t cmd_len = 2;
932 int end;
933
934 ILO_GPE_VALID_GEN(dev, 7, 7.5);
935
936 /* VS, HS, DS, GS, and PS variants */
937 assert(subop >= 0x12 && subop <= 0x16);
938
939 /*
940 * From the Ivy Bridge PRM, volume 2 part 1, page 68:
941 *
942 * "(A table that says the maximum size of each constant buffer is
943 * 16KB")
944 *
945 * From the Ivy Bridge PRM, volume 2 part 1, page 115:
946 *
947 * "The sum of the Constant Buffer Offset and the Constant Buffer Size
948 * may not exceed the maximum value of the Constant Buffer Size."
949 *
950 * Thus, the valid range of buffer end is [0KB, 16KB].
951 */
952 end = (offset + size) / 1024;
953 if (end > 16) {
954 assert(!"invalid constant buffer end");
955 end = 16;
956 }
957
958 /* the valid range of buffer offset is [0KB, 15KB] */
959 offset = (offset + 1023) / 1024;
960 if (offset > 15) {
961 assert(!"invalid constant buffer offset");
962 offset = 15;
963 }
964
965 if (offset > end) {
966 assert(!size);
967 offset = end;
968 }
969
970 /* the valid range of buffer size is [0KB, 15KB] */
971 size = end - offset;
972 if (size > 15) {
973 assert(!"invalid constant buffer size");
974 size = 15;
975 }
976
977 ilo_cp_begin(cp, cmd_len);
978 ilo_cp_write(cp, cmd | (cmd_len - 2));
979 ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
980 size);
981 ilo_cp_end(cp);
982 }
983
984 static inline void
985 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
986 int offset, int size,
987 struct ilo_cp *cp)
988 {
989 gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
990 }
991
992 static inline void
993 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
994 int offset, int size,
995 struct ilo_cp *cp)
996 {
997 gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
998 }
999
1000 static inline void
1001 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
1002 int offset, int size,
1003 struct ilo_cp *cp)
1004 {
1005 gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
1006 }
1007
1008 static inline void
1009 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
1010 int offset, int size,
1011 struct ilo_cp *cp)
1012 {
1013 gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
1014 }
1015
1016 static inline void
1017 gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
1018 int offset, int size,
1019 struct ilo_cp *cp)
1020 {
1021 gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
1022 }
1023
1024 static inline void
1025 gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
1026 const struct pipe_stream_output_info *so_info,
1027 struct ilo_cp *cp)
1028 {
1029 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
1030 uint16_t cmd_len;
1031 int buffer_selects, num_entries, i;
1032 uint16_t so_decls[128];
1033
1034 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1035
1036 buffer_selects = 0;
1037 num_entries = 0;
1038
1039 if (so_info) {
1040 int buffer_offsets[PIPE_MAX_SO_BUFFERS];
1041
1042 memset(buffer_offsets, 0, sizeof(buffer_offsets));
1043
1044 for (i = 0; i < so_info->num_outputs; i++) {
1045 unsigned decl, buf, reg, mask;
1046
1047 buf = so_info->output[i].output_buffer;
1048
1049 /* pad with holes */
1050 assert(buffer_offsets[buf] <= so_info->output[i].dst_offset);
1051 while (buffer_offsets[buf] < so_info->output[i].dst_offset) {
1052 int num_dwords;
1053
1054 num_dwords = so_info->output[i].dst_offset - buffer_offsets[buf];
1055 if (num_dwords > 4)
1056 num_dwords = 4;
1057
1058 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1059 SO_DECL_HOLE_FLAG |
1060 ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT;
1061
1062 so_decls[num_entries++] = decl;
1063 buffer_offsets[buf] += num_dwords;
1064 }
1065
1066 reg = so_info->output[i].register_index;
1067 mask = ((1 << so_info->output[i].num_components) - 1) <<
1068 so_info->output[i].start_component;
1069
1070 decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT |
1071 reg << SO_DECL_REGISTER_INDEX_SHIFT |
1072 mask << SO_DECL_COMPONENT_MASK_SHIFT;
1073
1074 so_decls[num_entries++] = decl;
1075 buffer_selects |= 1 << buf;
1076 buffer_offsets[buf] += so_info->output[i].num_components;
1077 }
1078 }
1079
1080 /*
1081 * From the Ivy Bridge PRM, volume 2 part 1, page 201:
1082 *
1083 * "Errata: All 128 decls for all four streams must be included
1084 * whenever this command is issued. The "Num Entries [n]" fields still
1085 * contain the actual numbers of valid decls."
1086 *
1087 * Also note that "DWord Length" has 9 bits for this command, and the type
1088 * of cmd_len is thus uint16_t.
1089 */
1090 cmd_len = 2 * 128 + 3;
1091
1092 ilo_cp_begin(cp, cmd_len);
1093 ilo_cp_write(cp, cmd | (cmd_len - 2));
1094 ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT |
1095 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT |
1096 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT |
1097 buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT);
1098 ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT |
1099 0 << SO_NUM_ENTRIES_2_SHIFT |
1100 0 << SO_NUM_ENTRIES_1_SHIFT |
1101 num_entries << SO_NUM_ENTRIES_0_SHIFT);
1102
1103 for (i = 0; i < num_entries; i++) {
1104 ilo_cp_write(cp, so_decls[i]);
1105 ilo_cp_write(cp, 0);
1106 }
1107 for (; i < 128; i++) {
1108 ilo_cp_write(cp, 0);
1109 ilo_cp_write(cp, 0);
1110 }
1111
1112 ilo_cp_end(cp);
1113 }
1114
1115 static inline void
1116 gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
1117 int index, int base, int stride,
1118 const struct pipe_stream_output_target *so_target,
1119 struct ilo_cp *cp)
1120 {
1121 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
1122 const uint8_t cmd_len = 4;
1123 struct ilo_buffer *buf;
1124 int end;
1125
1126 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1127
1128 if (!so_target || !so_target->buffer) {
1129 ilo_cp_begin(cp, cmd_len);
1130 ilo_cp_write(cp, cmd | (cmd_len - 2));
1131 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT);
1132 ilo_cp_write(cp, 0);
1133 ilo_cp_write(cp, 0);
1134 ilo_cp_end(cp);
1135 return;
1136 }
1137
1138 buf = ilo_buffer(so_target->buffer);
1139
1140 /* DWord-aligned */
1141 assert(stride % 4 == 0 && base % 4 == 0);
1142 assert(so_target->buffer_offset % 4 == 0);
1143
1144 stride &= ~3;
1145 base = (base + so_target->buffer_offset) & ~3;
1146 end = (base + so_target->buffer_size) & ~3;
1147
1148 ilo_cp_begin(cp, cmd_len);
1149 ilo_cp_write(cp, cmd | (cmd_len - 2));
1150 ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT |
1151 stride);
1152 ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1153 ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
1154 ilo_cp_end(cp);
1155 }
1156
1157 static inline void
1158 gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
1159 const struct pipe_draw_info *info,
1160 const struct ilo_ib_state *ib,
1161 bool rectlist,
1162 struct ilo_cp *cp)
1163 {
1164 const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
1165 const uint8_t cmd_len = 7;
1166 const int prim = (rectlist) ?
1167 _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
1168 const int vb_access = (info->indexed) ?
1169 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
1170 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
1171 const uint32_t vb_start = info->start +
1172 ((info->indexed) ? ib->draw_start_offset : 0);
1173
1174 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1175
1176 ilo_cp_begin(cp, cmd_len);
1177 ilo_cp_write(cp, cmd | (cmd_len - 2));
1178 ilo_cp_write(cp, vb_access | prim);
1179 ilo_cp_write(cp, info->count);
1180 ilo_cp_write(cp, vb_start);
1181 ilo_cp_write(cp, info->instance_count);
1182 ilo_cp_write(cp, info->start_instance);
1183 ilo_cp_write(cp, info->index_bias);
1184 ilo_cp_end(cp);
1185 }
1186
1187 static inline uint32_t
1188 gen7_emit_SF_CLIP_VIEWPORT(const struct ilo_dev_info *dev,
1189 const struct ilo_viewport_cso *viewports,
1190 unsigned num_viewports,
1191 struct ilo_cp *cp)
1192 {
1193 const int state_align = 64 / 4;
1194 const int state_len = 16 * num_viewports;
1195 uint32_t state_offset, *dw;
1196 unsigned i;
1197
1198 ILO_GPE_VALID_GEN(dev, 7, 7.5);
1199
1200 /*
1201 * From the Ivy Bridge PRM, volume 2 part 1, page 270:
1202 *
1203 * "The viewport-specific state used by both the SF and CL units
1204 * (SF_CLIP_VIEWPORT) is stored as an array of up to 16 elements, each
1205 * of which contains the DWords described below. The start of each
1206 * element is spaced 16 DWords apart. The location of first element of
1207 * the array, as specified by both Pointer to SF_VIEWPORT and Pointer
1208 * to CLIP_VIEWPORT, is aligned to a 64-byte boundary."
1209 */
1210 assert(num_viewports && num_viewports <= 16);
1211
1212 dw = ilo_cp_steal_ptr(cp, "SF_CLIP_VIEWPORT",
1213 state_len, state_align, &state_offset);
1214
1215 for (i = 0; i < num_viewports; i++) {
1216 const struct ilo_viewport_cso *vp = &viewports[i];
1217
1218 dw[0] = fui(vp->m00);
1219 dw[1] = fui(vp->m11);
1220 dw[2] = fui(vp->m22);
1221 dw[3] = fui(vp->m30);
1222 dw[4] = fui(vp->m31);
1223 dw[5] = fui(vp->m32);
1224 dw[6] = 0;
1225 dw[7] = 0;
1226 dw[8] = fui(vp->min_gbx);
1227 dw[9] = fui(vp->max_gbx);
1228 dw[10] = fui(vp->min_gby);
1229 dw[11] = fui(vp->max_gby);
1230 dw[12] = 0;
1231 dw[13] = 0;
1232 dw[14] = 0;
1233 dw[15] = 0;
1234
1235 dw += 16;
1236 }
1237
1238 return state_offset;
1239 }
1240
1241 #endif /* ILO_GPE_GEN7_H */