2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_mi.h"
31 #include "core/ilo_builder_render.h"
32 #include "util/u_prim.h"
34 #include "ilo_blitter.h"
35 #include "ilo_query.h"
36 #include "ilo_resource.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render_gen.h"
42 * This should be called before PIPE_CONTROL.
45 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
48 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
50 * "Pipe-control with CS-stall bit set must be sent BEFORE the
51 * pipe-control with a post-sync op and no write-cache flushes."
53 * This WA may also be triggered indirectly by the other two WAs on the
56 * "Before any depth stall flush (including those produced by
57 * non-pipelined state commands), software needs to first send a
58 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
60 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
61 * PIPE_CONTROL with any non-zero post-sync-op is required."
63 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
64 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
65 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
66 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
68 ILO_DEV_ASSERT(r
->dev
, 6, 6);
70 if (!direct_wa_cond
&& !indirect_wa_cond
)
73 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
75 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
77 * "1 of the following must also be set (when CS stall is set):
79 * - Depth Cache Flush Enable ([0] of DW1)
80 * - Stall at Pixel Scoreboard ([1] of DW1)
81 * - Depth Stall ([13] of DW1)
82 * - Post-Sync Operation ([13] of DW1)
83 * - Render Target Cache Flush Enable ([12] of DW1)
84 * - Notify Enable ([8] of DW1)"
86 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
88 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
89 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
91 ilo_render_pipe_control(r
, direct_wa
);
94 if (indirect_wa_cond
&&
95 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
96 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
98 ilo_render_pipe_control(r
, indirect_wa
);
103 * This should be called before any non-pipelined state command.
106 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
108 ILO_DEV_ASSERT(r
->dev
, 6, 6);
110 /* non-pipelined state commands produce depth stall */
111 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
115 gen6_wa_post_3dstate_urb_no_gs(struct ilo_render
*r
)
118 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
120 * "Because of a urb corruption caused by allocating a previous
121 * gsunit's urb entry to vsunit software is required to send a
122 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
123 * size == 0) plus a dummy DRAW call before any case where VS will
124 * be taking over GS URB space."
126 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
128 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
129 gen6_wa_pre_pipe_control(r
, dw1
);
130 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
131 ilo_render_pipe_control(r
, dw1
);
135 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
138 * According to upload_vs_state() of the classic driver, we need to emit a
139 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
140 * being buffered by VS FF, to the point that the FF dies.
142 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
143 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
144 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
146 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
147 gen6_wa_pre_pipe_control(r
, dw1
);
148 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
149 ilo_render_pipe_control(r
, dw1
);
153 gen6_wa_pre_3dstate_vs_toggle(struct ilo_render
*r
)
156 * The classic driver has this undocumented WA:
158 * From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
159 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
161 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
162 * command that causes the VS Function Enable to toggle. Pipeline
163 * flush can be executed by sending a PIPE_CONTROL command with CS
164 * stall bit set and a post sync operation.
166 const uint32_t dw1
= GEN6_PIPE_CONTROL_WRITE_IMM
|
167 GEN6_PIPE_CONTROL_CS_STALL
;
169 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
170 gen6_wa_pre_pipe_control(r
, dw1
);
171 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
172 ilo_render_pipe_control(r
, dw1
);
176 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
179 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
181 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
182 * field set (DW1 Bit 1), must be issued prior to any change to the
183 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
185 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
187 ILO_DEV_ASSERT(r
->dev
, 6, 6);
189 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
190 gen6_wa_pre_pipe_control(r
, dw1
);
191 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
192 ilo_render_pipe_control(r
, dw1
);
196 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
199 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
201 * "Driver must guarentee that all the caches in the depth pipe are
202 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
203 * requires driver to send a PIPE_CONTROL with a CS stall along with a
204 * Depth Flush prior to this command."
206 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
207 GEN6_PIPE_CONTROL_CS_STALL
;
209 ILO_DEV_ASSERT(r
->dev
, 6, 6);
211 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
212 gen6_wa_pre_pipe_control(r
, dw1
);
213 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
214 ilo_render_pipe_control(r
, dw1
);
218 gen6_wa_pre_depth(struct ilo_render
*r
)
220 ILO_DEV_ASSERT(r
->dev
, 6, 6);
223 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
225 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
226 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
227 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
228 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
229 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
230 * Depth Flush Bit set, followed by another pipelined depth stall
231 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
232 * guarantee that the pipeline from WM onwards is already flushed
233 * (e.g., via a preceding MI_FLUSH)."
235 * According to the classic driver, it also applies for GEN6.
237 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
238 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
240 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
241 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
242 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
245 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
248 gen6_draw_common_select(struct ilo_render
*r
,
249 const struct ilo_state_vector
*vec
,
250 struct ilo_render_draw_session
*session
)
252 /* PIPELINE_SELECT */
253 if (r
->hw_ctx_changed
) {
254 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
255 gen6_wa_pre_non_pipelined(r
);
257 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
262 gen6_draw_common_sip(struct ilo_render
*r
,
263 const struct ilo_state_vector
*vec
,
264 struct ilo_render_draw_session
*session
)
267 if (r
->hw_ctx_changed
) {
268 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
269 gen6_wa_pre_non_pipelined(r
);
271 gen6_STATE_SIP(r
->builder
, 0);
276 gen6_draw_common_base_address(struct ilo_render
*r
,
277 const struct ilo_state_vector
*vec
,
278 struct ilo_render_draw_session
*session
)
280 /* STATE_BASE_ADDRESS */
281 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
282 r
->batch_bo_changed
) {
283 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
284 gen6_wa_pre_non_pipelined(r
);
286 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
287 gen8_state_base_address(r
->builder
, r
->hw_ctx_changed
);
289 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
292 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
294 * "The following commands must be reissued following any change to
295 * the base addresses:
297 * * 3DSTATE_BINDING_TABLE_POINTERS
298 * * 3DSTATE_SAMPLER_STATE_POINTERS
299 * * 3DSTATE_VIEWPORT_STATE_POINTERS
300 * * 3DSTATE_CC_POINTERS
301 * * MEDIA_STATE_POINTERS"
303 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
304 * reasonable to also reissue the command. Same to PCB.
306 session
->viewport_changed
= true;
308 session
->scissor_changed
= true;
310 session
->blend_changed
= true;
311 session
->dsa_changed
= true;
312 session
->cc_changed
= true;
314 session
->sampler_vs_changed
= true;
315 session
->sampler_gs_changed
= true;
316 session
->sampler_fs_changed
= true;
318 session
->pcb_vs_changed
= true;
319 session
->pcb_gs_changed
= true;
320 session
->pcb_fs_changed
= true;
322 session
->binding_table_vs_changed
= true;
323 session
->binding_table_gs_changed
= true;
324 session
->binding_table_fs_changed
= true;
329 gen6_draw_common_urb(struct ilo_render
*r
,
330 const struct ilo_state_vector
*vec
,
331 struct ilo_render_draw_session
*session
)
333 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
334 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
337 if (session
->urb_delta
.dirty
& (ILO_STATE_URB_3DSTATE_URB_VS
|
338 ILO_STATE_URB_3DSTATE_URB_GS
)) {
339 gen6_3DSTATE_URB(r
->builder
, &vec
->urb
);
341 if (r
->state
.gs
.active
&& !gs_active
)
342 gen6_wa_post_3dstate_urb_no_gs(r
);
345 r
->state
.gs
.active
= gs_active
;
349 gen6_draw_common_pointers_1(struct ilo_render
*r
,
350 const struct ilo_state_vector
*vec
,
351 struct ilo_render_draw_session
*session
)
353 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
354 if (session
->viewport_changed
) {
355 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
356 r
->state
.CLIP_VIEWPORT
,
357 r
->state
.SF_VIEWPORT
,
358 r
->state
.CC_VIEWPORT
);
363 gen6_draw_common_pointers_2(struct ilo_render
*r
,
364 const struct ilo_state_vector
*vec
,
365 struct ilo_render_draw_session
*session
)
367 /* 3DSTATE_CC_STATE_POINTERS */
368 if (session
->blend_changed
||
369 session
->dsa_changed
||
370 session
->cc_changed
) {
371 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
372 r
->state
.BLEND_STATE
,
373 r
->state
.DEPTH_STENCIL_STATE
,
374 r
->state
.COLOR_CALC_STATE
);
377 /* 3DSTATE_SAMPLER_STATE_POINTERS */
378 if (session
->sampler_vs_changed
||
379 session
->sampler_gs_changed
||
380 session
->sampler_fs_changed
) {
381 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
382 r
->state
.vs
.SAMPLER_STATE
,
384 r
->state
.wm
.SAMPLER_STATE
);
389 gen6_draw_common_pointers_3(struct ilo_render
*r
,
390 const struct ilo_state_vector
*vec
,
391 struct ilo_render_draw_session
*session
)
393 /* 3DSTATE_SCISSOR_STATE_POINTERS */
394 if (session
->scissor_changed
) {
395 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
396 r
->state
.SCISSOR_RECT
);
399 /* 3DSTATE_BINDING_TABLE_POINTERS */
400 if (session
->binding_table_vs_changed
||
401 session
->binding_table_gs_changed
||
402 session
->binding_table_fs_changed
) {
403 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
404 r
->state
.vs
.BINDING_TABLE_STATE
,
405 r
->state
.gs
.BINDING_TABLE_STATE
,
406 r
->state
.wm
.BINDING_TABLE_STATE
);
411 gen6_draw_vf(struct ilo_render
*r
,
412 const struct ilo_state_vector
*vec
,
413 struct ilo_render_draw_session
*session
)
415 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
416 /* 3DSTATE_INDEX_BUFFER */
417 if ((session
->vf_delta
.dirty
& ILO_STATE_VF_3DSTATE_INDEX_BUFFER
) ||
418 DIRTY(IB
) || r
->batch_bo_changed
)
419 gen6_3DSTATE_INDEX_BUFFER(r
->builder
, &vec
->ve
->vf
, &vec
->ib
.ib
);
422 if (session
->vf_delta
.dirty
& ILO_STATE_VF_3DSTATE_VF
)
423 gen75_3DSTATE_VF(r
->builder
, &vec
->ve
->vf
);
425 /* 3DSTATE_INDEX_BUFFER */
426 if ((session
->vf_delta
.dirty
& ILO_STATE_VF_3DSTATE_INDEX_BUFFER
) ||
427 DIRTY(IB
) || r
->batch_bo_changed
)
428 gen6_3DSTATE_INDEX_BUFFER(r
->builder
, &vec
->ve
->vf
, &vec
->ib
.ib
);
431 /* 3DSTATE_VERTEX_BUFFERS */
432 if ((session
->vf_delta
.dirty
& ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS
) ||
433 DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
) {
434 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, &vec
->ve
->vf
,
435 vec
->vb
.vb
, vec
->ve
->vb_count
);
438 /* 3DSTATE_VERTEX_ELEMENTS */
439 if (session
->vf_delta
.dirty
& ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS
)
440 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &vec
->ve
->vf
);
444 gen6_draw_vf_statistics(struct ilo_render
*r
,
445 const struct ilo_state_vector
*vec
,
446 struct ilo_render_draw_session
*session
)
448 /* 3DSTATE_VF_STATISTICS */
449 if (r
->hw_ctx_changed
)
450 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
454 gen6_draw_vs(struct ilo_render
*r
,
455 const struct ilo_state_vector
*vec
,
456 struct ilo_render_draw_session
*session
)
458 /* 3DSTATE_CONSTANT_VS */
459 if (session
->pcb_vs_changed
) {
460 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
461 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
462 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
465 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
466 gen6_wa_post_3dstate_constant_vs(r
);
470 if (DIRTY(VS
) || r
->instruction_bo_changed
) {
471 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->vs
);
472 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->vs
);
474 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
475 gen6_wa_pre_3dstate_vs_toggle(r
);
477 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) &&
478 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
))
479 gen6_3DSTATE_VS(r
->builder
, &cso
->vs_sol
.vs
, kernel_offset
);
481 gen6_3DSTATE_VS(r
->builder
, &cso
->vs
, kernel_offset
);
486 gen6_draw_gs(struct ilo_render
*r
,
487 const struct ilo_state_vector
*vec
,
488 struct ilo_render_draw_session
*session
)
490 /* 3DSTATE_CONSTANT_GS */
491 if (session
->pcb_gs_changed
)
492 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
495 if (DIRTY(GS
) || DIRTY(VS
) ||
496 session
->prim_changed
|| r
->instruction_bo_changed
) {
497 const union ilo_shader_cso
*cso
;
498 uint32_t kernel_offset
;
501 cso
= ilo_shader_get_kernel_cso(vec
->gs
);
502 kernel_offset
= ilo_shader_get_kernel_offset(vec
->gs
);
504 gen6_3DSTATE_GS(r
->builder
, &cso
->gs
, kernel_offset
);
505 } else if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) &&
506 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)) {
507 const int verts_per_prim
=
508 u_vertices_per_prim(session
->reduced_prim
);
509 enum ilo_kernel_param param
;
511 switch (verts_per_prim
) {
513 param
= ILO_KERNEL_VS_GEN6_SO_POINT_OFFSET
;
516 param
= ILO_KERNEL_VS_GEN6_SO_LINE_OFFSET
;
519 param
= ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET
;
523 cso
= ilo_shader_get_kernel_cso(vec
->vs
);
524 kernel_offset
= ilo_shader_get_kernel_offset(vec
->vs
) +
525 ilo_shader_get_kernel_param(vec
->vs
, param
);
527 gen6_3DSTATE_GS(r
->builder
, &cso
->vs_sol
.sol
, kernel_offset
);
529 gen6_3DSTATE_GS(r
->builder
, &vec
->disabled_gs
, 0);
535 gen6_draw_update_max_svbi(struct ilo_render
*r
,
536 const struct ilo_state_vector
*vec
,
537 struct ilo_render_draw_session
*session
)
539 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
540 const struct pipe_stream_output_info
*so_info
=
541 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
542 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
543 unsigned max_svbi
= 0xffffffff;
546 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
547 const int output_buffer
= so_info
->output
[i
].output_buffer
;
548 const struct pipe_stream_output_target
*so
=
549 vec
->so
.states
[output_buffer
];
550 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
551 const int elem_size
= so_info
->output
[i
].num_components
* 4;
559 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
561 count
= buf_size
/ struct_size
;
562 if (buf_size
% struct_size
>= elem_size
)
565 if (count
< max_svbi
)
569 if (r
->state
.so_max_vertices
!= max_svbi
) {
570 r
->state
.so_max_vertices
= max_svbi
;
579 gen6_draw_gs_svbi(struct ilo_render
*r
,
580 const struct ilo_state_vector
*vec
,
581 struct ilo_render_draw_session
*session
)
583 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
585 /* 3DSTATE_GS_SVB_INDEX */
587 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
588 gen6_wa_pre_non_pipelined(r
);
590 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
591 0, 0, r
->state
.so_max_vertices
,
594 if (r
->hw_ctx_changed
) {
598 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
600 * "If a buffer is not enabled then the SVBI must be set to 0x0
601 * in order to not cause overflow in that SVBI."
603 * "If a buffer is not enabled then the MaxSVBI must be set to
604 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
606 for (i
= 1; i
< 4; i
++) {
607 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
608 i
, 0, 0xffffffff, false);
615 gen6_draw_clip(struct ilo_render
*r
,
616 const struct ilo_state_vector
*vec
,
617 struct ilo_render_draw_session
*session
)
620 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_CLIP
)
621 gen6_3DSTATE_CLIP(r
->builder
, &vec
->rasterizer
->rs
);
625 gen6_draw_sf(struct ilo_render
*r
,
626 const struct ilo_state_vector
*vec
,
627 struct ilo_render_draw_session
*session
)
630 if ((session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SF
) || DIRTY(FS
)) {
631 const struct ilo_state_sbe
*sbe
= ilo_shader_get_kernel_sbe(vec
->fs
);
632 gen6_3DSTATE_SF(r
->builder
, &vec
->rasterizer
->rs
, sbe
);
637 gen6_draw_sf_rect(struct ilo_render
*r
,
638 const struct ilo_state_vector
*vec
,
639 struct ilo_render_draw_session
*session
)
641 /* 3DSTATE_DRAWING_RECTANGLE */
643 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
644 gen6_wa_pre_non_pipelined(r
);
646 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
647 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
652 gen6_draw_wm(struct ilo_render
*r
,
653 const struct ilo_state_vector
*vec
,
654 struct ilo_render_draw_session
*session
)
656 /* 3DSTATE_CONSTANT_PS */
657 if (session
->pcb_fs_changed
) {
658 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
659 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
660 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
666 (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_WM
) ||
667 r
->instruction_bo_changed
) {
668 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->fs
);
669 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->fs
);
671 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
672 gen6_wa_pre_3dstate_wm_max_threads(r
);
674 gen6_3DSTATE_WM(r
->builder
, &vec
->rasterizer
->rs
,
675 &cso
->ps
, kernel_offset
);
680 gen6_draw_wm_multisample(struct ilo_render
*r
,
681 const struct ilo_state_vector
*vec
,
682 struct ilo_render_draw_session
*session
)
684 /* 3DSTATE_MULTISAMPLE */
685 if (DIRTY(FB
) || (session
->rs_delta
.dirty
&
686 ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
)) {
687 const uint8_t sample_count
= (vec
->fb
.num_samples
> 1) ? 4 : 1;
689 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
690 gen6_wa_pre_non_pipelined(r
);
691 gen6_wa_pre_3dstate_multisample(r
);
694 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &vec
->rasterizer
->rs
,
695 &r
->sample_pattern
, sample_count
);
698 /* 3DSTATE_SAMPLE_MASK */
699 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
)
700 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &vec
->rasterizer
->rs
);
704 gen6_draw_wm_depth(struct ilo_render
*r
,
705 const struct ilo_state_vector
*vec
,
706 struct ilo_render_draw_session
*session
)
708 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
709 if (DIRTY(FB
) || r
->batch_bo_changed
) {
710 const struct ilo_state_zs
*zs
;
711 uint32_t clear_params
;
713 if (vec
->fb
.state
.zsbuf
) {
714 const struct ilo_surface_cso
*surface
=
715 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
716 const struct ilo_texture_slice
*slice
=
717 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
718 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
720 assert(!surface
->is_rt
);
723 clear_params
= slice
->clear_value
;
726 zs
= &vec
->fb
.null_zs
;
730 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
731 gen6_wa_pre_non_pipelined(r
);
732 gen6_wa_pre_depth(r
);
735 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
736 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
737 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
738 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
743 gen6_draw_wm_raster(struct ilo_render
*r
,
744 const struct ilo_state_vector
*vec
,
745 struct ilo_render_draw_session
*session
)
747 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
748 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
749 vec
->rasterizer
->state
.poly_stipple_enable
) {
750 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
751 gen6_wa_pre_non_pipelined(r
);
753 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
, &vec
->poly_stipple
);
754 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, &vec
->poly_stipple
);
757 /* 3DSTATE_LINE_STIPPLE */
758 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
759 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
760 gen6_wa_pre_non_pipelined(r
);
762 gen6_3DSTATE_LINE_STIPPLE(r
->builder
, &vec
->line_stipple
);
765 /* 3DSTATE_AA_LINE_PARAMETERS */
766 if (session
->rs_delta
.dirty
&
767 ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS
) {
768 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
769 gen6_wa_pre_non_pipelined(r
);
771 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
, &vec
->rasterizer
->rs
);
778 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
779 const struct ilo_state_vector
*vec
,
780 struct ilo_render_draw_session
*session
)
782 ILO_DEV_ASSERT(render
->dev
, 6, 6);
785 * We try to keep the order of the commands match, as closely as possible,
786 * that of the classic i965 driver. It allows us to compare the command
789 gen6_draw_common_select(render
, vec
, session
);
790 gen6_draw_gs_svbi(render
, vec
, session
);
791 gen6_draw_common_sip(render
, vec
, session
);
792 gen6_draw_vf_statistics(render
, vec
, session
);
793 gen6_draw_common_base_address(render
, vec
, session
);
794 gen6_draw_common_pointers_1(render
, vec
, session
);
795 gen6_draw_common_urb(render
, vec
, session
);
796 gen6_draw_common_pointers_2(render
, vec
, session
);
797 gen6_draw_wm_multisample(render
, vec
, session
);
798 gen6_draw_vs(render
, vec
, session
);
799 gen6_draw_gs(render
, vec
, session
);
800 gen6_draw_clip(render
, vec
, session
);
801 gen6_draw_sf(render
, vec
, session
);
802 gen6_draw_wm(render
, vec
, session
);
803 gen6_draw_common_pointers_3(render
, vec
, session
);
804 gen6_draw_wm_depth(render
, vec
, session
);
805 gen6_draw_wm_raster(render
, vec
, session
);
806 gen6_draw_sf_rect(render
, vec
, session
);
807 gen6_draw_vf(render
, vec
, session
);
809 ilo_render_3dprimitive(render
, &vec
->draw_info
);
813 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
814 const struct ilo_blitter
*blitter
)
816 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
817 gen6_wa_post_3dstate_constant_vs(r
);
819 gen6_wa_pre_3dstate_vs_toggle(r
);
820 gen6_3DSTATE_VS(r
->builder
, &blitter
->vs
, 0);
822 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
823 gen6_3DSTATE_GS(r
->builder
, &blitter
->gs
, 0);
825 gen6_3DSTATE_CLIP(r
->builder
, &blitter
->fb
.rs
);
826 gen6_3DSTATE_SF(r
->builder
, &blitter
->fb
.rs
, &blitter
->sbe
);
830 gen6_rectlist_wm(struct ilo_render
*r
,
831 const struct ilo_blitter
*blitter
)
833 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
835 gen6_wa_pre_3dstate_wm_max_threads(r
);
836 gen6_3DSTATE_WM(r
->builder
, &blitter
->fb
.rs
, &blitter
->ps
, 0);
840 gen6_rectlist_wm_depth(struct ilo_render
*r
,
841 const struct ilo_blitter
*blitter
)
843 gen6_wa_pre_depth(r
);
845 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
846 ILO_BLITTER_USE_FB_STENCIL
))
847 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
849 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
850 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
851 &blitter
->fb
.dst
.u
.zs
);
854 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
855 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
856 &blitter
->fb
.dst
.u
.zs
);
859 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
860 blitter
->depth_clear_value
);
864 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
865 const struct ilo_blitter
*blitter
)
867 const uint8_t sample_count
= (blitter
->fb
.num_samples
> 1) ? 4 : 1;
869 gen6_wa_pre_3dstate_multisample(r
);
871 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &blitter
->fb
.rs
, &r
->sample_pattern
, sample_count
);
872 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &blitter
->fb
.rs
);
876 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
877 const struct ilo_blitter
*blitter
)
879 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
885 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
886 const struct ilo_blitter
*blitter
,
887 const struct ilo_render_rectlist_session
*session
)
889 ILO_DEV_ASSERT(r
->dev
, 6, 6);
891 gen6_wa_pre_non_pipelined(r
);
893 gen6_rectlist_wm_multisample(r
, blitter
);
895 gen6_state_base_address(r
->builder
, true);
897 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
898 session
->vb_start
, session
->vb_end
,
899 sizeof(blitter
->vertices
[0]));
901 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->vf
);
903 gen6_3DSTATE_URB(r
->builder
, &blitter
->urb
);
905 if (r
->state
.gs
.active
) {
906 gen6_wa_post_3dstate_urb_no_gs(r
);
907 r
->state
.gs
.active
= false;
911 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
912 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
913 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
916 gen6_rectlist_vs_to_sf(r
, blitter
);
917 gen6_rectlist_wm(r
, blitter
);
919 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
920 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
921 0, 0, r
->state
.CC_VIEWPORT
);
924 gen6_rectlist_wm_depth(r
, blitter
);
926 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
927 blitter
->fb
.width
, blitter
->fb
.height
);
929 ilo_render_3dprimitive(r
, &blitter
->draw_info
);
933 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
934 const struct ilo_state_vector
*vec
)
938 ILO_DEV_ASSERT(render
->dev
, 6, 6);
941 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
942 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
943 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
946 GEN6_STATE_BASE_ADDRESS__SIZE
+
947 GEN6_STATE_SIP__SIZE
+
948 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
949 GEN6_PIPELINE_SELECT__SIZE
+
950 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
951 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
952 GEN6_3DSTATE_URB__SIZE
+
953 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
954 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
955 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
956 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
957 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
958 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
959 GEN6_3DSTATE_VS__SIZE
+
960 GEN6_3DSTATE_GS__SIZE
+
961 GEN6_3DSTATE_CLIP__SIZE
+
962 GEN6_3DSTATE_SF__SIZE
+
963 GEN6_3DSTATE_WM__SIZE
+
964 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
965 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
966 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
967 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
968 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
969 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
970 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
971 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
972 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
973 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
974 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
975 GEN6_3DPRIMITIVE__SIZE
;