2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_mi.h"
31 #include "core/ilo_builder_render.h"
32 #include "util/u_prim.h"
34 #include "ilo_blitter.h"
35 #include "ilo_query.h"
36 #include "ilo_shader.h"
37 #include "ilo_state.h"
38 #include "ilo_render_gen.h"
41 * This should be called before PIPE_CONTROL.
44 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
47 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
49 * "Pipe-control with CS-stall bit set must be sent BEFORE the
50 * pipe-control with a post-sync op and no write-cache flushes."
52 * This WA may also be triggered indirectly by the other two WAs on the
55 * "Before any depth stall flush (including those produced by
56 * non-pipelined state commands), software needs to first send a
57 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
59 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
60 * PIPE_CONTROL with any non-zero post-sync-op is required."
62 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
63 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
64 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
65 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
67 ILO_DEV_ASSERT(r
->dev
, 6, 6);
69 if (!direct_wa_cond
&& !indirect_wa_cond
)
72 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
74 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
76 * "1 of the following must also be set (when CS stall is set):
78 * - Depth Cache Flush Enable ([0] of DW1)
79 * - Stall at Pixel Scoreboard ([1] of DW1)
80 * - Depth Stall ([13] of DW1)
81 * - Post-Sync Operation ([13] of DW1)
82 * - Render Target Cache Flush Enable ([12] of DW1)
83 * - Notify Enable ([8] of DW1)"
85 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
87 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
88 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
90 ilo_render_pipe_control(r
, direct_wa
);
93 if (indirect_wa_cond
&&
94 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
95 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
97 ilo_render_pipe_control(r
, indirect_wa
);
102 * This should be called before any non-pipelined state command.
105 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
107 ILO_DEV_ASSERT(r
->dev
, 6, 6);
109 /* non-pipelined state commands produce depth stall */
110 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
114 gen6_wa_post_3dstate_urb_no_gs(struct ilo_render
*r
)
117 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
119 * "Because of a urb corruption caused by allocating a previous
120 * gsunit's urb entry to vsunit software is required to send a
121 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
122 * size == 0) plus a dummy DRAW call before any case where VS will
123 * be taking over GS URB space."
125 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
127 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
128 gen6_wa_pre_pipe_control(r
, dw1
);
129 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
130 ilo_render_pipe_control(r
, dw1
);
134 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
137 * According to upload_vs_state() of the classic driver, we need to emit a
138 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
139 * being buffered by VS FF, to the point that the FF dies.
141 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
142 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
143 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
145 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
146 gen6_wa_pre_pipe_control(r
, dw1
);
147 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
148 ilo_render_pipe_control(r
, dw1
);
152 gen6_wa_pre_3dstate_vs_toggle(struct ilo_render
*r
)
155 * The classic driver has this undocumented WA:
157 * From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
158 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
160 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
161 * command that causes the VS Function Enable to toggle. Pipeline
162 * flush can be executed by sending a PIPE_CONTROL command with CS
163 * stall bit set and a post sync operation.
165 const uint32_t dw1
= GEN6_PIPE_CONTROL_WRITE_IMM
|
166 GEN6_PIPE_CONTROL_CS_STALL
;
168 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
169 gen6_wa_pre_pipe_control(r
, dw1
);
170 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
171 ilo_render_pipe_control(r
, dw1
);
175 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
178 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
180 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
181 * field set (DW1 Bit 1), must be issued prior to any change to the
182 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
184 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
186 ILO_DEV_ASSERT(r
->dev
, 6, 6);
188 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
189 gen6_wa_pre_pipe_control(r
, dw1
);
190 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
191 ilo_render_pipe_control(r
, dw1
);
195 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
198 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
200 * "Driver must guarentee that all the caches in the depth pipe are
201 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
202 * requires driver to send a PIPE_CONTROL with a CS stall along with a
203 * Depth Flush prior to this command."
205 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
206 GEN6_PIPE_CONTROL_CS_STALL
;
208 ILO_DEV_ASSERT(r
->dev
, 6, 6);
210 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
211 gen6_wa_pre_pipe_control(r
, dw1
);
212 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
213 ilo_render_pipe_control(r
, dw1
);
217 gen6_wa_pre_depth(struct ilo_render
*r
)
219 ILO_DEV_ASSERT(r
->dev
, 6, 6);
222 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
224 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
225 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
226 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
227 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
228 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
229 * Depth Flush Bit set, followed by another pipelined depth stall
230 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
231 * guarantee that the pipeline from WM onwards is already flushed
232 * (e.g., via a preceding MI_FLUSH)."
234 * According to the classic driver, it also applies for GEN6.
236 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
237 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
239 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
240 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
241 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
244 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
247 gen6_draw_common_select(struct ilo_render
*r
,
248 const struct ilo_state_vector
*vec
,
249 struct ilo_render_draw_session
*session
)
251 /* PIPELINE_SELECT */
252 if (r
->hw_ctx_changed
) {
253 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
254 gen6_wa_pre_non_pipelined(r
);
256 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
261 gen6_draw_common_sip(struct ilo_render
*r
,
262 const struct ilo_state_vector
*vec
,
263 struct ilo_render_draw_session
*session
)
266 if (r
->hw_ctx_changed
) {
267 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
268 gen6_wa_pre_non_pipelined(r
);
270 gen6_STATE_SIP(r
->builder
, 0);
275 gen6_draw_common_base_address(struct ilo_render
*r
,
276 const struct ilo_state_vector
*vec
,
277 struct ilo_render_draw_session
*session
)
279 /* STATE_BASE_ADDRESS */
280 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
281 r
->batch_bo_changed
) {
282 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
283 gen6_wa_pre_non_pipelined(r
);
285 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
286 gen8_state_base_address(r
->builder
, r
->hw_ctx_changed
);
288 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
291 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
293 * "The following commands must be reissued following any change to
294 * the base addresses:
296 * * 3DSTATE_BINDING_TABLE_POINTERS
297 * * 3DSTATE_SAMPLER_STATE_POINTERS
298 * * 3DSTATE_VIEWPORT_STATE_POINTERS
299 * * 3DSTATE_CC_POINTERS
300 * * MEDIA_STATE_POINTERS"
302 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
303 * reasonable to also reissue the command. Same to PCB.
305 session
->viewport_changed
= true;
307 session
->scissor_changed
= true;
309 session
->blend_changed
= true;
310 session
->dsa_changed
= true;
311 session
->cc_changed
= true;
313 session
->sampler_vs_changed
= true;
314 session
->sampler_gs_changed
= true;
315 session
->sampler_fs_changed
= true;
317 session
->pcb_vs_changed
= true;
318 session
->pcb_gs_changed
= true;
319 session
->pcb_fs_changed
= true;
321 session
->binding_table_vs_changed
= true;
322 session
->binding_table_gs_changed
= true;
323 session
->binding_table_fs_changed
= true;
328 gen6_draw_common_urb(struct ilo_render
*r
,
329 const struct ilo_state_vector
*vec
,
330 struct ilo_render_draw_session
*session
)
333 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
334 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
335 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
336 int vs_entry_size
, gs_entry_size
;
337 int vs_total_size
, gs_total_size
;
339 vs_entry_size
= (vec
->vs
) ?
340 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
343 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
344 * share VUE handles. The VUE allocation size must be large enough to
345 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
347 * I am not sure if the PRM explicitly states that VF and VS share VUE
348 * handles. But here is a citation that implies so:
350 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
352 * "Once a FF stage that spawn threads has sufficient input to
353 * initiate a thread, it must guarantee that it is safe to request
354 * the thread initiation. For all these FF stages, this check is
357 * - The availability of output URB entries:
358 * - VS: As the input URB entries are overwritten with the
359 * VS-generated output data, output URB availability isn't a
362 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
363 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
365 gs_entry_size
= (vec
->gs
) ?
366 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
367 (gs_active
) ? vs_entry_size
: 0;
370 vs_entry_size
*= sizeof(float) * 4;
371 gs_entry_size
*= sizeof(float) * 4;
372 vs_total_size
= r
->dev
->urb_size
;
376 gs_total_size
= vs_total_size
;
382 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
383 vs_entry_size
, gs_entry_size
);
385 if (r
->state
.gs
.active
&& !gs_active
)
386 gen6_wa_post_3dstate_urb_no_gs(r
);
388 r
->state
.gs
.active
= gs_active
;
393 gen6_draw_common_pointers_1(struct ilo_render
*r
,
394 const struct ilo_state_vector
*vec
,
395 struct ilo_render_draw_session
*session
)
397 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
398 if (session
->viewport_changed
) {
399 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
400 r
->state
.CLIP_VIEWPORT
,
401 r
->state
.SF_VIEWPORT
,
402 r
->state
.CC_VIEWPORT
);
407 gen6_draw_common_pointers_2(struct ilo_render
*r
,
408 const struct ilo_state_vector
*vec
,
409 struct ilo_render_draw_session
*session
)
411 /* 3DSTATE_CC_STATE_POINTERS */
412 if (session
->blend_changed
||
413 session
->dsa_changed
||
414 session
->cc_changed
) {
415 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
416 r
->state
.BLEND_STATE
,
417 r
->state
.DEPTH_STENCIL_STATE
,
418 r
->state
.COLOR_CALC_STATE
);
421 /* 3DSTATE_SAMPLER_STATE_POINTERS */
422 if (session
->sampler_vs_changed
||
423 session
->sampler_gs_changed
||
424 session
->sampler_fs_changed
) {
425 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
426 r
->state
.vs
.SAMPLER_STATE
,
428 r
->state
.wm
.SAMPLER_STATE
);
433 gen6_draw_common_pointers_3(struct ilo_render
*r
,
434 const struct ilo_state_vector
*vec
,
435 struct ilo_render_draw_session
*session
)
437 /* 3DSTATE_SCISSOR_STATE_POINTERS */
438 if (session
->scissor_changed
) {
439 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
440 r
->state
.SCISSOR_RECT
);
443 /* 3DSTATE_BINDING_TABLE_POINTERS */
444 if (session
->binding_table_vs_changed
||
445 session
->binding_table_gs_changed
||
446 session
->binding_table_fs_changed
) {
447 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
448 r
->state
.vs
.BINDING_TABLE_STATE
,
449 r
->state
.gs
.BINDING_TABLE_STATE
,
450 r
->state
.wm
.BINDING_TABLE_STATE
);
455 gen6_draw_vf(struct ilo_render
*r
,
456 const struct ilo_state_vector
*vec
,
457 struct ilo_render_draw_session
*session
)
459 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
460 /* 3DSTATE_INDEX_BUFFER */
461 if (DIRTY(IB
) || r
->batch_bo_changed
) {
462 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
467 if (session
->primitive_restart_changed
) {
468 gen75_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
469 vec
->draw
->restart_index
);
473 /* 3DSTATE_INDEX_BUFFER */
474 if (DIRTY(IB
) || session
->primitive_restart_changed
||
475 r
->batch_bo_changed
) {
476 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
477 &vec
->ib
, vec
->draw
->primitive_restart
);
481 /* 3DSTATE_VERTEX_BUFFERS */
482 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
483 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
485 /* 3DSTATE_VERTEX_ELEMENTS */
487 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, vec
->ve
);
491 gen6_draw_vf_statistics(struct ilo_render
*r
,
492 const struct ilo_state_vector
*vec
,
493 struct ilo_render_draw_session
*session
)
495 /* 3DSTATE_VF_STATISTICS */
496 if (r
->hw_ctx_changed
)
497 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
501 gen6_draw_vs(struct ilo_render
*r
,
502 const struct ilo_state_vector
*vec
,
503 struct ilo_render_draw_session
*session
)
505 /* 3DSTATE_CONSTANT_VS */
506 if (session
->pcb_vs_changed
) {
507 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
508 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
509 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
512 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
513 gen6_wa_post_3dstate_constant_vs(r
);
517 if (DIRTY(VS
) || r
->instruction_bo_changed
) {
518 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
519 gen6_wa_pre_3dstate_vs_toggle(r
);
521 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
526 gen6_draw_gs(struct ilo_render
*r
,
527 const struct ilo_state_vector
*vec
,
528 struct ilo_render_draw_session
*session
)
530 /* 3DSTATE_CONSTANT_GS */
531 if (session
->pcb_gs_changed
)
532 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
535 if (DIRTY(GS
) || DIRTY(VS
) ||
536 session
->prim_changed
|| r
->instruction_bo_changed
) {
538 gen6_3DSTATE_GS(r
->builder
, vec
->gs
);
539 } else if (vec
->vs
&&
540 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)) {
541 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
542 gen6_so_3DSTATE_GS(r
->builder
, vec
->vs
, verts_per_prim
);
544 gen6_disable_3DSTATE_GS(r
->builder
);
550 gen6_draw_update_max_svbi(struct ilo_render
*r
,
551 const struct ilo_state_vector
*vec
,
552 struct ilo_render_draw_session
*session
)
554 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
555 const struct pipe_stream_output_info
*so_info
=
556 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
557 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
558 unsigned max_svbi
= 0xffffffff;
561 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
562 const int output_buffer
= so_info
->output
[i
].output_buffer
;
563 const struct pipe_stream_output_target
*so
=
564 vec
->so
.states
[output_buffer
];
565 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
566 const int elem_size
= so_info
->output
[i
].num_components
* 4;
574 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
576 count
= buf_size
/ struct_size
;
577 if (buf_size
% struct_size
>= elem_size
)
580 if (count
< max_svbi
)
584 if (r
->state
.so_max_vertices
!= max_svbi
) {
585 r
->state
.so_max_vertices
= max_svbi
;
594 gen6_draw_gs_svbi(struct ilo_render
*r
,
595 const struct ilo_state_vector
*vec
,
596 struct ilo_render_draw_session
*session
)
598 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
600 /* 3DSTATE_GS_SVB_INDEX */
602 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
603 gen6_wa_pre_non_pipelined(r
);
605 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
606 0, 0, r
->state
.so_max_vertices
,
609 if (r
->hw_ctx_changed
) {
613 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
615 * "If a buffer is not enabled then the SVBI must be set to 0x0
616 * in order to not cause overflow in that SVBI."
618 * "If a buffer is not enabled then the MaxSVBI must be set to
619 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
621 for (i
= 1; i
< 4; i
++) {
622 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
623 i
, 0, 0xffffffff, false);
630 gen6_draw_clip(struct ilo_render
*r
,
631 const struct ilo_state_vector
*vec
,
632 struct ilo_render_draw_session
*session
)
635 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_CLIP
)
636 gen6_3DSTATE_CLIP(r
->builder
, &vec
->rasterizer
->rs
);
640 gen6_draw_sf(struct ilo_render
*r
,
641 const struct ilo_state_vector
*vec
,
642 struct ilo_render_draw_session
*session
)
645 if ((session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SF
) ||
646 DIRTY(RASTERIZER
) || DIRTY(FS
)) {
647 gen6_3DSTATE_SF(r
->builder
, &vec
->rasterizer
->rs
,
648 vec
->rasterizer
->state
.sprite_coord_mode
, vec
->fs
);
653 gen6_draw_sf_rect(struct ilo_render
*r
,
654 const struct ilo_state_vector
*vec
,
655 struct ilo_render_draw_session
*session
)
657 /* 3DSTATE_DRAWING_RECTANGLE */
659 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
660 gen6_wa_pre_non_pipelined(r
);
662 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
663 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
668 gen6_draw_wm(struct ilo_render
*r
,
669 const struct ilo_state_vector
*vec
,
670 struct ilo_render_draw_session
*session
)
672 /* 3DSTATE_CONSTANT_PS */
673 if (session
->pcb_fs_changed
) {
674 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
675 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
676 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
681 if (DIRTY(FS
) || DIRTY(BLEND
) ||
682 (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_WM
) ||
683 r
->instruction_bo_changed
) {
684 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
685 gen6_wa_pre_3dstate_wm_max_threads(r
);
687 gen6_3DSTATE_WM(r
->builder
, &vec
->rasterizer
->rs
, vec
->fs
,
688 vec
->blend
->dual_blend
, vec
->blend
->alpha_may_kill
);
693 gen6_draw_wm_multisample(struct ilo_render
*r
,
694 const struct ilo_state_vector
*vec
,
695 struct ilo_render_draw_session
*session
)
697 /* 3DSTATE_MULTISAMPLE */
698 if (DIRTY(FB
) || (session
->rs_delta
.dirty
&
699 ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
)) {
700 const uint32_t *pattern
;
702 pattern
= (vec
->fb
.num_samples
> 1) ?
703 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
705 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
706 gen6_wa_pre_non_pipelined(r
);
707 gen6_wa_pre_3dstate_multisample(r
);
710 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
711 &vec
->rasterizer
->rs
, pattern
, 1);
714 /* 3DSTATE_SAMPLE_MASK */
715 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
)
716 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &vec
->rasterizer
->rs
);
720 gen6_draw_wm_depth(struct ilo_render
*r
,
721 const struct ilo_state_vector
*vec
,
722 struct ilo_render_draw_session
*session
)
724 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
725 if (DIRTY(FB
) || r
->batch_bo_changed
) {
726 const struct ilo_state_zs
*zs
;
727 uint32_t clear_params
;
729 if (vec
->fb
.state
.zsbuf
) {
730 const struct ilo_surface_cso
*surface
=
731 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
732 const struct ilo_texture_slice
*slice
=
733 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
734 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
736 assert(!surface
->is_rt
);
739 clear_params
= slice
->clear_value
;
742 zs
= &vec
->fb
.null_zs
;
746 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
747 gen6_wa_pre_non_pipelined(r
);
748 gen6_wa_pre_depth(r
);
751 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
752 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
753 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
754 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
759 gen6_draw_wm_raster(struct ilo_render
*r
,
760 const struct ilo_state_vector
*vec
,
761 struct ilo_render_draw_session
*session
)
763 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
764 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
765 vec
->rasterizer
->state
.poly_stipple_enable
) {
766 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
767 gen6_wa_pre_non_pipelined(r
);
769 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
772 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
775 /* 3DSTATE_LINE_STIPPLE */
776 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
777 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
778 gen6_wa_pre_non_pipelined(r
);
780 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
781 vec
->rasterizer
->state
.line_stipple_pattern
,
782 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
785 /* 3DSTATE_AA_LINE_PARAMETERS */
786 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
787 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
788 gen6_wa_pre_non_pipelined(r
);
790 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
797 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
798 const struct ilo_state_vector
*vec
,
799 struct ilo_render_draw_session
*session
)
801 ILO_DEV_ASSERT(render
->dev
, 6, 6);
804 * We try to keep the order of the commands match, as closely as possible,
805 * that of the classic i965 driver. It allows us to compare the command
808 gen6_draw_common_select(render
, vec
, session
);
809 gen6_draw_gs_svbi(render
, vec
, session
);
810 gen6_draw_common_sip(render
, vec
, session
);
811 gen6_draw_vf_statistics(render
, vec
, session
);
812 gen6_draw_common_base_address(render
, vec
, session
);
813 gen6_draw_common_pointers_1(render
, vec
, session
);
814 gen6_draw_common_urb(render
, vec
, session
);
815 gen6_draw_common_pointers_2(render
, vec
, session
);
816 gen6_draw_wm_multisample(render
, vec
, session
);
817 gen6_draw_vs(render
, vec
, session
);
818 gen6_draw_gs(render
, vec
, session
);
819 gen6_draw_clip(render
, vec
, session
);
820 gen6_draw_sf(render
, vec
, session
);
821 gen6_draw_wm(render
, vec
, session
);
822 gen6_draw_common_pointers_3(render
, vec
, session
);
823 gen6_draw_wm_depth(render
, vec
, session
);
824 gen6_draw_wm_raster(render
, vec
, session
);
825 gen6_draw_sf_rect(render
, vec
, session
);
826 gen6_draw_vf(render
, vec
, session
);
828 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
832 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
833 const struct ilo_blitter
*blitter
)
835 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
836 gen6_wa_post_3dstate_constant_vs(r
);
838 gen6_wa_pre_3dstate_vs_toggle(r
);
839 gen6_disable_3DSTATE_VS(r
->builder
);
841 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
842 gen6_disable_3DSTATE_GS(r
->builder
);
844 gen6_3DSTATE_CLIP(r
->builder
, &blitter
->fb
.rs
);
845 gen6_3DSTATE_SF(r
->builder
, &blitter
->fb
.rs
, 0, NULL
);
849 gen6_rectlist_wm(struct ilo_render
*r
,
850 const struct ilo_blitter
*blitter
)
852 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
854 gen6_wa_pre_3dstate_wm_max_threads(r
);
855 gen6_3DSTATE_WM(r
->builder
, &blitter
->fb
.rs
, NULL
, false, false);
859 gen6_rectlist_wm_depth(struct ilo_render
*r
,
860 const struct ilo_blitter
*blitter
)
862 gen6_wa_pre_depth(r
);
864 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
865 ILO_BLITTER_USE_FB_STENCIL
))
866 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
868 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
869 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
870 &blitter
->fb
.dst
.u
.zs
);
873 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
874 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
875 &blitter
->fb
.dst
.u
.zs
);
878 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
879 blitter
->depth_clear_value
);
883 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
884 const struct ilo_blitter
*blitter
)
886 const uint32_t *pattern
= (blitter
->fb
.num_samples
> 1) ?
887 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
889 gen6_wa_pre_3dstate_multisample(r
);
891 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &blitter
->fb
.rs
, pattern
, true);
892 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &blitter
->fb
.rs
);
896 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
897 const struct ilo_blitter
*blitter
)
899 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
905 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
906 const struct ilo_blitter
*blitter
,
907 const struct ilo_render_rectlist_session
*session
)
909 ILO_DEV_ASSERT(r
->dev
, 6, 6);
911 gen6_wa_pre_non_pipelined(r
);
913 gen6_rectlist_wm_multisample(r
, blitter
);
915 gen6_state_base_address(r
->builder
, true);
917 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
918 session
->vb_start
, session
->vb_end
,
919 sizeof(blitter
->vertices
[0]));
921 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
923 gen6_3DSTATE_URB(r
->builder
, r
->dev
->urb_size
, 0,
924 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) * 4 * sizeof(float),
927 if (r
->state
.gs
.active
) {
928 gen6_wa_post_3dstate_urb_no_gs(r
);
929 r
->state
.gs
.active
= false;
933 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
934 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
935 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
938 gen6_rectlist_vs_to_sf(r
, blitter
);
939 gen6_rectlist_wm(r
, blitter
);
941 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
942 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
943 0, 0, r
->state
.CC_VIEWPORT
);
946 gen6_rectlist_wm_depth(r
, blitter
);
948 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
949 blitter
->fb
.width
, blitter
->fb
.height
);
951 ilo_render_3dprimitive(r
, &blitter
->draw
, NULL
);
955 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
956 const struct ilo_state_vector
*vec
)
960 ILO_DEV_ASSERT(render
->dev
, 6, 6);
963 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
964 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
965 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
968 GEN6_STATE_BASE_ADDRESS__SIZE
+
969 GEN6_STATE_SIP__SIZE
+
970 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
971 GEN6_PIPELINE_SELECT__SIZE
+
972 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
973 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
974 GEN6_3DSTATE_URB__SIZE
+
975 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
976 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
977 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
978 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
979 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
980 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
981 GEN6_3DSTATE_VS__SIZE
+
982 GEN6_3DSTATE_GS__SIZE
+
983 GEN6_3DSTATE_CLIP__SIZE
+
984 GEN6_3DSTATE_SF__SIZE
+
985 GEN6_3DSTATE_WM__SIZE
+
986 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
987 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
988 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
989 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
990 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
991 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
992 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
993 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
994 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
995 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
996 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
997 GEN6_3DPRIMITIVE__SIZE
;