2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
33 #include "ilo_builder_3d.h"
34 #include "ilo_builder_mi.h"
35 #include "ilo_builder_render.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render_gen.h"
42 * This should be called before PIPE_CONTROL.
45 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
48 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
50 * "Pipe-control with CS-stall bit set must be sent BEFORE the
51 * pipe-control with a post-sync op and no write-cache flushes."
53 * This WA may also be triggered indirectly by the other two WAs on the
56 * "Before any depth stall flush (including those produced by
57 * non-pipelined state commands), software needs to first send a
58 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
60 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
61 * PIPE_CONTROL with any non-zero post-sync-op is required."
63 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
64 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
65 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
66 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
68 ILO_DEV_ASSERT(r
->dev
, 6, 6);
70 if (!direct_wa_cond
&& !indirect_wa_cond
)
73 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
75 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
77 * "1 of the following must also be set (when CS stall is set):
79 * - Depth Cache Flush Enable ([0] of DW1)
80 * - Stall at Pixel Scoreboard ([1] of DW1)
81 * - Depth Stall ([13] of DW1)
82 * - Post-Sync Operation ([13] of DW1)
83 * - Render Target Cache Flush Enable ([12] of DW1)
84 * - Notify Enable ([8] of DW1)"
86 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
88 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
89 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
91 ilo_render_pipe_control(r
, direct_wa
);
94 if (indirect_wa_cond
&&
95 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
96 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
98 ilo_render_pipe_control(r
, indirect_wa
);
103 * This should be called before any non-pipelined state command.
106 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
108 ILO_DEV_ASSERT(r
->dev
, 6, 6);
110 /* non-pipelined state commands produce depth stall */
111 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
115 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
118 * According to upload_vs_state() of the classic driver, we need to emit a
119 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
120 * being buffered by VS FF, to the point that the FF dies.
122 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
123 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
124 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
126 gen6_wa_pre_pipe_control(r
, dw1
);
128 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
129 ilo_render_pipe_control(r
, dw1
);
133 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
136 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
138 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
139 * field set (DW1 Bit 1), must be issued prior to any change to the
140 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
142 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
144 ILO_DEV_ASSERT(r
->dev
, 6, 6);
146 gen6_wa_pre_pipe_control(r
, dw1
);
148 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
149 ilo_render_pipe_control(r
, dw1
);
153 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
156 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
158 * "Driver must guarentee that all the caches in the depth pipe are
159 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
160 * requires driver to send a PIPE_CONTROL with a CS stall along with a
161 * Depth Flush prior to this command."
163 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
164 GEN6_PIPE_CONTROL_CS_STALL
;
166 ILO_DEV_ASSERT(r
->dev
, 6, 6);
168 gen6_wa_pre_pipe_control(r
, dw1
);
170 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
171 ilo_render_pipe_control(r
, dw1
);
175 gen6_wa_pre_depth(struct ilo_render
*r
)
177 ILO_DEV_ASSERT(r
->dev
, 6, 6);
180 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
182 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
183 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
184 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
185 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
186 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
187 * Depth Flush Bit set, followed by another pipelined depth stall
188 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
189 * guarantee that the pipeline from WM onwards is already flushed
190 * (e.g., via a preceding MI_FLUSH)."
192 * According to the classic driver, it also applies for GEN6.
194 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
195 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
197 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
198 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
199 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
202 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
205 gen6_draw_common_select(struct ilo_render
*r
,
206 const struct ilo_state_vector
*vec
,
207 struct ilo_render_draw_session
*session
)
209 /* PIPELINE_SELECT */
210 if (r
->hw_ctx_changed
) {
211 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
212 gen6_wa_pre_non_pipelined(r
);
214 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
219 gen6_draw_common_sip(struct ilo_render
*r
,
220 const struct ilo_state_vector
*vec
,
221 struct ilo_render_draw_session
*session
)
224 if (r
->hw_ctx_changed
) {
225 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
226 gen6_wa_pre_non_pipelined(r
);
228 gen6_STATE_SIP(r
->builder
, 0);
233 gen6_draw_common_base_address(struct ilo_render
*r
,
234 const struct ilo_state_vector
*vec
,
235 struct ilo_render_draw_session
*session
)
237 /* STATE_BASE_ADDRESS */
238 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
239 r
->batch_bo_changed
) {
240 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
241 gen6_wa_pre_non_pipelined(r
);
243 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
244 gen8_state_base_address(r
->builder
, r
->hw_ctx_changed
);
246 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
249 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
251 * "The following commands must be reissued following any change to
252 * the base addresses:
254 * * 3DSTATE_BINDING_TABLE_POINTERS
255 * * 3DSTATE_SAMPLER_STATE_POINTERS
256 * * 3DSTATE_VIEWPORT_STATE_POINTERS
257 * * 3DSTATE_CC_POINTERS
258 * * MEDIA_STATE_POINTERS"
260 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
261 * reasonable to also reissue the command. Same to PCB.
263 session
->viewport_changed
= true;
265 session
->scissor_changed
= true;
267 session
->blend_changed
= true;
268 session
->dsa_changed
= true;
269 session
->cc_changed
= true;
271 session
->sampler_vs_changed
= true;
272 session
->sampler_gs_changed
= true;
273 session
->sampler_fs_changed
= true;
275 session
->pcb_vs_changed
= true;
276 session
->pcb_gs_changed
= true;
277 session
->pcb_fs_changed
= true;
279 session
->binding_table_vs_changed
= true;
280 session
->binding_table_gs_changed
= true;
281 session
->binding_table_fs_changed
= true;
286 gen6_draw_common_urb(struct ilo_render
*r
,
287 const struct ilo_state_vector
*vec
,
288 struct ilo_render_draw_session
*session
)
291 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
292 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
293 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
294 int vs_entry_size
, gs_entry_size
;
295 int vs_total_size
, gs_total_size
;
297 vs_entry_size
= (vec
->vs
) ?
298 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
301 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
302 * share VUE handles. The VUE allocation size must be large enough to
303 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
305 * I am not sure if the PRM explicitly states that VF and VS share VUE
306 * handles. But here is a citation that implies so:
308 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
310 * "Once a FF stage that spawn threads has sufficient input to
311 * initiate a thread, it must guarantee that it is safe to request
312 * the thread initiation. For all these FF stages, this check is
315 * - The availability of output URB entries:
316 * - VS: As the input URB entries are overwritten with the
317 * VS-generated output data, output URB availability isn't a
320 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
321 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
323 gs_entry_size
= (vec
->gs
) ?
324 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
325 (gs_active
) ? vs_entry_size
: 0;
328 vs_entry_size
*= sizeof(float) * 4;
329 gs_entry_size
*= sizeof(float) * 4;
330 vs_total_size
= r
->dev
->urb_size
;
334 gs_total_size
= vs_total_size
;
340 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
341 vs_entry_size
, gs_entry_size
);
344 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
346 * "Because of a urb corruption caused by allocating a previous
347 * gsunit's urb entry to vsunit software is required to send a
348 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
349 * size == 0) plus a dummy DRAW call before any case where VS will
350 * be taking over GS URB space."
352 if (r
->state
.gs
.active
&& !gs_active
)
353 ilo_render_emit_flush(r
);
355 r
->state
.gs
.active
= gs_active
;
360 gen6_draw_common_pointers_1(struct ilo_render
*r
,
361 const struct ilo_state_vector
*vec
,
362 struct ilo_render_draw_session
*session
)
364 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
365 if (session
->viewport_changed
) {
366 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
367 r
->state
.CLIP_VIEWPORT
,
368 r
->state
.SF_VIEWPORT
,
369 r
->state
.CC_VIEWPORT
);
374 gen6_draw_common_pointers_2(struct ilo_render
*r
,
375 const struct ilo_state_vector
*vec
,
376 struct ilo_render_draw_session
*session
)
378 /* 3DSTATE_CC_STATE_POINTERS */
379 if (session
->blend_changed
||
380 session
->dsa_changed
||
381 session
->cc_changed
) {
382 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
383 r
->state
.BLEND_STATE
,
384 r
->state
.DEPTH_STENCIL_STATE
,
385 r
->state
.COLOR_CALC_STATE
);
388 /* 3DSTATE_SAMPLER_STATE_POINTERS */
389 if (session
->sampler_vs_changed
||
390 session
->sampler_gs_changed
||
391 session
->sampler_fs_changed
) {
392 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
393 r
->state
.vs
.SAMPLER_STATE
,
395 r
->state
.wm
.SAMPLER_STATE
);
400 gen6_draw_common_pointers_3(struct ilo_render
*r
,
401 const struct ilo_state_vector
*vec
,
402 struct ilo_render_draw_session
*session
)
404 /* 3DSTATE_SCISSOR_STATE_POINTERS */
405 if (session
->scissor_changed
) {
406 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
407 r
->state
.SCISSOR_RECT
);
410 /* 3DSTATE_BINDING_TABLE_POINTERS */
411 if (session
->binding_table_vs_changed
||
412 session
->binding_table_gs_changed
||
413 session
->binding_table_fs_changed
) {
414 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
415 r
->state
.vs
.BINDING_TABLE_STATE
,
416 r
->state
.gs
.BINDING_TABLE_STATE
,
417 r
->state
.wm
.BINDING_TABLE_STATE
);
422 gen6_draw_vf(struct ilo_render
*r
,
423 const struct ilo_state_vector
*vec
,
424 struct ilo_render_draw_session
*session
)
426 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
427 /* 3DSTATE_INDEX_BUFFER */
428 if (DIRTY(IB
) || r
->batch_bo_changed
) {
429 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
434 if (session
->primitive_restart_changed
) {
435 gen75_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
436 vec
->draw
->restart_index
);
440 /* 3DSTATE_INDEX_BUFFER */
441 if (DIRTY(IB
) || session
->primitive_restart_changed
||
442 r
->batch_bo_changed
) {
443 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
444 &vec
->ib
, vec
->draw
->primitive_restart
);
448 /* 3DSTATE_VERTEX_BUFFERS */
449 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
450 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
452 /* 3DSTATE_VERTEX_ELEMENTS */
454 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, vec
->ve
);
458 gen6_draw_vf_statistics(struct ilo_render
*r
,
459 const struct ilo_state_vector
*vec
,
460 struct ilo_render_draw_session
*session
)
462 /* 3DSTATE_VF_STATISTICS */
463 if (r
->hw_ctx_changed
)
464 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
468 gen6_draw_vs(struct ilo_render
*r
,
469 const struct ilo_state_vector
*vec
,
470 struct ilo_render_draw_session
*session
)
472 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
473 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
476 * the classic i965 does this in upload_vs_state(), citing a spec that I
479 if (emit_3dstate_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
480 gen6_wa_pre_non_pipelined(r
);
482 /* 3DSTATE_CONSTANT_VS */
483 if (emit_3dstate_constant_vs
) {
484 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
485 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
486 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
492 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
494 if (emit_3dstate_constant_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
495 gen6_wa_post_3dstate_constant_vs(r
);
499 gen6_draw_gs(struct ilo_render
*r
,
500 const struct ilo_state_vector
*vec
,
501 struct ilo_render_draw_session
*session
)
503 /* 3DSTATE_CONSTANT_GS */
504 if (session
->pcb_gs_changed
)
505 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
508 if (DIRTY(GS
) || DIRTY(VS
) ||
509 session
->prim_changed
|| r
->instruction_bo_changed
) {
511 gen6_3DSTATE_GS(r
->builder
, vec
->gs
);
512 } else if (vec
->vs
&&
513 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)) {
514 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
515 gen6_so_3DSTATE_GS(r
->builder
, vec
->vs
, verts_per_prim
);
517 gen6_disable_3DSTATE_GS(r
->builder
);
523 gen6_draw_update_max_svbi(struct ilo_render
*r
,
524 const struct ilo_state_vector
*vec
,
525 struct ilo_render_draw_session
*session
)
527 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
528 const struct pipe_stream_output_info
*so_info
=
529 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
530 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
531 unsigned max_svbi
= 0xffffffff;
534 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
535 const int output_buffer
= so_info
->output
[i
].output_buffer
;
536 const struct pipe_stream_output_target
*so
=
537 vec
->so
.states
[output_buffer
];
538 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
539 const int elem_size
= so_info
->output
[i
].num_components
* 4;
547 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
549 count
= buf_size
/ struct_size
;
550 if (buf_size
% struct_size
>= elem_size
)
553 if (count
< max_svbi
)
557 if (r
->state
.so_max_vertices
!= max_svbi
) {
558 r
->state
.so_max_vertices
= max_svbi
;
567 gen6_draw_gs_svbi(struct ilo_render
*r
,
568 const struct ilo_state_vector
*vec
,
569 struct ilo_render_draw_session
*session
)
571 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
573 /* 3DSTATE_GS_SVB_INDEX */
575 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
576 gen6_wa_pre_non_pipelined(r
);
578 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
579 0, 0, r
->state
.so_max_vertices
,
582 if (r
->hw_ctx_changed
) {
586 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
588 * "If a buffer is not enabled then the SVBI must be set to 0x0
589 * in order to not cause overflow in that SVBI."
591 * "If a buffer is not enabled then the MaxSVBI must be set to
592 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
594 for (i
= 1; i
< 4; i
++) {
595 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
596 i
, 0, 0xffffffff, false);
603 gen6_draw_clip(struct ilo_render
*r
,
604 const struct ilo_state_vector
*vec
,
605 struct ilo_render_draw_session
*session
)
608 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
609 bool enable_guardband
= true;
613 * Gen8+ has viewport extent test. Guard band test can be enabled on
614 * prior Gens only when the viewport is larger than the framebuffer,
615 * unless we emulate viewport extent test on them.
617 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8)) {
618 for (i
= 0; i
< vec
->viewport
.count
; i
++) {
619 const struct ilo_viewport_cso
*vp
= &vec
->viewport
.cso
[i
];
621 if (vp
->min_x
> 0.0f
|| vp
->max_x
< vec
->fb
.state
.width
||
622 vp
->min_y
> 0.0f
|| vp
->max_y
< vec
->fb
.state
.height
) {
623 enable_guardband
= false;
629 gen6_3DSTATE_CLIP(r
->builder
, vec
->rasterizer
,
630 vec
->fs
, enable_guardband
, 1);
635 gen6_draw_sf(struct ilo_render
*r
,
636 const struct ilo_state_vector
*vec
,
637 struct ilo_render_draw_session
*session
)
640 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(FB
)) {
641 gen6_3DSTATE_SF(r
->builder
, vec
->rasterizer
, vec
->fs
,
642 vec
->fb
.num_samples
);
647 gen6_draw_sf_rect(struct ilo_render
*r
,
648 const struct ilo_state_vector
*vec
,
649 struct ilo_render_draw_session
*session
)
651 /* 3DSTATE_DRAWING_RECTANGLE */
653 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
654 gen6_wa_pre_non_pipelined(r
);
656 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
657 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
662 gen6_draw_wm(struct ilo_render
*r
,
663 const struct ilo_state_vector
*vec
,
664 struct ilo_render_draw_session
*session
)
666 /* 3DSTATE_CONSTANT_PS */
667 if (session
->pcb_fs_changed
) {
668 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
669 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
670 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
675 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
676 DIRTY(RASTERIZER
) || r
->instruction_bo_changed
) {
677 const bool dual_blend
= vec
->blend
->dual_blend
;
678 const bool cc_may_kill
= (vec
->dsa
->dw_blend_alpha
||
679 vec
->blend
->alpha_to_coverage
);
681 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
682 gen6_wa_pre_3dstate_wm_max_threads(r
);
684 gen6_3DSTATE_WM(r
->builder
, vec
->fs
,
685 vec
->rasterizer
, dual_blend
, cc_may_kill
);
690 gen6_draw_wm_multisample(struct ilo_render
*r
,
691 const struct ilo_state_vector
*vec
,
692 struct ilo_render_draw_session
*session
)
694 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
695 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
696 const uint32_t *pattern
;
698 pattern
= (vec
->fb
.num_samples
> 1) ?
699 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
701 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
702 gen6_wa_pre_non_pipelined(r
);
703 gen6_wa_pre_3dstate_multisample(r
);
706 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
707 vec
->fb
.num_samples
, pattern
,
708 vec
->rasterizer
->state
.half_pixel_center
);
710 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
711 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1);
716 gen6_draw_wm_depth(struct ilo_render
*r
,
717 const struct ilo_state_vector
*vec
,
718 struct ilo_render_draw_session
*session
)
720 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
721 if (DIRTY(FB
) || r
->batch_bo_changed
) {
722 const struct ilo_zs_surface
*zs
;
723 uint32_t clear_params
;
725 if (vec
->fb
.state
.zsbuf
) {
726 const struct ilo_surface_cso
*surface
=
727 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
728 const struct ilo_texture_slice
*slice
=
729 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
730 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
732 assert(!surface
->is_rt
);
735 clear_params
= slice
->clear_value
;
738 zs
= &vec
->fb
.null_zs
;
742 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
743 gen6_wa_pre_non_pipelined(r
);
744 gen6_wa_pre_depth(r
);
747 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
, false);
748 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
749 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
750 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
755 gen6_draw_wm_raster(struct ilo_render
*r
,
756 const struct ilo_state_vector
*vec
,
757 struct ilo_render_draw_session
*session
)
759 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
760 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
761 vec
->rasterizer
->state
.poly_stipple_enable
) {
762 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
763 gen6_wa_pre_non_pipelined(r
);
765 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
768 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
771 /* 3DSTATE_LINE_STIPPLE */
772 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
773 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
774 gen6_wa_pre_non_pipelined(r
);
776 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
777 vec
->rasterizer
->state
.line_stipple_pattern
,
778 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
781 /* 3DSTATE_AA_LINE_PARAMETERS */
782 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
783 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
784 gen6_wa_pre_non_pipelined(r
);
786 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
793 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
794 const struct ilo_state_vector
*vec
,
795 struct ilo_render_draw_session
*session
)
797 ILO_DEV_ASSERT(render
->dev
, 6, 6);
800 * We try to keep the order of the commands match, as closely as possible,
801 * that of the classic i965 driver. It allows us to compare the command
804 gen6_draw_common_select(render
, vec
, session
);
805 gen6_draw_gs_svbi(render
, vec
, session
);
806 gen6_draw_common_sip(render
, vec
, session
);
807 gen6_draw_vf_statistics(render
, vec
, session
);
808 gen6_draw_common_base_address(render
, vec
, session
);
809 gen6_draw_common_pointers_1(render
, vec
, session
);
810 gen6_draw_common_urb(render
, vec
, session
);
811 gen6_draw_common_pointers_2(render
, vec
, session
);
812 gen6_draw_wm_multisample(render
, vec
, session
);
813 gen6_draw_vs(render
, vec
, session
);
814 gen6_draw_gs(render
, vec
, session
);
815 gen6_draw_clip(render
, vec
, session
);
816 gen6_draw_sf(render
, vec
, session
);
817 gen6_draw_wm(render
, vec
, session
);
818 gen6_draw_common_pointers_3(render
, vec
, session
);
819 gen6_draw_wm_depth(render
, vec
, session
);
820 gen6_draw_wm_raster(render
, vec
, session
);
821 gen6_draw_sf_rect(render
, vec
, session
);
822 gen6_draw_vf(render
, vec
, session
);
824 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
828 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
829 const struct ilo_blitter
*blitter
)
831 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
832 gen6_disable_3DSTATE_VS(r
->builder
);
834 gen6_wa_post_3dstate_constant_vs(r
);
836 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
837 gen6_disable_3DSTATE_GS(r
->builder
);
839 gen6_disable_3DSTATE_CLIP(r
->builder
);
840 gen6_3DSTATE_SF(r
->builder
, NULL
, NULL
, blitter
->fb
.num_samples
);
844 gen6_rectlist_wm(struct ilo_render
*r
,
845 const struct ilo_blitter
*blitter
)
849 switch (blitter
->op
) {
850 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
851 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
853 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
854 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
856 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
857 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
864 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
866 gen6_wa_pre_3dstate_wm_max_threads(r
);
867 gen6_hiz_3DSTATE_WM(r
->builder
, hiz_op
);
871 gen6_rectlist_wm_depth(struct ilo_render
*r
,
872 const struct ilo_blitter
*blitter
)
874 gen6_wa_pre_depth(r
);
876 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
877 ILO_BLITTER_USE_FB_STENCIL
)) {
878 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
879 &blitter
->fb
.dst
.u
.zs
, true);
882 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
883 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
884 &blitter
->fb
.dst
.u
.zs
);
887 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
888 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
889 &blitter
->fb
.dst
.u
.zs
);
892 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
893 blitter
->depth_clear_value
);
897 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
898 const struct ilo_blitter
*blitter
)
900 const uint32_t *pattern
= (blitter
->fb
.num_samples
> 1) ?
901 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
903 gen6_wa_pre_3dstate_multisample(r
);
905 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
908 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
909 (1 << blitter
->fb
.num_samples
) - 1);
913 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
914 const struct ilo_blitter
*blitter
)
916 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
922 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
923 const struct ilo_blitter
*blitter
,
924 const struct ilo_render_rectlist_session
*session
)
926 ILO_DEV_ASSERT(r
->dev
, 6, 6);
928 gen6_wa_pre_non_pipelined(r
);
930 gen6_rectlist_wm_multisample(r
, blitter
);
932 gen6_state_base_address(r
->builder
, true);
934 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
935 session
->vb_start
, session
->vb_end
,
936 sizeof(blitter
->vertices
[0]));
938 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
940 gen6_3DSTATE_URB(r
->builder
, r
->dev
->urb_size
, 0,
941 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) * 4 * sizeof(float),
944 /* 3DSTATE_URB workaround */
945 if (r
->state
.gs
.active
) {
946 ilo_render_emit_flush(r
);
947 r
->state
.gs
.active
= false;
951 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
952 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
953 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
956 gen6_rectlist_vs_to_sf(r
, blitter
);
957 gen6_rectlist_wm(r
, blitter
);
959 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
960 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
961 0, 0, r
->state
.CC_VIEWPORT
);
964 gen6_rectlist_wm_depth(r
, blitter
);
966 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
967 blitter
->fb
.width
, blitter
->fb
.height
);
969 ilo_render_3dprimitive(r
, &blitter
->draw
, NULL
);
973 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
974 const struct ilo_state_vector
*vec
)
978 ILO_DEV_ASSERT(render
->dev
, 6, 6);
981 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
982 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
983 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
986 GEN6_STATE_BASE_ADDRESS__SIZE
+
987 GEN6_STATE_SIP__SIZE
+
988 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
989 GEN6_PIPELINE_SELECT__SIZE
+
990 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
991 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
992 GEN6_3DSTATE_URB__SIZE
+
993 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
994 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
995 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
996 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
997 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
998 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
999 GEN6_3DSTATE_VS__SIZE
+
1000 GEN6_3DSTATE_GS__SIZE
+
1001 GEN6_3DSTATE_CLIP__SIZE
+
1002 GEN6_3DSTATE_SF__SIZE
+
1003 GEN6_3DSTATE_WM__SIZE
+
1004 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1005 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1006 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1007 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1008 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1009 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1010 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1011 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1012 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1013 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1014 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1015 GEN6_3DPRIMITIVE__SIZE
;