2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_render.h"
32 #include "ilo_blitter.h"
33 #include "ilo_shader.h"
34 #include "ilo_state.h"
35 #include "ilo_render_gen.h"
38 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render
*r
)
41 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
43 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
44 * in the ring after this instruction
45 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
47 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
49 ILO_DEV_ASSERT(r
->dev
, 7, 7);
51 r
->state
.deferred_pipe_control_dw1
|= dw1
;
55 gen7_wa_pre_vs(struct ilo_render
*r
)
58 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
60 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
61 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
62 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
63 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
64 * needs to be sent before any combination of VS associated 3DSTATE."
66 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
67 GEN6_PIPE_CONTROL_WRITE_IMM
;
69 ILO_DEV_ASSERT(r
->dev
, 7, 7);
71 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
72 ilo_render_pipe_control(r
, dw1
);
76 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render
*r
)
79 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
81 * "Due to an HW issue driver needs to send a pipe control with stall
82 * when ever there is state change in depth bias related state (in
85 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
87 ILO_DEV_ASSERT(r
->dev
, 7, 7);
89 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
90 ilo_render_pipe_control(r
, dw1
);
94 gen7_wa_pre_3dstate_multisample(struct ilo_render
*r
)
97 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
99 * "Driver must ierarchi that all the caches in the depth pipe are
100 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
101 * requires driver to send a PIPE_CONTROL with a CS stall along with a
102 * Depth Flush prior to this command.
104 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
105 GEN6_PIPE_CONTROL_CS_STALL
;
107 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
109 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
110 ilo_render_pipe_control(r
, dw1
);
114 gen7_wa_pre_depth(struct ilo_render
*r
)
116 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
118 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
120 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
122 * "Driver must send a least one PIPE_CONTROL command with CS Stall
123 * and a post sync operation prior to the group of depth
124 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
125 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
127 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
|
128 GEN6_PIPE_CONTROL_WRITE_IMM
;
130 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
131 ilo_render_pipe_control(r
, dw1
);
135 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
137 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
138 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
139 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
140 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
141 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
142 * Depth Flush Bit set, followed by another pipelined depth stall
143 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
144 * guarantee that the pipeline from WM onwards is already flushed
145 * (e.g., via a preceding MI_FLUSH)."
147 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
148 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
149 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
153 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render
*r
)
156 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
158 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
159 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
160 * Pixel Scoreboard set is required to be issued."
162 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
164 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
166 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
167 ilo_render_pipe_control(r
, dw1
);
171 gen7_wa_post_ps_and_later(struct ilo_render
*r
)
174 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
176 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
177 * Enable bit set after all the following states are programmed:
180 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
181 * - 3DSTATE_CONSTANT_PS
182 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
183 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
184 * - 3DSTATE_CC_STATE_POINTERS
185 * - 3DSTATE_BLEND_STATE_POINTERS
186 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
188 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
;
190 ILO_DEV_ASSERT(r
->dev
, 7, 7);
192 r
->state
.deferred_pipe_control_dw1
|= dw1
;
195 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
198 gen7_draw_common_urb(struct ilo_render
*r
,
199 const struct ilo_state_vector
*vec
,
200 struct ilo_render_draw_session
*session
)
202 /* 3DSTATE_URB_{VS,GS,HS,DS} */
203 if (session
->urb_delta
.dirty
& (ILO_STATE_URB_3DSTATE_URB_VS
|
204 ILO_STATE_URB_3DSTATE_URB_HS
|
205 ILO_STATE_URB_3DSTATE_URB_DS
|
206 ILO_STATE_URB_3DSTATE_URB_GS
)) {
207 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
210 gen7_3DSTATE_URB_VS(r
->builder
, &vec
->urb
);
211 gen7_3DSTATE_URB_GS(r
->builder
, &vec
->urb
);
212 gen7_3DSTATE_URB_HS(r
->builder
, &vec
->urb
);
213 gen7_3DSTATE_URB_DS(r
->builder
, &vec
->urb
);
218 gen7_draw_common_pcb_alloc(struct ilo_render
*r
,
219 const struct ilo_state_vector
*vec
,
220 struct ilo_render_draw_session
*session
)
222 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
223 if (session
->urb_delta
.dirty
&
224 (ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS
|
225 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS
|
226 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS
|
227 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS
|
228 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS
)) {
229 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, &vec
->urb
);
230 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS(r
->builder
, &vec
->urb
);
231 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, &vec
->urb
);
233 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
234 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
239 gen7_draw_common_pointers_1(struct ilo_render
*r
,
240 const struct ilo_state_vector
*vec
,
241 struct ilo_render_draw_session
*session
)
243 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
244 if (session
->viewport_changed
) {
245 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
246 r
->state
.CC_VIEWPORT
);
248 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r
->builder
,
249 r
->state
.SF_CLIP_VIEWPORT
);
254 gen7_draw_common_pointers_2(struct ilo_render
*r
,
255 const struct ilo_state_vector
*vec
,
256 struct ilo_render_draw_session
*session
)
258 /* 3DSTATE_BLEND_STATE_POINTERS */
259 if (session
->blend_changed
) {
260 gen7_3DSTATE_BLEND_STATE_POINTERS(r
->builder
,
261 r
->state
.BLEND_STATE
);
264 /* 3DSTATE_CC_STATE_POINTERS */
265 if (session
->cc_changed
) {
266 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
267 r
->state
.COLOR_CALC_STATE
);
270 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
271 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8) && session
->dsa_changed
) {
272 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
273 r
->state
.DEPTH_STENCIL_STATE
);
278 gen7_draw_vs(struct ilo_render
*r
,
279 const struct ilo_state_vector
*vec
,
280 struct ilo_render_draw_session
*session
)
282 const bool emit_3dstate_binding_table
= session
->binding_table_vs_changed
;
283 const bool emit_3dstate_sampler_state
= session
->sampler_vs_changed
;
284 /* see gen6_draw_vs() */
285 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
286 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
288 /* emit depth stall before any of the VS commands */
289 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
290 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
291 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
295 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
296 if (emit_3dstate_binding_table
) {
297 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r
->builder
,
298 r
->state
.vs
.BINDING_TABLE_STATE
);
301 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
302 if (emit_3dstate_sampler_state
) {
303 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r
->builder
,
304 r
->state
.vs
.SAMPLER_STATE
);
307 /* 3DSTATE_CONSTANT_VS */
308 if (emit_3dstate_constant_vs
) {
309 gen7_3DSTATE_CONSTANT_VS(r
->builder
,
310 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
311 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
316 if (emit_3dstate_vs
) {
317 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->vs
);
318 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->vs
);
320 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
321 gen8_3DSTATE_VS(r
->builder
, &cso
->vs
, kernel_offset
);
323 gen6_3DSTATE_VS(r
->builder
, &cso
->vs
, kernel_offset
);
328 gen7_draw_hs(struct ilo_render
*r
,
329 const struct ilo_state_vector
*vec
,
330 struct ilo_render_draw_session
*session
)
332 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
333 if (r
->hw_ctx_changed
) {
334 const struct ilo_state_hs
*hs
= &vec
->disabled_hs
;
335 const uint32_t kernel_offset
= 0;
337 gen7_3DSTATE_CONSTANT_HS(r
->builder
, 0, 0, 0);
339 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
340 gen8_3DSTATE_HS(r
->builder
, hs
, kernel_offset
);
342 gen7_3DSTATE_HS(r
->builder
, hs
, kernel_offset
);
345 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
346 if (r
->hw_ctx_changed
)
347 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r
->builder
, 0);
351 gen7_draw_te(struct ilo_render
*r
,
352 const struct ilo_state_vector
*vec
,
353 struct ilo_render_draw_session
*session
)
356 if (r
->hw_ctx_changed
) {
357 const struct ilo_state_ds
*ds
= &vec
->disabled_ds
;
358 gen7_3DSTATE_TE(r
->builder
, ds
);
363 gen7_draw_ds(struct ilo_render
*r
,
364 const struct ilo_state_vector
*vec
,
365 struct ilo_render_draw_session
*session
)
367 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
368 if (r
->hw_ctx_changed
) {
369 const struct ilo_state_ds
*ds
= &vec
->disabled_ds
;
370 const uint32_t kernel_offset
= 0;
372 gen7_3DSTATE_CONSTANT_DS(r
->builder
, 0, 0, 0);
374 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
375 gen8_3DSTATE_DS(r
->builder
, ds
, kernel_offset
);
377 gen7_3DSTATE_DS(r
->builder
, ds
, kernel_offset
);
380 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
381 if (r
->hw_ctx_changed
)
382 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r
->builder
, 0);
387 gen7_draw_gs(struct ilo_render
*r
,
388 const struct ilo_state_vector
*vec
,
389 struct ilo_render_draw_session
*session
)
391 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
392 if (r
->hw_ctx_changed
) {
393 const struct ilo_state_gs
*gs
= &vec
->disabled_gs
;
394 const uint32_t kernel_offset
= 0;
396 gen7_3DSTATE_CONSTANT_GS(r
->builder
, 0, 0, 0);
398 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
399 gen8_3DSTATE_GS(r
->builder
, gs
, kernel_offset
);
401 gen7_3DSTATE_GS(r
->builder
, gs
, kernel_offset
);
404 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
405 if (session
->binding_table_gs_changed
) {
406 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r
->builder
,
407 r
->state
.gs
.BINDING_TABLE_STATE
);
412 gen7_draw_sol(struct ilo_render
*r
,
413 const struct ilo_state_vector
*vec
,
414 struct ilo_render_draw_session
*session
)
416 const struct ilo_state_sol
*sol
;
417 const struct ilo_shader_state
*shader
;
418 bool dirty_sh
= false;
422 dirty_sh
= DIRTY(GS
);
426 dirty_sh
= DIRTY(VS
);
429 sol
= ilo_shader_get_kernel_sol(shader
);
431 /* 3DSTATE_SO_BUFFER */
432 if ((DIRTY(SO
) || dirty_sh
|| r
->batch_bo_changed
) &&
436 for (i
= 0; i
< ILO_STATE_SOL_MAX_BUFFER_COUNT
; i
++) {
437 const struct pipe_stream_output_target
*target
=
438 (i
< vec
->so
.count
&& vec
->so
.states
[i
]) ?
439 vec
->so
.states
[i
] : NULL
;
440 const struct ilo_state_sol_buffer
*sb
= (target
) ?
441 &((const struct ilo_stream_output_target
*) target
)->sb
:
444 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
445 gen8_3DSTATE_SO_BUFFER(r
->builder
, sol
, sb
, i
);
447 gen7_3DSTATE_SO_BUFFER(r
->builder
, sol
, sb
, i
);
451 /* 3DSTATE_SO_DECL_LIST */
452 if (dirty_sh
&& vec
->so
.enabled
)
453 gen7_3DSTATE_SO_DECL_LIST(r
->builder
, sol
);
456 * From the Ivy Bridge PRM, volume 2 part 1, page 196-197:
458 * "Anytime the SOL unit MMIO registers or non-pipeline state are
459 * written, the SOL unit needs to receive a pipeline state update with
460 * SOL unit dirty state for information programmed in MMIO/NP to get
461 * loaded into the SOL unit.
463 * The SOL unit incorrectly double buffers MMIO/NP registers and only
464 * moves them into the design for usage when control topology is
465 * received with the SOL unit dirty state.
467 * If the state does not change, need to resend the same state.
469 * Because of corruption, software must flush the whole fixed function
470 * pipeline when 3DSTATE_STREAMOUT changes state."
472 * The first and fourth paragraphs are gone on Gen7.5+.
475 /* 3DSTATE_STREAMOUT */
476 gen7_3DSTATE_STREAMOUT(r
->builder
, sol
);
480 gen7_draw_sf(struct ilo_render
*r
,
481 const struct ilo_state_vector
*vec
,
482 struct ilo_render_draw_session
*session
)
486 const struct ilo_state_sbe
*sbe
= ilo_shader_get_kernel_sbe(vec
->fs
);
487 gen7_3DSTATE_SBE(r
->builder
, sbe
);
491 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SF
) {
492 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
493 gen7_wa_pre_3dstate_sf_depth_bias(r
);
495 gen7_3DSTATE_SF(r
->builder
, &vec
->rasterizer
->rs
);
500 gen7_draw_wm(struct ilo_render
*r
,
501 const struct ilo_state_vector
*vec
,
502 struct ilo_render_draw_session
*session
)
504 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->fs
);
505 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->fs
);
508 if (DIRTY(FS
) || (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_WM
))
509 gen7_3DSTATE_WM(r
->builder
, &vec
->rasterizer
->rs
, &cso
->ps
);
511 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
512 if (session
->binding_table_fs_changed
) {
513 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
514 r
->state
.wm
.BINDING_TABLE_STATE
);
517 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
518 if (session
->sampler_fs_changed
) {
519 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
520 r
->state
.wm
.SAMPLER_STATE
);
523 /* 3DSTATE_CONSTANT_PS */
524 if (session
->pcb_fs_changed
) {
525 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
526 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
527 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
532 if (DIRTY(FS
) || r
->instruction_bo_changed
) {
533 if (r
->hw_ctx_changed
)
534 gen7_wa_pre_3dstate_ps_max_threads(r
);
536 gen7_3DSTATE_PS(r
->builder
, &cso
->ps
, kernel_offset
);
539 /* 3DSTATE_SCISSOR_STATE_POINTERS */
540 if (session
->scissor_changed
) {
541 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
542 r
->state
.SCISSOR_RECT
);
546 const bool emit_3dstate_ps
= (DIRTY(FS
) || DIRTY(BLEND
));
547 const bool emit_3dstate_depth_buffer
=
548 (DIRTY(FB
) || DIRTY(DSA
) || r
->state_bo_changed
);
550 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
551 /* XXX what is the best way to know if this workaround is needed? */
552 if (emit_3dstate_ps
||
553 session
->pcb_fs_changed
||
554 session
->viewport_changed
||
555 session
->binding_table_fs_changed
||
556 session
->sampler_fs_changed
||
557 session
->cc_changed
||
558 session
->blend_changed
||
559 session
->dsa_changed
)
560 gen7_wa_post_ps_and_later(r
);
563 if (emit_3dstate_depth_buffer
)
564 gen7_wa_pre_depth(r
);
567 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
568 if (DIRTY(FB
) || r
->batch_bo_changed
) {
569 const struct ilo_state_zs
*zs
;
570 uint32_t clear_params
;
572 if (vec
->fb
.state
.zsbuf
) {
573 const struct ilo_surface_cso
*surface
=
574 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
575 const struct ilo_texture_slice
*slice
=
576 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
577 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
579 assert(!surface
->is_rt
);
581 clear_params
= slice
->clear_value
;
584 zs
= &vec
->fb
.null_zs
;
588 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
589 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
590 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
591 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
596 gen7_draw_wm_multisample(struct ilo_render
*r
,
597 const struct ilo_state_vector
*vec
,
598 struct ilo_render_draw_session
*session
)
600 /* 3DSTATE_MULTISAMPLE */
601 if (DIRTY(FB
) || (session
->rs_delta
.dirty
&
602 ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
)) {
603 const uint8_t sample_count
= (vec
->fb
.num_samples
> 4) ? 8 :
604 (vec
->fb
.num_samples
> 1) ? 4 : 1;
606 gen7_wa_pre_3dstate_multisample(r
);
608 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &vec
->rasterizer
->rs
,
609 &r
->sample_pattern
, sample_count
);
612 /* 3DSTATE_SAMPLE_MASK */
613 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
)
614 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &vec
->rasterizer
->rs
);
618 ilo_render_emit_draw_commands_gen7(struct ilo_render
*render
,
619 const struct ilo_state_vector
*vec
,
620 struct ilo_render_draw_session
*session
)
622 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
625 * We try to keep the order of the commands match, as closely as possible,
626 * that of the classic i965 driver. It allows us to compare the command
629 gen6_draw_common_select(render
, vec
, session
);
630 gen6_draw_common_sip(render
, vec
, session
);
631 gen6_draw_vf_statistics(render
, vec
, session
);
632 gen7_draw_common_pcb_alloc(render
, vec
, session
);
633 gen6_draw_common_base_address(render
, vec
, session
);
634 gen7_draw_common_pointers_1(render
, vec
, session
);
635 gen7_draw_common_urb(render
, vec
, session
);
636 gen7_draw_common_pointers_2(render
, vec
, session
);
637 gen7_draw_wm_multisample(render
, vec
, session
);
638 gen7_draw_gs(render
, vec
, session
);
639 gen7_draw_hs(render
, vec
, session
);
640 gen7_draw_te(render
, vec
, session
);
641 gen7_draw_ds(render
, vec
, session
);
642 gen7_draw_vs(render
, vec
, session
);
643 gen7_draw_sol(render
, vec
, session
);
644 gen6_draw_clip(render
, vec
, session
);
645 gen7_draw_sf(render
, vec
, session
);
646 gen7_draw_wm(render
, vec
, session
);
647 gen6_draw_wm_raster(render
, vec
, session
);
648 gen6_draw_sf_rect(render
, vec
, session
);
649 gen6_draw_vf(render
, vec
, session
);
651 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
655 gen7_rectlist_pcb_alloc(struct ilo_render
*r
,
656 const struct ilo_blitter
*blitter
)
658 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, &blitter
->urb
);
659 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, &blitter
->urb
);
661 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
662 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
666 gen7_rectlist_urb(struct ilo_render
*r
,
667 const struct ilo_blitter
*blitter
)
669 gen7_3DSTATE_URB_VS(r
->builder
, &blitter
->urb
);
670 gen7_3DSTATE_URB_GS(r
->builder
, &blitter
->urb
);
671 gen7_3DSTATE_URB_HS(r
->builder
, &blitter
->urb
);
672 gen7_3DSTATE_URB_DS(r
->builder
, &blitter
->urb
);
676 gen7_rectlist_vs_to_sf(struct ilo_render
*r
,
677 const struct ilo_blitter
*blitter
)
679 gen7_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
680 gen6_3DSTATE_VS(r
->builder
, &blitter
->vs
, 0);
682 gen7_3DSTATE_CONSTANT_HS(r
->builder
, NULL
, NULL
, 0);
683 gen7_3DSTATE_HS(r
->builder
, &blitter
->hs
, 0);
685 gen7_3DSTATE_TE(r
->builder
, &blitter
->ds
);
687 gen7_3DSTATE_CONSTANT_DS(r
->builder
, NULL
, NULL
, 0);
688 gen7_3DSTATE_DS(r
->builder
, &blitter
->ds
, 0);
690 gen7_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
691 gen7_3DSTATE_GS(r
->builder
, &blitter
->gs
, 0);
693 gen7_3DSTATE_STREAMOUT(r
->builder
, &blitter
->sol
);
695 gen6_3DSTATE_CLIP(r
->builder
, &blitter
->fb
.rs
);
697 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
698 gen7_wa_pre_3dstate_sf_depth_bias(r
);
700 gen7_3DSTATE_SF(r
->builder
, &blitter
->fb
.rs
);
701 gen7_3DSTATE_SBE(r
->builder
, &blitter
->sbe
);
705 gen7_rectlist_wm(struct ilo_render
*r
,
706 const struct ilo_blitter
*blitter
)
708 gen7_3DSTATE_WM(r
->builder
, &blitter
->fb
.rs
, &blitter
->ps
);
710 gen7_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
712 gen7_wa_pre_3dstate_ps_max_threads(r
);
713 gen7_3DSTATE_PS(r
->builder
, &blitter
->ps
, 0);
717 gen7_rectlist_wm_depth(struct ilo_render
*r
,
718 const struct ilo_blitter
*blitter
)
720 gen7_wa_pre_depth(r
);
722 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
723 ILO_BLITTER_USE_FB_STENCIL
))
724 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
726 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
727 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
728 &blitter
->fb
.dst
.u
.zs
);
731 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
732 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
733 &blitter
->fb
.dst
.u
.zs
);
736 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
737 blitter
->depth_clear_value
);
741 gen7_rectlist_wm_multisample(struct ilo_render
*r
,
742 const struct ilo_blitter
*blitter
)
744 const uint8_t sample_count
= (blitter
->fb
.num_samples
> 4) ? 8 :
745 (blitter
->fb
.num_samples
> 1) ? 4 : 1;
747 gen7_wa_pre_3dstate_multisample(r
);
749 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &blitter
->fb
.rs
,
750 &r
->sample_pattern
, sample_count
);
752 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &blitter
->fb
.rs
);
756 ilo_render_emit_rectlist_commands_gen7(struct ilo_render
*r
,
757 const struct ilo_blitter
*blitter
,
758 const struct ilo_render_rectlist_session
*session
)
760 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
762 gen7_rectlist_wm_multisample(r
, blitter
);
764 gen6_state_base_address(r
->builder
, true);
766 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
767 session
->vb_start
, session
->vb_end
,
768 sizeof(blitter
->vertices
[0]));
770 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->vf
);
772 gen7_rectlist_pcb_alloc(r
, blitter
);
774 /* needed for any VS-related commands */
775 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
778 gen7_rectlist_urb(r
, blitter
);
780 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
781 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
782 r
->state
.DEPTH_STENCIL_STATE
);
785 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
786 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
787 r
->state
.COLOR_CALC_STATE
);
790 gen7_rectlist_vs_to_sf(r
, blitter
);
791 gen7_rectlist_wm(r
, blitter
);
793 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
794 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
795 r
->state
.CC_VIEWPORT
);
798 gen7_rectlist_wm_depth(r
, blitter
);
800 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
801 blitter
->fb
.width
, blitter
->fb
.height
);
803 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
804 gen7_wa_post_ps_and_later(r
);
806 ilo_render_3dprimitive(r
, &blitter
->draw
, NULL
);
810 ilo_render_get_draw_commands_len_gen7(const struct ilo_render
*render
,
811 const struct ilo_state_vector
*vec
)
815 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
818 len
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
819 len
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
820 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
821 len
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
822 len
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
823 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
826 GEN6_STATE_BASE_ADDRESS__SIZE
+
827 GEN6_STATE_SIP__SIZE
+
828 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
829 GEN6_PIPELINE_SELECT__SIZE
+
830 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
831 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
832 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
833 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
834 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
835 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
836 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
837 GEN75_3DSTATE_VF__SIZE
+
838 GEN6_3DSTATE_VS__SIZE
+
839 GEN6_3DSTATE_GS__SIZE
+
840 GEN6_3DSTATE_CLIP__SIZE
+
841 GEN6_3DSTATE_SF__SIZE
+
842 GEN6_3DSTATE_WM__SIZE
+
843 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
844 GEN7_3DSTATE_HS__SIZE
+
845 GEN7_3DSTATE_TE__SIZE
+
846 GEN7_3DSTATE_DS__SIZE
+
847 GEN7_3DSTATE_STREAMOUT__SIZE
+
848 GEN7_3DSTATE_SBE__SIZE
+
849 GEN7_3DSTATE_PS__SIZE
+
850 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
851 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
852 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
853 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
854 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
855 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
856 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
857 GEN6_3DPRIMITIVE__SIZE
;