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[mesa.git] / src / gallium / drivers / ilo / ilo_render_gen7.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_render.h"
31 #include "util/u_dual_blend.h"
32
33 #include "ilo_blitter.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
37
38 static void
39 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render *r)
40 {
41 /*
42 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
43 *
44 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
45 * in the ring after this instruction
46 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
47 */
48 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
49
50 ILO_DEV_ASSERT(r->dev, 7, 7);
51
52 r->state.deferred_pipe_control_dw1 |= dw1;
53 }
54
55 static void
56 gen7_wa_pre_vs(struct ilo_render *r)
57 {
58 /*
59 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
60 *
61 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
62 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
63 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
64 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
65 * needs to be sent before any combination of VS associated 3DSTATE."
66 */
67 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL |
68 GEN6_PIPE_CONTROL_WRITE_IMM;
69
70 ILO_DEV_ASSERT(r->dev, 7, 7);
71
72 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
73 ilo_render_pipe_control(r, dw1);
74 }
75
76 static void
77 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render *r)
78 {
79 /*
80 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
81 *
82 * "Due to an HW issue driver needs to send a pipe control with stall
83 * when ever there is state change in depth bias related state (in
84 * 3DSTATE_SF)"
85 */
86 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
87
88 ILO_DEV_ASSERT(r->dev, 7, 7);
89
90 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
91 ilo_render_pipe_control(r, dw1);
92 }
93
94 static void
95 gen7_wa_pre_3dstate_multisample(struct ilo_render *r)
96 {
97 /*
98 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
99 *
100 * "Driver must ierarchi that all the caches in the depth pipe are
101 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
102 * requires driver to send a PIPE_CONTROL with a CS stall along with a
103 * Depth Flush prior to this command.
104 */
105 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
106 GEN6_PIPE_CONTROL_CS_STALL;
107
108 ILO_DEV_ASSERT(r->dev, 7, 7.5);
109
110 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
111 ilo_render_pipe_control(r, dw1);
112 }
113
114 static void
115 gen7_wa_pre_depth(struct ilo_render *r)
116 {
117 ILO_DEV_ASSERT(r->dev, 7, 7.5);
118
119 if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
120 /*
121 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
122 *
123 * "Driver must send a least one PIPE_CONTROL command with CS Stall
124 * and a post sync operation prior to the group of depth
125 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
126 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
127 */
128 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL |
129 GEN6_PIPE_CONTROL_WRITE_IMM;
130
131 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
132 ilo_render_pipe_control(r, dw1);
133 }
134
135 /*
136 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
137 *
138 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
139 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
140 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
141 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
142 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
143 * Depth Flush Bit set, followed by another pipelined depth stall
144 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
145 * guarantee that the pipeline from WM onwards is already flushed
146 * (e.g., via a preceding MI_FLUSH)."
147 */
148 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
149 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
150 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
151 }
152
153 static void
154 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render *r)
155 {
156 /*
157 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
158 *
159 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
160 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
161 * Pixel Scoreboard set is required to be issued."
162 */
163 const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
164
165 ILO_DEV_ASSERT(r->dev, 7, 7.5);
166
167 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
168 ilo_render_pipe_control(r, dw1);
169 }
170
171 static void
172 gen7_wa_post_ps_and_later(struct ilo_render *r)
173 {
174 /*
175 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
176 *
177 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
178 * Enable bit set after all the following states are programmed:
179 *
180 * - 3DSTATE_PS
181 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
182 * - 3DSTATE_CONSTANT_PS
183 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
184 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
185 * - 3DSTATE_CC_STATE_POINTERS
186 * - 3DSTATE_BLEND_STATE_POINTERS
187 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
188 */
189 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL;
190
191 ILO_DEV_ASSERT(r->dev, 7, 7);
192
193 r->state.deferred_pipe_control_dw1 |= dw1;
194 }
195
196 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
197
198 void
199 gen7_draw_common_urb(struct ilo_render *r,
200 const struct ilo_state_vector *vec,
201 struct ilo_render_draw_session *session)
202 {
203 /* 3DSTATE_URB_{VS,GS,HS,DS} */
204 if (DIRTY(VE) || DIRTY(VS)) {
205 /* the first 16KB are reserved for VS and PS PCBs */
206 const int offset =
207 (ilo_dev_gen(r->dev) >= ILO_GEN(8)) ||
208 (ilo_dev_gen(r->dev) == ILO_GEN(7.5) && r->dev->gt == 3) ?
209 32768 : 16384;
210 int vs_entry_size, vs_total_size;
211
212 vs_entry_size = (vec->vs) ?
213 ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
214
215 /*
216 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
217 *
218 * "Programming Restriction: As the VS URB entry serves as both the
219 * per-vertex input and output of the VS shader, the VS URB
220 * Allocation Size must be sized to the maximum of the vertex input
221 * and output structures."
222 */
223 if (vs_entry_size < vec->ve->count + vec->ve->prepend_nosrc_cso)
224 vs_entry_size = vec->ve->count + vec->ve->prepend_nosrc_cso;
225
226 vs_entry_size *= sizeof(float) * 4;
227 vs_total_size = r->dev->urb_size - offset;
228
229 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
230 gen7_wa_pre_vs(r);
231
232 gen7_3DSTATE_URB_VS(r->builder,
233 offset, vs_total_size, vs_entry_size);
234
235 gen7_3DSTATE_URB_GS(r->builder, offset, 0, 0);
236 gen7_3DSTATE_URB_HS(r->builder, offset, 0, 0);
237 gen7_3DSTATE_URB_DS(r->builder, offset, 0, 0);
238 }
239 }
240
241 void
242 gen7_draw_common_pcb_alloc(struct ilo_render *r,
243 const struct ilo_state_vector *vec,
244 struct ilo_render_draw_session *session)
245 {
246 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
247 if (r->hw_ctx_changed) {
248 /*
249 * Push constant buffers are only allowed to take up at most the first
250 * 16KB of the URB. Split the space evenly for VS and FS.
251 */
252 const int max_size =
253 (ilo_dev_gen(r->dev) >= ILO_GEN(8)) ||
254 (ilo_dev_gen(r->dev) == ILO_GEN(7.5) && r->dev->gt == 3) ?
255 32768 : 16384;
256 const int size = max_size / 2;
257 int offset = 0;
258
259 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r->builder, offset, size);
260 offset += size;
261
262 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r->builder, offset, size);
263
264 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
265 gen7_wa_post_3dstate_push_constant_alloc_ps(r);
266 }
267 }
268
269 void
270 gen7_draw_common_pointers_1(struct ilo_render *r,
271 const struct ilo_state_vector *vec,
272 struct ilo_render_draw_session *session)
273 {
274 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
275 if (session->viewport_changed) {
276 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r->builder,
277 r->state.CC_VIEWPORT);
278
279 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r->builder,
280 r->state.SF_CLIP_VIEWPORT);
281 }
282 }
283
284 void
285 gen7_draw_common_pointers_2(struct ilo_render *r,
286 const struct ilo_state_vector *vec,
287 struct ilo_render_draw_session *session)
288 {
289 /* 3DSTATE_BLEND_STATE_POINTERS */
290 if (session->blend_changed) {
291 gen7_3DSTATE_BLEND_STATE_POINTERS(r->builder,
292 r->state.BLEND_STATE);
293 }
294
295 /* 3DSTATE_CC_STATE_POINTERS */
296 if (session->cc_changed) {
297 gen7_3DSTATE_CC_STATE_POINTERS(r->builder,
298 r->state.COLOR_CALC_STATE);
299 }
300
301 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
302 if (ilo_dev_gen(r->dev) < ILO_GEN(8) && session->dsa_changed) {
303 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r->builder,
304 r->state.DEPTH_STENCIL_STATE);
305 }
306 }
307
308 void
309 gen7_draw_vs(struct ilo_render *r,
310 const struct ilo_state_vector *vec,
311 struct ilo_render_draw_session *session)
312 {
313 const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
314 const bool emit_3dstate_sampler_state = session->sampler_vs_changed;
315 /* see gen6_draw_vs() */
316 const bool emit_3dstate_constant_vs = session->pcb_vs_changed;
317 const bool emit_3dstate_vs = (DIRTY(VS) || r->instruction_bo_changed);
318
319 /* emit depth stall before any of the VS commands */
320 if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
321 if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
322 emit_3dstate_constant_vs || emit_3dstate_vs)
323 gen7_wa_pre_vs(r);
324 }
325
326 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
327 if (emit_3dstate_binding_table) {
328 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r->builder,
329 r->state.vs.BINDING_TABLE_STATE);
330 }
331
332 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
333 if (emit_3dstate_sampler_state) {
334 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r->builder,
335 r->state.vs.SAMPLER_STATE);
336 }
337
338 /* 3DSTATE_CONSTANT_VS */
339 if (emit_3dstate_constant_vs) {
340 gen7_3DSTATE_CONSTANT_VS(r->builder,
341 &r->state.vs.PUSH_CONSTANT_BUFFER,
342 &r->state.vs.PUSH_CONSTANT_BUFFER_size,
343 1);
344 }
345
346 /* 3DSTATE_VS */
347 if (ilo_dev_gen(r->dev) >= ILO_GEN(8)) {
348 if (emit_3dstate_vs || DIRTY(RASTERIZER)) {
349 gen8_3DSTATE_VS(r->builder, vec->vs,
350 vec->rasterizer->state.clip_plane_enable);
351 }
352 } else {
353 if (emit_3dstate_vs)
354 gen6_3DSTATE_VS(r->builder, vec->vs);
355 }
356 }
357
358 void
359 gen7_draw_hs(struct ilo_render *r,
360 const struct ilo_state_vector *vec,
361 struct ilo_render_draw_session *session)
362 {
363 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
364 if (r->hw_ctx_changed) {
365 gen7_3DSTATE_CONSTANT_HS(r->builder, 0, 0, 0);
366 gen7_disable_3DSTATE_HS(r->builder);
367 }
368
369 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
370 if (r->hw_ctx_changed)
371 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r->builder, 0);
372 }
373
374 void
375 gen7_draw_te(struct ilo_render *r,
376 const struct ilo_state_vector *vec,
377 struct ilo_render_draw_session *session)
378 {
379 /* 3DSTATE_TE */
380 if (r->hw_ctx_changed)
381 gen7_3DSTATE_TE(r->builder);
382 }
383
384 void
385 gen7_draw_ds(struct ilo_render *r,
386 const struct ilo_state_vector *vec,
387 struct ilo_render_draw_session *session)
388 {
389 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
390 if (r->hw_ctx_changed) {
391 gen7_3DSTATE_CONSTANT_DS(r->builder, 0, 0, 0);
392 gen7_disable_3DSTATE_DS(r->builder);
393 }
394
395 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
396 if (r->hw_ctx_changed)
397 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r->builder, 0);
398
399 }
400
401 void
402 gen7_draw_gs(struct ilo_render *r,
403 const struct ilo_state_vector *vec,
404 struct ilo_render_draw_session *session)
405 {
406 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
407 if (r->hw_ctx_changed) {
408 gen7_3DSTATE_CONSTANT_GS(r->builder, 0, 0, 0);
409 gen7_disable_3DSTATE_GS(r->builder);
410 }
411
412 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
413 if (session->binding_table_gs_changed) {
414 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r->builder,
415 r->state.gs.BINDING_TABLE_STATE);
416 }
417 }
418
419 void
420 gen7_draw_sol(struct ilo_render *r,
421 const struct ilo_state_vector *vec,
422 struct ilo_render_draw_session *session)
423 {
424 const struct pipe_stream_output_info *so_info;
425 const struct ilo_shader_state *shader;
426 bool dirty_sh = false;
427
428 if (vec->gs) {
429 shader = vec->gs;
430 dirty_sh = DIRTY(GS);
431 }
432 else {
433 shader = vec->vs;
434 dirty_sh = DIRTY(VS);
435 }
436
437 so_info = ilo_shader_get_kernel_so_info(shader);
438
439 /* 3DSTATE_SO_BUFFER */
440 if ((DIRTY(SO) || dirty_sh || r->batch_bo_changed) &&
441 vec->so.enabled) {
442 int i;
443
444 for (i = 0; i < vec->so.count; i++) {
445 const int stride = so_info->stride[i] * 4; /* in bytes */
446
447 gen7_3DSTATE_SO_BUFFER(r->builder, i, stride, vec->so.states[i]);
448 }
449
450 for (; i < 4; i++)
451 gen7_disable_3DSTATE_SO_BUFFER(r->builder, i);
452 }
453
454 /* 3DSTATE_SO_DECL_LIST */
455 if (dirty_sh && vec->so.enabled)
456 gen7_3DSTATE_SO_DECL_LIST(r->builder, so_info);
457
458 /* 3DSTATE_STREAMOUT */
459 if (DIRTY(SO) || DIRTY(RASTERIZER) || dirty_sh) {
460 const int output_count = ilo_shader_get_kernel_param(shader,
461 ILO_KERNEL_OUTPUT_COUNT);
462 int buf_strides[4] = { 0, 0, 0, 0 };
463 int i;
464
465 for (i = 0; i < vec->so.count; i++)
466 buf_strides[i] = so_info->stride[i] * 4;
467
468 gen7_3DSTATE_STREAMOUT(r->builder, 0,
469 vec->rasterizer->state.rasterizer_discard,
470 output_count, buf_strides);
471 }
472 }
473
474 static void
475 gen7_draw_sf(struct ilo_render *r,
476 const struct ilo_state_vector *vec,
477 struct ilo_render_draw_session *session)
478 {
479 /* 3DSTATE_SBE */
480 if (DIRTY(RASTERIZER) || DIRTY(FS)) {
481 gen7_3DSTATE_SBE(r->builder, vec->fs, (vec->rasterizer) ?
482 vec->rasterizer->state.sprite_coord_mode : 0);
483 }
484
485 /* 3DSTATE_SF */
486 if (DIRTY(RASTERIZER) || DIRTY(FB)) {
487 struct pipe_surface *zs = vec->fb.state.zsbuf;
488
489 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
490 gen7_wa_pre_3dstate_sf_depth_bias(r);
491
492 gen7_3DSTATE_SF(r->builder,
493 (vec->rasterizer) ? &vec->rasterizer->sf : NULL,
494 (zs) ? zs->format : PIPE_FORMAT_NONE,
495 vec->fb.num_samples);
496 }
497 }
498
499 static void
500 gen7_draw_wm(struct ilo_render *r,
501 const struct ilo_state_vector *vec,
502 struct ilo_render_draw_session *session)
503 {
504 /* 3DSTATE_WM */
505 if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DSA) || DIRTY(RASTERIZER)) {
506 const bool cc_may_kill = (vec->dsa->dw_blend_alpha ||
507 vec->blend->alpha_to_coverage);
508
509 gen7_3DSTATE_WM(r->builder, vec->fs, vec->rasterizer, cc_may_kill);
510 }
511
512 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
513 if (session->binding_table_fs_changed) {
514 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
515 r->state.wm.BINDING_TABLE_STATE);
516 }
517
518 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
519 if (session->sampler_fs_changed) {
520 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
521 r->state.wm.SAMPLER_STATE);
522 }
523
524 /* 3DSTATE_CONSTANT_PS */
525 if (session->pcb_fs_changed) {
526 gen7_3DSTATE_CONSTANT_PS(r->builder,
527 &r->state.wm.PUSH_CONSTANT_BUFFER,
528 &r->state.wm.PUSH_CONSTANT_BUFFER_size,
529 1);
530 }
531
532 /* 3DSTATE_PS */
533 if (DIRTY(FS) || DIRTY(BLEND) || r->instruction_bo_changed) {
534 const bool dual_blend = vec->blend->dual_blend;
535
536 if (r->hw_ctx_changed)
537 gen7_wa_pre_3dstate_ps_max_threads(r);
538
539 gen7_3DSTATE_PS(r->builder, vec->fs, dual_blend);
540 }
541
542 /* 3DSTATE_SCISSOR_STATE_POINTERS */
543 if (session->scissor_changed) {
544 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
545 r->state.SCISSOR_RECT);
546 }
547
548 {
549 const bool emit_3dstate_ps = (DIRTY(FS) || DIRTY(BLEND));
550 const bool emit_3dstate_depth_buffer =
551 (DIRTY(FB) || DIRTY(DSA) || r->state_bo_changed);
552
553 if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
554 /* XXX what is the best way to know if this workaround is needed? */
555 if (emit_3dstate_ps ||
556 session->pcb_fs_changed ||
557 session->viewport_changed ||
558 session->binding_table_fs_changed ||
559 session->sampler_fs_changed ||
560 session->cc_changed ||
561 session->blend_changed ||
562 session->dsa_changed)
563 gen7_wa_post_ps_and_later(r);
564 }
565
566 if (emit_3dstate_depth_buffer)
567 gen7_wa_pre_depth(r);
568 }
569
570 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
571 if (DIRTY(FB) || r->batch_bo_changed) {
572 const struct ilo_state_zs *zs;
573 uint32_t clear_params;
574
575 if (vec->fb.state.zsbuf) {
576 const struct ilo_surface_cso *surface =
577 (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
578 const struct ilo_texture_slice *slice =
579 ilo_texture_get_slice(ilo_texture(surface->base.texture),
580 surface->base.u.tex.level, surface->base.u.tex.first_layer);
581
582 assert(!surface->is_rt);
583 zs = &surface->u.zs;
584 clear_params = slice->clear_value;
585 }
586 else {
587 zs = &vec->fb.null_zs;
588 clear_params = 0;
589 }
590
591 gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
592 gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
593 gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
594 gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
595 }
596 }
597
598 static void
599 gen7_draw_wm_multisample(struct ilo_render *r,
600 const struct ilo_state_vector *vec,
601 struct ilo_render_draw_session *session)
602 {
603 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
604 if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
605 const uint32_t *pattern;
606
607 gen7_wa_pre_3dstate_multisample(r);
608
609 pattern = (vec->fb.num_samples > 4) ? r->sample_pattern_8x :
610 (vec->fb.num_samples > 1) ? &r->sample_pattern_4x :
611 &r->sample_pattern_1x;
612
613 gen6_3DSTATE_MULTISAMPLE(r->builder,
614 vec->fb.num_samples, pattern,
615 vec->rasterizer->state.half_pixel_center);
616
617 gen7_3DSTATE_SAMPLE_MASK(r->builder,
618 (vec->fb.num_samples > 1) ? vec->sample_mask : 0x1,
619 vec->fb.num_samples);
620 }
621 }
622
623 void
624 ilo_render_emit_draw_commands_gen7(struct ilo_render *render,
625 const struct ilo_state_vector *vec,
626 struct ilo_render_draw_session *session)
627 {
628 ILO_DEV_ASSERT(render->dev, 7, 7.5);
629
630 /*
631 * We try to keep the order of the commands match, as closely as possible,
632 * that of the classic i965 driver. It allows us to compare the command
633 * streams easily.
634 */
635 gen6_draw_common_select(render, vec, session);
636 gen6_draw_common_sip(render, vec, session);
637 gen6_draw_vf_statistics(render, vec, session);
638 gen7_draw_common_pcb_alloc(render, vec, session);
639 gen6_draw_common_base_address(render, vec, session);
640 gen7_draw_common_pointers_1(render, vec, session);
641 gen7_draw_common_urb(render, vec, session);
642 gen7_draw_common_pointers_2(render, vec, session);
643 gen7_draw_wm_multisample(render, vec, session);
644 gen7_draw_gs(render, vec, session);
645 gen7_draw_hs(render, vec, session);
646 gen7_draw_te(render, vec, session);
647 gen7_draw_ds(render, vec, session);
648 gen7_draw_vs(render, vec, session);
649 gen7_draw_sol(render, vec, session);
650 gen6_draw_clip(render, vec, session);
651 gen7_draw_sf(render, vec, session);
652 gen7_draw_wm(render, vec, session);
653 gen6_draw_wm_raster(render, vec, session);
654 gen6_draw_sf_rect(render, vec, session);
655 gen6_draw_vf(render, vec, session);
656
657 ilo_render_3dprimitive(render, vec->draw, &vec->ib);
658 }
659
660 static void
661 gen7_rectlist_pcb_alloc(struct ilo_render *r,
662 const struct ilo_blitter *blitter)
663 {
664 /*
665 * Push constant buffers are only allowed to take up at most the first
666 * 16KB of the URB. Split the space evenly for VS and FS.
667 */
668 const int max_size =
669 (ilo_dev_gen(r->dev) >= ILO_GEN(8)) ||
670 (ilo_dev_gen(r->dev) == ILO_GEN(7.5) && r->dev->gt == 3) ?
671 32768 : 16384;
672 const int size = max_size / 2;
673 int offset = 0;
674
675 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r->builder, offset, size);
676 offset += size;
677
678 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r->builder, offset, size);
679
680 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
681 gen7_wa_post_3dstate_push_constant_alloc_ps(r);
682 }
683
684 static void
685 gen7_rectlist_urb(struct ilo_render *r,
686 const struct ilo_blitter *blitter)
687 {
688 /* the first 16KB are reserved for VS and PS PCBs */
689 const int offset =
690 (ilo_dev_gen(r->dev) >= ILO_GEN(8)) ||
691 (ilo_dev_gen(r->dev) == ILO_GEN(7.5) && r->dev->gt == 3) ?
692 32768 : 16384;
693
694 gen7_3DSTATE_URB_VS(r->builder, offset, r->dev->urb_size - offset,
695 (blitter->ve.count + blitter->ve.prepend_nosrc_cso) *
696 4 * sizeof(float));
697
698 gen7_3DSTATE_URB_GS(r->builder, offset, 0, 0);
699 gen7_3DSTATE_URB_HS(r->builder, offset, 0, 0);
700 gen7_3DSTATE_URB_DS(r->builder, offset, 0, 0);
701 }
702
703 static void
704 gen7_rectlist_vs_to_sf(struct ilo_render *r,
705 const struct ilo_blitter *blitter)
706 {
707 gen7_3DSTATE_CONSTANT_VS(r->builder, NULL, NULL, 0);
708 gen6_disable_3DSTATE_VS(r->builder);
709
710 gen7_3DSTATE_CONSTANT_HS(r->builder, NULL, NULL, 0);
711 gen7_disable_3DSTATE_HS(r->builder);
712
713 gen7_3DSTATE_TE(r->builder);
714
715 gen7_3DSTATE_CONSTANT_DS(r->builder, NULL, NULL, 0);
716 gen7_disable_3DSTATE_DS(r->builder);
717
718 gen7_3DSTATE_CONSTANT_GS(r->builder, NULL, NULL, 0);
719 gen7_disable_3DSTATE_GS(r->builder);
720
721 gen7_3DSTATE_STREAMOUT(r->builder, 0, false, 0x0, 0);
722
723 gen6_disable_3DSTATE_CLIP(r->builder);
724
725 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
726 gen7_wa_pre_3dstate_sf_depth_bias(r);
727
728 gen7_3DSTATE_SF(r->builder, NULL, blitter->fb.dst.base.format,
729 blitter->fb.num_samples);
730 gen7_3DSTATE_SBE(r->builder, NULL, 0);
731 }
732
733 static void
734 gen7_rectlist_wm(struct ilo_render *r,
735 const struct ilo_blitter *blitter)
736 {
737 uint32_t hiz_op;
738
739 switch (blitter->op) {
740 case ILO_BLITTER_RECTLIST_CLEAR_ZS:
741 hiz_op = GEN7_WM_DW1_DEPTH_CLEAR;
742 break;
743 case ILO_BLITTER_RECTLIST_RESOLVE_Z:
744 hiz_op = GEN7_WM_DW1_DEPTH_RESOLVE;
745 break;
746 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
747 hiz_op = GEN7_WM_DW1_HIZ_RESOLVE;
748 break;
749 default:
750 hiz_op = 0;
751 break;
752 }
753
754 gen7_hiz_3DSTATE_WM(r->builder, hiz_op);
755
756 gen7_3DSTATE_CONSTANT_PS(r->builder, NULL, NULL, 0);
757
758 gen7_wa_pre_3dstate_ps_max_threads(r);
759 gen7_disable_3DSTATE_PS(r->builder);
760 }
761
762 static void
763 gen7_rectlist_wm_depth(struct ilo_render *r,
764 const struct ilo_blitter *blitter)
765 {
766 gen7_wa_pre_depth(r);
767
768 if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
769 ILO_BLITTER_USE_FB_STENCIL))
770 gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
771
772 if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
773 gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
774 &blitter->fb.dst.u.zs);
775 }
776
777 if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
778 gen6_3DSTATE_STENCIL_BUFFER(r->builder,
779 &blitter->fb.dst.u.zs);
780 }
781
782 gen7_3DSTATE_CLEAR_PARAMS(r->builder,
783 blitter->depth_clear_value);
784 }
785
786 static void
787 gen7_rectlist_wm_multisample(struct ilo_render *r,
788 const struct ilo_blitter *blitter)
789 {
790 const uint32_t *pattern =
791 (blitter->fb.num_samples > 4) ? r->sample_pattern_8x :
792 (blitter->fb.num_samples > 1) ? &r->sample_pattern_4x :
793 &r->sample_pattern_1x;
794
795 gen7_wa_pre_3dstate_multisample(r);
796
797 gen6_3DSTATE_MULTISAMPLE(r->builder, blitter->fb.num_samples,
798 pattern, true);
799
800 gen7_3DSTATE_SAMPLE_MASK(r->builder,
801 (1 << blitter->fb.num_samples) - 1, blitter->fb.num_samples);
802 }
803
804 void
805 ilo_render_emit_rectlist_commands_gen7(struct ilo_render *r,
806 const struct ilo_blitter *blitter,
807 const struct ilo_render_rectlist_session *session)
808 {
809 ILO_DEV_ASSERT(r->dev, 7, 7.5);
810
811 gen7_rectlist_wm_multisample(r, blitter);
812
813 gen6_state_base_address(r->builder, true);
814
815 gen6_user_3DSTATE_VERTEX_BUFFERS(r->builder,
816 session->vb_start, session->vb_end,
817 sizeof(blitter->vertices[0]));
818
819 gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &blitter->ve);
820
821 gen7_rectlist_pcb_alloc(r, blitter);
822
823 /* needed for any VS-related commands */
824 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
825 gen7_wa_pre_vs(r);
826
827 gen7_rectlist_urb(r, blitter);
828
829 if (blitter->uses & ILO_BLITTER_USE_DSA) {
830 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r->builder,
831 r->state.DEPTH_STENCIL_STATE);
832 }
833
834 if (blitter->uses & ILO_BLITTER_USE_CC) {
835 gen7_3DSTATE_CC_STATE_POINTERS(r->builder,
836 r->state.COLOR_CALC_STATE);
837 }
838
839 gen7_rectlist_vs_to_sf(r, blitter);
840 gen7_rectlist_wm(r, blitter);
841
842 if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
843 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r->builder,
844 r->state.CC_VIEWPORT);
845 }
846
847 gen7_rectlist_wm_depth(r, blitter);
848
849 gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
850 blitter->fb.width, blitter->fb.height);
851
852 if (ilo_dev_gen(r->dev) == ILO_GEN(7))
853 gen7_wa_post_ps_and_later(r);
854
855 ilo_render_3dprimitive(r, &blitter->draw, NULL);
856 }
857
858 int
859 ilo_render_get_draw_commands_len_gen7(const struct ilo_render *render,
860 const struct ilo_state_vector *vec)
861 {
862 static int len;
863
864 ILO_DEV_ASSERT(render->dev, 7, 7.5);
865
866 if (!len) {
867 len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
868 len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
869 len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
870 len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
871 len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
872 len += GEN6_PIPE_CONTROL__SIZE * 5;
873
874 len +=
875 GEN6_STATE_BASE_ADDRESS__SIZE +
876 GEN6_STATE_SIP__SIZE +
877 GEN6_3DSTATE_VF_STATISTICS__SIZE +
878 GEN6_PIPELINE_SELECT__SIZE +
879 GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
880 GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
881 GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
882 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
883 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
884 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
885 GEN6_3DSTATE_INDEX_BUFFER__SIZE +
886 GEN75_3DSTATE_VF__SIZE +
887 GEN6_3DSTATE_VS__SIZE +
888 GEN6_3DSTATE_GS__SIZE +
889 GEN6_3DSTATE_CLIP__SIZE +
890 GEN6_3DSTATE_SF__SIZE +
891 GEN6_3DSTATE_WM__SIZE +
892 GEN6_3DSTATE_SAMPLE_MASK__SIZE +
893 GEN7_3DSTATE_HS__SIZE +
894 GEN7_3DSTATE_TE__SIZE +
895 GEN7_3DSTATE_DS__SIZE +
896 GEN7_3DSTATE_STREAMOUT__SIZE +
897 GEN7_3DSTATE_SBE__SIZE +
898 GEN7_3DSTATE_PS__SIZE +
899 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
900 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
901 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
902 GEN6_3DSTATE_LINE_STIPPLE__SIZE +
903 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
904 GEN6_3DSTATE_MULTISAMPLE__SIZE +
905 GEN7_3DSTATE_SO_DECL_LIST__SIZE +
906 GEN6_3DPRIMITIVE__SIZE;
907 }
908
909 return len;
910 }