2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_render.h"
32 #include "ilo_blitter.h"
33 #include "ilo_resource.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
39 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render
*r
)
42 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
44 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
45 * in the ring after this instruction
46 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
48 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
50 ILO_DEV_ASSERT(r
->dev
, 7, 7);
52 r
->state
.deferred_pipe_control_dw1
|= dw1
;
56 gen7_wa_pre_vs(struct ilo_render
*r
)
59 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
61 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
62 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
63 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
64 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
65 * needs to be sent before any combination of VS associated 3DSTATE."
67 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
68 GEN6_PIPE_CONTROL_WRITE_IMM
;
70 ILO_DEV_ASSERT(r
->dev
, 7, 7);
72 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
73 ilo_render_pipe_control(r
, dw1
);
77 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render
*r
)
80 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
82 * "Due to an HW issue driver needs to send a pipe control with stall
83 * when ever there is state change in depth bias related state (in
86 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
88 ILO_DEV_ASSERT(r
->dev
, 7, 7);
90 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
91 ilo_render_pipe_control(r
, dw1
);
95 gen7_wa_pre_3dstate_multisample(struct ilo_render
*r
)
98 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
100 * "Driver must ierarchi that all the caches in the depth pipe are
101 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
102 * requires driver to send a PIPE_CONTROL with a CS stall along with a
103 * Depth Flush prior to this command.
105 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
106 GEN6_PIPE_CONTROL_CS_STALL
;
108 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
110 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
111 ilo_render_pipe_control(r
, dw1
);
115 gen7_wa_pre_depth(struct ilo_render
*r
)
117 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
119 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
121 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
123 * "Driver must send a least one PIPE_CONTROL command with CS Stall
124 * and a post sync operation prior to the group of depth
125 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
126 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
128 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
|
129 GEN6_PIPE_CONTROL_WRITE_IMM
;
131 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
132 ilo_render_pipe_control(r
, dw1
);
136 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
138 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
139 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
140 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
141 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
142 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
143 * Depth Flush Bit set, followed by another pipelined depth stall
144 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
145 * guarantee that the pipeline from WM onwards is already flushed
146 * (e.g., via a preceding MI_FLUSH)."
148 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
149 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
150 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
154 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render
*r
)
157 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
159 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
160 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
161 * Pixel Scoreboard set is required to be issued."
163 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
165 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
167 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
168 ilo_render_pipe_control(r
, dw1
);
172 gen7_wa_post_ps_and_later(struct ilo_render
*r
)
175 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
177 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
178 * Enable bit set after all the following states are programmed:
181 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
182 * - 3DSTATE_CONSTANT_PS
183 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
184 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
185 * - 3DSTATE_CC_STATE_POINTERS
186 * - 3DSTATE_BLEND_STATE_POINTERS
187 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
189 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
;
191 ILO_DEV_ASSERT(r
->dev
, 7, 7);
193 r
->state
.deferred_pipe_control_dw1
|= dw1
;
196 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
199 gen7_draw_common_urb(struct ilo_render
*r
,
200 const struct ilo_state_vector
*vec
,
201 struct ilo_render_draw_session
*session
)
203 /* 3DSTATE_URB_{VS,GS,HS,DS} */
204 if (session
->urb_delta
.dirty
& (ILO_STATE_URB_3DSTATE_URB_VS
|
205 ILO_STATE_URB_3DSTATE_URB_HS
|
206 ILO_STATE_URB_3DSTATE_URB_DS
|
207 ILO_STATE_URB_3DSTATE_URB_GS
)) {
208 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
211 gen7_3DSTATE_URB_VS(r
->builder
, &vec
->urb
);
212 gen7_3DSTATE_URB_GS(r
->builder
, &vec
->urb
);
213 gen7_3DSTATE_URB_HS(r
->builder
, &vec
->urb
);
214 gen7_3DSTATE_URB_DS(r
->builder
, &vec
->urb
);
219 gen7_draw_common_pcb_alloc(struct ilo_render
*r
,
220 const struct ilo_state_vector
*vec
,
221 struct ilo_render_draw_session
*session
)
223 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
224 if (session
->urb_delta
.dirty
&
225 (ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS
|
226 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS
|
227 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS
|
228 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS
|
229 ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS
)) {
230 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, &vec
->urb
);
231 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS(r
->builder
, &vec
->urb
);
232 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, &vec
->urb
);
234 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
235 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
240 gen7_draw_common_pointers_1(struct ilo_render
*r
,
241 const struct ilo_state_vector
*vec
,
242 struct ilo_render_draw_session
*session
)
244 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
245 if (session
->viewport_changed
) {
246 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
247 r
->state
.CC_VIEWPORT
);
249 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r
->builder
,
250 r
->state
.SF_CLIP_VIEWPORT
);
255 gen7_draw_common_pointers_2(struct ilo_render
*r
,
256 const struct ilo_state_vector
*vec
,
257 struct ilo_render_draw_session
*session
)
259 /* 3DSTATE_BLEND_STATE_POINTERS */
260 if (session
->blend_changed
) {
261 gen7_3DSTATE_BLEND_STATE_POINTERS(r
->builder
,
262 r
->state
.BLEND_STATE
);
265 /* 3DSTATE_CC_STATE_POINTERS */
266 if (session
->cc_changed
) {
267 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
268 r
->state
.COLOR_CALC_STATE
);
271 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
272 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8) && session
->dsa_changed
) {
273 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
274 r
->state
.DEPTH_STENCIL_STATE
);
279 gen7_draw_vs(struct ilo_render
*r
,
280 const struct ilo_state_vector
*vec
,
281 struct ilo_render_draw_session
*session
)
283 const bool emit_3dstate_binding_table
= session
->binding_table_vs_changed
;
284 const bool emit_3dstate_sampler_state
= session
->sampler_vs_changed
;
285 /* see gen6_draw_vs() */
286 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
287 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
289 /* emit depth stall before any of the VS commands */
290 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
291 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
292 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
296 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
297 if (emit_3dstate_binding_table
) {
298 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r
->builder
,
299 r
->state
.vs
.BINDING_TABLE_STATE
);
302 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
303 if (emit_3dstate_sampler_state
) {
304 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r
->builder
,
305 r
->state
.vs
.SAMPLER_STATE
);
308 /* 3DSTATE_CONSTANT_VS */
309 if (emit_3dstate_constant_vs
) {
310 gen7_3DSTATE_CONSTANT_VS(r
->builder
,
311 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
312 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
317 if (emit_3dstate_vs
) {
318 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->vs
);
319 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->vs
);
321 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
322 gen8_3DSTATE_VS(r
->builder
, &cso
->vs
, kernel_offset
);
324 gen6_3DSTATE_VS(r
->builder
, &cso
->vs
, kernel_offset
);
329 gen7_draw_hs(struct ilo_render
*r
,
330 const struct ilo_state_vector
*vec
,
331 struct ilo_render_draw_session
*session
)
333 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
334 if (r
->hw_ctx_changed
) {
335 const struct ilo_state_hs
*hs
= &vec
->disabled_hs
;
336 const uint32_t kernel_offset
= 0;
338 gen7_3DSTATE_CONSTANT_HS(r
->builder
, 0, 0, 0);
340 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
341 gen8_3DSTATE_HS(r
->builder
, hs
, kernel_offset
);
343 gen7_3DSTATE_HS(r
->builder
, hs
, kernel_offset
);
346 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
347 if (r
->hw_ctx_changed
)
348 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r
->builder
, 0);
352 gen7_draw_te(struct ilo_render
*r
,
353 const struct ilo_state_vector
*vec
,
354 struct ilo_render_draw_session
*session
)
357 if (r
->hw_ctx_changed
) {
358 const struct ilo_state_ds
*ds
= &vec
->disabled_ds
;
359 gen7_3DSTATE_TE(r
->builder
, ds
);
364 gen7_draw_ds(struct ilo_render
*r
,
365 const struct ilo_state_vector
*vec
,
366 struct ilo_render_draw_session
*session
)
368 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
369 if (r
->hw_ctx_changed
) {
370 const struct ilo_state_ds
*ds
= &vec
->disabled_ds
;
371 const uint32_t kernel_offset
= 0;
373 gen7_3DSTATE_CONSTANT_DS(r
->builder
, 0, 0, 0);
375 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
376 gen8_3DSTATE_DS(r
->builder
, ds
, kernel_offset
);
378 gen7_3DSTATE_DS(r
->builder
, ds
, kernel_offset
);
381 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
382 if (r
->hw_ctx_changed
)
383 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r
->builder
, 0);
388 gen7_draw_gs(struct ilo_render
*r
,
389 const struct ilo_state_vector
*vec
,
390 struct ilo_render_draw_session
*session
)
392 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
393 if (r
->hw_ctx_changed
) {
394 const struct ilo_state_gs
*gs
= &vec
->disabled_gs
;
395 const uint32_t kernel_offset
= 0;
397 gen7_3DSTATE_CONSTANT_GS(r
->builder
, 0, 0, 0);
399 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
400 gen8_3DSTATE_GS(r
->builder
, gs
, kernel_offset
);
402 gen7_3DSTATE_GS(r
->builder
, gs
, kernel_offset
);
405 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
406 if (session
->binding_table_gs_changed
) {
407 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r
->builder
,
408 r
->state
.gs
.BINDING_TABLE_STATE
);
413 gen7_draw_sol(struct ilo_render
*r
,
414 const struct ilo_state_vector
*vec
,
415 struct ilo_render_draw_session
*session
)
417 const struct ilo_state_sol
*sol
;
418 const struct ilo_shader_state
*shader
;
419 bool dirty_sh
= false;
423 dirty_sh
= DIRTY(GS
);
427 dirty_sh
= DIRTY(VS
);
430 sol
= ilo_shader_get_kernel_sol(shader
);
432 /* 3DSTATE_SO_BUFFER */
433 if ((DIRTY(SO
) || dirty_sh
|| r
->batch_bo_changed
) &&
437 for (i
= 0; i
< ILO_STATE_SOL_MAX_BUFFER_COUNT
; i
++) {
438 const struct pipe_stream_output_target
*target
=
439 (i
< vec
->so
.count
&& vec
->so
.states
[i
]) ?
440 vec
->so
.states
[i
] : NULL
;
441 const struct ilo_state_sol_buffer
*sb
= (target
) ?
442 &((const struct ilo_stream_output_target
*) target
)->sb
:
445 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
446 gen8_3DSTATE_SO_BUFFER(r
->builder
, sol
, sb
, i
);
448 gen7_3DSTATE_SO_BUFFER(r
->builder
, sol
, sb
, i
);
452 /* 3DSTATE_SO_DECL_LIST */
453 if (dirty_sh
&& vec
->so
.enabled
)
454 gen7_3DSTATE_SO_DECL_LIST(r
->builder
, sol
);
457 * From the Ivy Bridge PRM, volume 2 part 1, page 196-197:
459 * "Anytime the SOL unit MMIO registers or non-pipeline state are
460 * written, the SOL unit needs to receive a pipeline state update with
461 * SOL unit dirty state for information programmed in MMIO/NP to get
462 * loaded into the SOL unit.
464 * The SOL unit incorrectly double buffers MMIO/NP registers and only
465 * moves them into the design for usage when control topology is
466 * received with the SOL unit dirty state.
468 * If the state does not change, need to resend the same state.
470 * Because of corruption, software must flush the whole fixed function
471 * pipeline when 3DSTATE_STREAMOUT changes state."
473 * The first and fourth paragraphs are gone on Gen7.5+.
476 /* 3DSTATE_STREAMOUT */
477 gen7_3DSTATE_STREAMOUT(r
->builder
, sol
);
481 gen7_draw_sf(struct ilo_render
*r
,
482 const struct ilo_state_vector
*vec
,
483 struct ilo_render_draw_session
*session
)
487 const struct ilo_state_sbe
*sbe
= ilo_shader_get_kernel_sbe(vec
->fs
);
488 gen7_3DSTATE_SBE(r
->builder
, sbe
);
492 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SF
) {
493 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
494 gen7_wa_pre_3dstate_sf_depth_bias(r
);
496 gen7_3DSTATE_SF(r
->builder
, &vec
->rasterizer
->rs
);
501 gen7_draw_wm(struct ilo_render
*r
,
502 const struct ilo_state_vector
*vec
,
503 struct ilo_render_draw_session
*session
)
505 const union ilo_shader_cso
*cso
= ilo_shader_get_kernel_cso(vec
->fs
);
506 const uint32_t kernel_offset
= ilo_shader_get_kernel_offset(vec
->fs
);
509 if (DIRTY(FS
) || (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_WM
))
510 gen7_3DSTATE_WM(r
->builder
, &vec
->rasterizer
->rs
, &cso
->ps
);
512 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
513 if (session
->binding_table_fs_changed
) {
514 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
515 r
->state
.wm
.BINDING_TABLE_STATE
);
518 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
519 if (session
->sampler_fs_changed
) {
520 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
521 r
->state
.wm
.SAMPLER_STATE
);
524 /* 3DSTATE_CONSTANT_PS */
525 if (session
->pcb_fs_changed
) {
526 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
527 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
528 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
533 if (DIRTY(FS
) || r
->instruction_bo_changed
) {
534 if (r
->hw_ctx_changed
)
535 gen7_wa_pre_3dstate_ps_max_threads(r
);
537 gen7_3DSTATE_PS(r
->builder
, &cso
->ps
, kernel_offset
);
540 /* 3DSTATE_SCISSOR_STATE_POINTERS */
541 if (session
->scissor_changed
) {
542 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
543 r
->state
.SCISSOR_RECT
);
547 const bool emit_3dstate_ps
= (DIRTY(FS
) || DIRTY(BLEND
));
548 const bool emit_3dstate_depth_buffer
=
549 (DIRTY(FB
) || DIRTY(DSA
) || r
->state_bo_changed
);
551 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
552 /* XXX what is the best way to know if this workaround is needed? */
553 if (emit_3dstate_ps
||
554 session
->pcb_fs_changed
||
555 session
->viewport_changed
||
556 session
->binding_table_fs_changed
||
557 session
->sampler_fs_changed
||
558 session
->cc_changed
||
559 session
->blend_changed
||
560 session
->dsa_changed
)
561 gen7_wa_post_ps_and_later(r
);
564 if (emit_3dstate_depth_buffer
)
565 gen7_wa_pre_depth(r
);
568 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
569 if (DIRTY(FB
) || r
->batch_bo_changed
) {
570 const struct ilo_state_zs
*zs
;
571 uint32_t clear_params
;
573 if (vec
->fb
.state
.zsbuf
) {
574 const struct ilo_surface_cso
*surface
=
575 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
576 const struct ilo_texture_slice
*slice
=
577 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
578 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
580 assert(!surface
->is_rt
);
582 clear_params
= slice
->clear_value
;
585 zs
= &vec
->fb
.null_zs
;
589 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
590 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
591 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
592 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
597 gen7_draw_wm_multisample(struct ilo_render
*r
,
598 const struct ilo_state_vector
*vec
,
599 struct ilo_render_draw_session
*session
)
601 /* 3DSTATE_MULTISAMPLE */
602 if (DIRTY(FB
) || (session
->rs_delta
.dirty
&
603 ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
)) {
604 const uint8_t sample_count
= (vec
->fb
.num_samples
> 4) ? 8 :
605 (vec
->fb
.num_samples
> 1) ? 4 : 1;
607 gen7_wa_pre_3dstate_multisample(r
);
609 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &vec
->rasterizer
->rs
,
610 &r
->sample_pattern
, sample_count
);
613 /* 3DSTATE_SAMPLE_MASK */
614 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
)
615 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &vec
->rasterizer
->rs
);
619 ilo_render_emit_draw_commands_gen7(struct ilo_render
*render
,
620 const struct ilo_state_vector
*vec
,
621 struct ilo_render_draw_session
*session
)
623 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
626 * We try to keep the order of the commands match, as closely as possible,
627 * that of the classic i965 driver. It allows us to compare the command
630 gen6_draw_common_select(render
, vec
, session
);
631 gen6_draw_common_sip(render
, vec
, session
);
632 gen6_draw_vf_statistics(render
, vec
, session
);
633 gen7_draw_common_pcb_alloc(render
, vec
, session
);
634 gen6_draw_common_base_address(render
, vec
, session
);
635 gen7_draw_common_pointers_1(render
, vec
, session
);
636 gen7_draw_common_urb(render
, vec
, session
);
637 gen7_draw_common_pointers_2(render
, vec
, session
);
638 gen7_draw_wm_multisample(render
, vec
, session
);
639 gen7_draw_gs(render
, vec
, session
);
640 gen7_draw_hs(render
, vec
, session
);
641 gen7_draw_te(render
, vec
, session
);
642 gen7_draw_ds(render
, vec
, session
);
643 gen7_draw_vs(render
, vec
, session
);
644 gen7_draw_sol(render
, vec
, session
);
645 gen6_draw_clip(render
, vec
, session
);
646 gen7_draw_sf(render
, vec
, session
);
647 gen7_draw_wm(render
, vec
, session
);
648 gen6_draw_wm_raster(render
, vec
, session
);
649 gen6_draw_sf_rect(render
, vec
, session
);
650 gen6_draw_vf(render
, vec
, session
);
652 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
656 gen7_rectlist_pcb_alloc(struct ilo_render
*r
,
657 const struct ilo_blitter
*blitter
)
659 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, &blitter
->urb
);
660 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, &blitter
->urb
);
662 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
663 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
667 gen7_rectlist_urb(struct ilo_render
*r
,
668 const struct ilo_blitter
*blitter
)
670 gen7_3DSTATE_URB_VS(r
->builder
, &blitter
->urb
);
671 gen7_3DSTATE_URB_GS(r
->builder
, &blitter
->urb
);
672 gen7_3DSTATE_URB_HS(r
->builder
, &blitter
->urb
);
673 gen7_3DSTATE_URB_DS(r
->builder
, &blitter
->urb
);
677 gen7_rectlist_vs_to_sf(struct ilo_render
*r
,
678 const struct ilo_blitter
*blitter
)
680 gen7_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
681 gen6_3DSTATE_VS(r
->builder
, &blitter
->vs
, 0);
683 gen7_3DSTATE_CONSTANT_HS(r
->builder
, NULL
, NULL
, 0);
684 gen7_3DSTATE_HS(r
->builder
, &blitter
->hs
, 0);
686 gen7_3DSTATE_TE(r
->builder
, &blitter
->ds
);
688 gen7_3DSTATE_CONSTANT_DS(r
->builder
, NULL
, NULL
, 0);
689 gen7_3DSTATE_DS(r
->builder
, &blitter
->ds
, 0);
691 gen7_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
692 gen7_3DSTATE_GS(r
->builder
, &blitter
->gs
, 0);
694 gen7_3DSTATE_STREAMOUT(r
->builder
, &blitter
->sol
);
696 gen6_3DSTATE_CLIP(r
->builder
, &blitter
->fb
.rs
);
698 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
699 gen7_wa_pre_3dstate_sf_depth_bias(r
);
701 gen7_3DSTATE_SF(r
->builder
, &blitter
->fb
.rs
);
702 gen7_3DSTATE_SBE(r
->builder
, &blitter
->sbe
);
706 gen7_rectlist_wm(struct ilo_render
*r
,
707 const struct ilo_blitter
*blitter
)
709 gen7_3DSTATE_WM(r
->builder
, &blitter
->fb
.rs
, &blitter
->ps
);
711 gen7_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
713 gen7_wa_pre_3dstate_ps_max_threads(r
);
714 gen7_3DSTATE_PS(r
->builder
, &blitter
->ps
, 0);
718 gen7_rectlist_wm_depth(struct ilo_render
*r
,
719 const struct ilo_blitter
*blitter
)
721 gen7_wa_pre_depth(r
);
723 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
724 ILO_BLITTER_USE_FB_STENCIL
))
725 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
727 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
728 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
729 &blitter
->fb
.dst
.u
.zs
);
732 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
733 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
734 &blitter
->fb
.dst
.u
.zs
);
737 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
738 blitter
->depth_clear_value
);
742 gen7_rectlist_wm_multisample(struct ilo_render
*r
,
743 const struct ilo_blitter
*blitter
)
745 const uint8_t sample_count
= (blitter
->fb
.num_samples
> 4) ? 8 :
746 (blitter
->fb
.num_samples
> 1) ? 4 : 1;
748 gen7_wa_pre_3dstate_multisample(r
);
750 gen6_3DSTATE_MULTISAMPLE(r
->builder
, &blitter
->fb
.rs
,
751 &r
->sample_pattern
, sample_count
);
753 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &blitter
->fb
.rs
);
757 ilo_render_emit_rectlist_commands_gen7(struct ilo_render
*r
,
758 const struct ilo_blitter
*blitter
,
759 const struct ilo_render_rectlist_session
*session
)
761 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
763 gen7_rectlist_wm_multisample(r
, blitter
);
765 gen6_state_base_address(r
->builder
, true);
767 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
768 session
->vb_start
, session
->vb_end
,
769 sizeof(blitter
->vertices
[0]));
771 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->vf
);
773 gen7_rectlist_pcb_alloc(r
, blitter
);
775 /* needed for any VS-related commands */
776 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
779 gen7_rectlist_urb(r
, blitter
);
781 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
782 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
783 r
->state
.DEPTH_STENCIL_STATE
);
786 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
787 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
788 r
->state
.COLOR_CALC_STATE
);
791 gen7_rectlist_vs_to_sf(r
, blitter
);
792 gen7_rectlist_wm(r
, blitter
);
794 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
795 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
796 r
->state
.CC_VIEWPORT
);
799 gen7_rectlist_wm_depth(r
, blitter
);
801 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
802 blitter
->fb
.width
, blitter
->fb
.height
);
804 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
805 gen7_wa_post_ps_and_later(r
);
807 ilo_render_3dprimitive(r
, &blitter
->draw
, NULL
);
811 ilo_render_get_draw_commands_len_gen7(const struct ilo_render
*render
,
812 const struct ilo_state_vector
*vec
)
816 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
819 len
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
820 len
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
821 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
822 len
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
823 len
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
824 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
827 GEN6_STATE_BASE_ADDRESS__SIZE
+
828 GEN6_STATE_SIP__SIZE
+
829 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
830 GEN6_PIPELINE_SELECT__SIZE
+
831 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
832 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
833 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
834 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
835 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
836 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
837 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
838 GEN75_3DSTATE_VF__SIZE
+
839 GEN6_3DSTATE_VS__SIZE
+
840 GEN6_3DSTATE_GS__SIZE
+
841 GEN6_3DSTATE_CLIP__SIZE
+
842 GEN6_3DSTATE_SF__SIZE
+
843 GEN6_3DSTATE_WM__SIZE
+
844 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
845 GEN7_3DSTATE_HS__SIZE
+
846 GEN7_3DSTATE_TE__SIZE
+
847 GEN7_3DSTATE_DS__SIZE
+
848 GEN7_3DSTATE_STREAMOUT__SIZE
+
849 GEN7_3DSTATE_SBE__SIZE
+
850 GEN7_3DSTATE_PS__SIZE
+
851 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
852 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
853 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
854 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
855 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
856 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
857 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
858 GEN6_3DPRIMITIVE__SIZE
;