2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
31 #include "ilo_blitter.h"
32 #include "ilo_builder_3d.h"
33 #include "ilo_builder_render.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render.h"
37 #include "ilo_render_gen.h"
38 #include "ilo_render_gen7.h"
41 * A wrapper for gen6_PIPE_CONTROL().
44 gen7_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
46 struct intel_bo
*bo
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) ?
47 r
->workaround_bo
: NULL
;
49 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
51 if (dw1
& GEN6_PIPE_CONTROL_CS_STALL
) {
52 /* CS stall cannot be set alone */
53 const uint32_t mask
= GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
|
54 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
55 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
|
56 GEN6_PIPE_CONTROL_DEPTH_STALL
|
57 GEN6_PIPE_CONTROL_WRITE__MASK
;
59 dw1
|= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
62 gen6_PIPE_CONTROL(r
->builder
, dw1
, bo
, 0, false);
65 r
->state
.current_pipe_control_dw1
|= dw1
;
66 r
->state
.deferred_pipe_control_dw1
&= ~dw1
;
70 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render
*r
)
73 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
75 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
76 * in the ring after this instruction
77 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
79 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
81 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
83 r
->state
.deferred_pipe_control_dw1
|= dw1
;
87 gen7_wa_pre_vs(struct ilo_render
*r
)
90 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
92 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
93 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
94 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
95 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
96 * needs to be sent before any combination of VS associated 3DSTATE."
98 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
99 GEN6_PIPE_CONTROL_WRITE_IMM
;
101 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
103 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
104 gen7_pipe_control(r
, dw1
);
108 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render
*r
)
111 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
113 * "Due to an HW issue driver needs to send a pipe control with stall
114 * when ever there is state change in depth bias related state (in
117 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
119 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
121 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
122 gen7_pipe_control(r
, dw1
);
126 gen7_wa_pre_3dstate_multisample(struct ilo_render
*r
)
129 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
131 * "Driver must ierarchi that all the caches in the depth pipe are
132 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
133 * requires driver to send a PIPE_CONTROL with a CS stall along with a
134 * Depth Flush prior to this command.
136 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
137 GEN6_PIPE_CONTROL_CS_STALL
;
139 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
141 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
142 gen7_pipe_control(r
, dw1
);
146 gen7_wa_pre_depth(struct ilo_render
*r
)
149 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
151 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
152 * a post sync operation prior to the group of depth
153 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
154 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
156 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
|
157 GEN6_PIPE_CONTROL_WRITE_IMM
;
159 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
161 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
162 gen7_pipe_control(r
, dw1
);
165 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
167 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
168 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
169 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
170 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
171 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
172 * Depth Flush Bit set, followed by another pipelined depth stall
173 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
174 * guarantee that the pipeline from WM onwards is already flushed
175 * (e.g., via a preceding MI_FLUSH)."
177 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
178 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
179 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
183 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render
*r
)
186 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
188 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
189 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
190 * Pixel Scoreboard set is required to be issued."
192 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
194 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
196 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
197 gen7_pipe_control(r
, dw1
);
201 gen7_wa_post_ps_and_later(struct ilo_render
*r
)
204 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
206 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
207 * Enable bit set after all the following states are programmed:
210 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
211 * - 3DSTATE_CONSTANT_PS
212 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
213 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
214 * - 3DSTATE_CC_STATE_POINTERS
215 * - 3DSTATE_BLEND_STATE_POINTERS
216 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
218 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
;
220 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
222 r
->state
.deferred_pipe_control_dw1
|= dw1
;
225 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
228 gen7_draw_common_urb(struct ilo_render
*r
,
229 const struct ilo_state_vector
*vec
,
230 struct gen6_draw_session
*session
)
232 /* 3DSTATE_URB_{VS,GS,HS,DS} */
233 if (DIRTY(VE
) || DIRTY(VS
)) {
234 /* the first 16KB are reserved for VS and PS PCBs */
235 const int offset
= (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) &&
236 r
->dev
->gt
== 3) ? 32768 : 16384;
237 int vs_entry_size
, vs_total_size
;
239 vs_entry_size
= (vec
->vs
) ?
240 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
243 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
245 * "Programming Restriction: As the VS URB entry serves as both the
246 * per-vertex input and output of the VS shader, the VS URB
247 * Allocation Size must be sized to the maximum of the vertex input
248 * and output structures."
250 if (vs_entry_size
< vec
->ve
->count
)
251 vs_entry_size
= vec
->ve
->count
;
253 vs_entry_size
*= sizeof(float) * 4;
254 vs_total_size
= r
->dev
->urb_size
- offset
;
258 gen7_3DSTATE_URB_VS(r
->builder
,
259 offset
, vs_total_size
, vs_entry_size
);
261 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
262 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
263 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
268 gen7_draw_common_pcb_alloc(struct ilo_render
*r
,
269 const struct ilo_state_vector
*vec
,
270 struct gen6_draw_session
*session
)
272 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
273 if (r
->hw_ctx_changed
) {
275 * Push constant buffers are only allowed to take up at most the first
276 * 16KB of the URB. Split the space evenly for VS and FS.
278 const int max_size
= (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) &&
279 r
->dev
->gt
== 3) ? 32768 : 16384;
280 const int size
= max_size
/ 2;
283 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
286 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
288 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
289 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
294 gen7_draw_common_pointers_1(struct ilo_render
*r
,
295 const struct ilo_state_vector
*vec
,
296 struct gen6_draw_session
*session
)
298 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
299 if (session
->viewport_changed
) {
300 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
301 r
->state
.CC_VIEWPORT
);
303 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r
->builder
,
304 r
->state
.SF_CLIP_VIEWPORT
);
309 gen7_draw_common_pointers_2(struct ilo_render
*r
,
310 const struct ilo_state_vector
*vec
,
311 struct gen6_draw_session
*session
)
313 /* 3DSTATE_BLEND_STATE_POINTERS */
314 if (session
->blend_changed
) {
315 gen7_3DSTATE_BLEND_STATE_POINTERS(r
->builder
,
316 r
->state
.BLEND_STATE
);
319 /* 3DSTATE_CC_STATE_POINTERS */
320 if (session
->cc_changed
) {
321 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
322 r
->state
.COLOR_CALC_STATE
);
325 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
326 if (session
->dsa_changed
) {
327 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
328 r
->state
.DEPTH_STENCIL_STATE
);
333 gen7_draw_vs(struct ilo_render
*r
,
334 const struct ilo_state_vector
*vec
,
335 struct gen6_draw_session
*session
)
337 const bool emit_3dstate_binding_table
=
338 session
->binding_table_vs_changed
;
339 const bool emit_3dstate_sampler_state
=
340 session
->sampler_vs_changed
;
341 /* see gen6_draw_vs() */
342 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
343 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(SAMPLER_VS
) ||
344 r
->instruction_bo_changed
);
346 /* emit depth stall before any of the VS commands */
347 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
348 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
351 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
352 if (emit_3dstate_binding_table
) {
353 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r
->builder
,
354 r
->state
.vs
.BINDING_TABLE_STATE
);
357 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
358 if (emit_3dstate_sampler_state
) {
359 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r
->builder
,
360 r
->state
.vs
.SAMPLER_STATE
);
363 /* 3DSTATE_CONSTANT_VS */
364 if (emit_3dstate_constant_vs
) {
365 gen7_3DSTATE_CONSTANT_VS(r
->builder
,
366 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
367 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
372 if (emit_3dstate_vs
) {
373 const int num_samplers
= vec
->sampler
[PIPE_SHADER_VERTEX
].count
;
375 gen6_3DSTATE_VS(r
->builder
, vec
->vs
, num_samplers
);
380 gen7_draw_hs(struct ilo_render
*r
,
381 const struct ilo_state_vector
*vec
,
382 struct gen6_draw_session
*session
)
384 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
385 if (r
->hw_ctx_changed
) {
386 gen7_3DSTATE_CONSTANT_HS(r
->builder
, 0, 0, 0);
387 gen7_3DSTATE_HS(r
->builder
, NULL
, 0);
390 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
391 if (r
->hw_ctx_changed
)
392 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r
->builder
, 0);
396 gen7_draw_te(struct ilo_render
*r
,
397 const struct ilo_state_vector
*vec
,
398 struct gen6_draw_session
*session
)
401 if (r
->hw_ctx_changed
)
402 gen7_3DSTATE_TE(r
->builder
);
406 gen7_draw_ds(struct ilo_render
*r
,
407 const struct ilo_state_vector
*vec
,
408 struct gen6_draw_session
*session
)
410 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
411 if (r
->hw_ctx_changed
) {
412 gen7_3DSTATE_CONSTANT_DS(r
->builder
, 0, 0, 0);
413 gen7_3DSTATE_DS(r
->builder
, NULL
, 0);
416 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
417 if (r
->hw_ctx_changed
)
418 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r
->builder
, 0);
423 gen7_draw_gs(struct ilo_render
*r
,
424 const struct ilo_state_vector
*vec
,
425 struct gen6_draw_session
*session
)
427 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
428 if (r
->hw_ctx_changed
) {
429 gen7_3DSTATE_CONSTANT_GS(r
->builder
, 0, 0, 0);
430 gen7_3DSTATE_GS(r
->builder
, NULL
, 0);
433 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
434 if (session
->binding_table_gs_changed
) {
435 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r
->builder
,
436 r
->state
.gs
.BINDING_TABLE_STATE
);
441 gen7_draw_sol(struct ilo_render
*r
,
442 const struct ilo_state_vector
*vec
,
443 struct gen6_draw_session
*session
)
445 const struct pipe_stream_output_info
*so_info
;
446 const struct ilo_shader_state
*shader
;
447 bool dirty_sh
= false;
451 dirty_sh
= DIRTY(GS
);
455 dirty_sh
= DIRTY(VS
);
458 so_info
= ilo_shader_get_kernel_so_info(shader
);
460 /* 3DSTATE_SO_BUFFER */
461 if ((DIRTY(SO
) || dirty_sh
|| r
->batch_bo_changed
) &&
465 for (i
= 0; i
< vec
->so
.count
; i
++) {
466 const int stride
= so_info
->stride
[i
] * 4; /* in bytes */
469 gen7_3DSTATE_SO_BUFFER(r
->builder
, i
, base
, stride
,
474 gen7_3DSTATE_SO_BUFFER(r
->builder
, i
, 0, 0, NULL
);
477 /* 3DSTATE_SO_DECL_LIST */
478 if (dirty_sh
&& vec
->so
.enabled
)
479 gen7_3DSTATE_SO_DECL_LIST(r
->builder
, so_info
);
481 /* 3DSTATE_STREAMOUT */
482 if (DIRTY(SO
) || DIRTY(RASTERIZER
) || dirty_sh
) {
483 const unsigned buffer_mask
= (1 << vec
->so
.count
) - 1;
484 const int output_count
= ilo_shader_get_kernel_param(shader
,
485 ILO_KERNEL_OUTPUT_COUNT
);
487 gen7_3DSTATE_STREAMOUT(r
->builder
, buffer_mask
, output_count
,
488 vec
->rasterizer
->state
.rasterizer_discard
);
493 gen7_draw_sf(struct ilo_render
*r
,
494 const struct ilo_state_vector
*vec
,
495 struct gen6_draw_session
*session
)
498 if (DIRTY(RASTERIZER
) || DIRTY(FS
))
499 gen7_3DSTATE_SBE(r
->builder
, vec
->rasterizer
, vec
->fs
);
502 if (DIRTY(RASTERIZER
) || DIRTY(FB
)) {
503 struct pipe_surface
*zs
= vec
->fb
.state
.zsbuf
;
505 gen7_wa_pre_3dstate_sf_depth_bias(r
);
506 gen7_3DSTATE_SF(r
->builder
, vec
->rasterizer
,
507 (zs
) ? zs
->format
: PIPE_FORMAT_NONE
);
512 gen7_draw_wm(struct ilo_render
*r
,
513 const struct ilo_state_vector
*vec
,
514 struct gen6_draw_session
*session
)
517 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) || DIRTY(RASTERIZER
)) {
518 const bool cc_may_kill
= (vec
->dsa
->dw_alpha
||
519 vec
->blend
->alpha_to_coverage
);
521 gen7_3DSTATE_WM(r
->builder
, vec
->fs
,
522 vec
->rasterizer
, cc_may_kill
, 0);
525 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
526 if (session
->binding_table_fs_changed
) {
527 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
528 r
->state
.wm
.BINDING_TABLE_STATE
);
531 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
532 if (session
->sampler_fs_changed
) {
533 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
534 r
->state
.wm
.SAMPLER_STATE
);
537 /* 3DSTATE_CONSTANT_PS */
538 if (session
->pcb_fs_changed
) {
539 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
540 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
541 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
546 if (DIRTY(FS
) || DIRTY(SAMPLER_FS
) || DIRTY(BLEND
) ||
547 r
->instruction_bo_changed
) {
548 const int num_samplers
= vec
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
549 const bool dual_blend
= vec
->blend
->dual_blend
;
551 if ((ilo_dev_gen(r
->dev
) == ILO_GEN(7) ||
552 ilo_dev_gen(r
->dev
) == ILO_GEN(7.5)) &&
554 gen7_wa_pre_3dstate_ps_max_threads(r
);
556 gen7_3DSTATE_PS(r
->builder
, vec
->fs
, num_samplers
, dual_blend
);
559 /* 3DSTATE_SCISSOR_STATE_POINTERS */
560 if (session
->scissor_changed
) {
561 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
562 r
->state
.SCISSOR_RECT
);
565 /* XXX what is the best way to know if this workaround is needed? */
567 const bool emit_3dstate_ps
=
568 (DIRTY(FS
) || DIRTY(SAMPLER_FS
) || DIRTY(BLEND
));
569 const bool emit_3dstate_depth_buffer
=
570 (DIRTY(FB
) || DIRTY(DSA
) || r
->state_bo_changed
);
572 if (emit_3dstate_ps
||
573 session
->pcb_fs_changed
||
574 session
->viewport_changed
||
575 session
->binding_table_fs_changed
||
576 session
->sampler_fs_changed
||
577 session
->cc_changed
||
578 session
->blend_changed
||
579 session
->dsa_changed
)
580 gen7_wa_post_ps_and_later(r
);
582 if (emit_3dstate_depth_buffer
)
583 gen7_wa_pre_depth(r
);
586 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
587 if (DIRTY(FB
) || r
->batch_bo_changed
) {
588 const struct ilo_zs_surface
*zs
;
589 uint32_t clear_params
;
591 if (vec
->fb
.state
.zsbuf
) {
592 const struct ilo_surface_cso
*surface
=
593 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
594 const struct ilo_texture_slice
*slice
=
595 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
596 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
598 assert(!surface
->is_rt
);
600 clear_params
= slice
->clear_value
;
603 zs
= &vec
->fb
.null_zs
;
607 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
608 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
609 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
610 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
615 gen7_draw_wm_multisample(struct ilo_render
*r
,
616 const struct ilo_state_vector
*vec
,
617 struct gen6_draw_session
*session
)
619 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
620 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
621 const uint32_t *packed_sample_pos
;
623 gen7_wa_pre_3dstate_multisample(r
);
626 (vec
->fb
.num_samples
> 4) ? r
->packed_sample_position_8x
:
627 (vec
->fb
.num_samples
> 1) ? &r
->packed_sample_position_4x
:
628 &r
->packed_sample_position_1x
;
630 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
631 vec
->fb
.num_samples
, packed_sample_pos
,
632 vec
->rasterizer
->state
.half_pixel_center
);
634 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
635 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1,
636 vec
->fb
.num_samples
);
641 gen7_draw_vf_draw(struct ilo_render
*r
,
642 const struct ilo_state_vector
*vec
,
643 struct gen6_draw_session
*session
)
645 if (r
->state
.deferred_pipe_control_dw1
)
646 gen7_pipe_control(r
, r
->state
.deferred_pipe_control_dw1
);
649 gen7_3DPRIMITIVE(r
->builder
, vec
->draw
, &vec
->ib
);
651 r
->state
.current_pipe_control_dw1
= 0;
652 r
->state
.deferred_pipe_control_dw1
= 0;
656 gen7_draw_commands(struct ilo_render
*render
,
657 const struct ilo_state_vector
*vec
,
658 struct gen6_draw_session
*session
)
661 * We try to keep the order of the commands match, as closely as possible,
662 * that of the classic i965 driver. It allows us to compare the command
665 gen6_draw_common_select(render
, vec
, session
);
666 gen6_draw_common_sip(render
, vec
, session
);
667 gen6_draw_vf_statistics(render
, vec
, session
);
668 gen7_draw_common_pcb_alloc(render
, vec
, session
);
669 gen6_draw_common_base_address(render
, vec
, session
);
670 gen7_draw_common_pointers_1(render
, vec
, session
);
671 gen7_draw_common_urb(render
, vec
, session
);
672 gen7_draw_common_pointers_2(render
, vec
, session
);
673 gen7_draw_wm_multisample(render
, vec
, session
);
674 gen7_draw_gs(render
, vec
, session
);
675 gen7_draw_hs(render
, vec
, session
);
676 gen7_draw_te(render
, vec
, session
);
677 gen7_draw_ds(render
, vec
, session
);
678 gen7_draw_vs(render
, vec
, session
);
679 gen7_draw_sol(render
, vec
, session
);
680 gen6_draw_clip(render
, vec
, session
);
681 gen7_draw_sf(render
, vec
, session
);
682 gen7_draw_wm(render
, vec
, session
);
683 gen6_draw_wm_raster(render
, vec
, session
);
684 gen6_draw_sf_rect(render
, vec
, session
);
685 gen6_draw_vf(render
, vec
, session
);
686 gen7_draw_vf_draw(render
, vec
, session
);
690 ilo_render_emit_draw_gen7(struct ilo_render
*render
,
691 const struct ilo_state_vector
*vec
)
693 struct gen6_draw_session session
;
695 gen6_draw_prepare(render
, vec
, &session
);
697 session
.emit_draw_commands
= gen7_draw_commands
;
699 gen6_draw_emit(render
, vec
, &session
);
700 gen6_draw_end(render
, vec
, &session
);
704 gen7_rectlist_pcb_alloc(struct ilo_render
*r
,
705 const struct ilo_blitter
*blitter
)
708 * Push constant buffers are only allowed to take up at most the first
709 * 16KB of the URB. Split the space evenly for VS and FS.
712 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ? 32768 : 16384;
713 const int size
= max_size
/ 2;
716 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
719 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
721 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
725 gen7_rectlist_urb(struct ilo_render
*r
,
726 const struct ilo_blitter
*blitter
)
728 /* the first 16KB are reserved for VS and PS PCBs */
730 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ? 32768 : 16384;
732 gen7_3DSTATE_URB_VS(r
->builder
, offset
, r
->dev
->urb_size
- offset
,
733 blitter
->ve
.count
* 4 * sizeof(float));
735 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
736 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
737 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
741 gen7_rectlist_vs_to_sf(struct ilo_render
*r
,
742 const struct ilo_blitter
*blitter
)
744 gen7_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
745 gen6_3DSTATE_VS(r
->builder
, NULL
, 0);
747 gen7_3DSTATE_CONSTANT_HS(r
->builder
, NULL
, NULL
, 0);
748 gen7_3DSTATE_HS(r
->builder
, NULL
, 0);
750 gen7_3DSTATE_TE(r
->builder
);
752 gen7_3DSTATE_CONSTANT_DS(r
->builder
, NULL
, NULL
, 0);
753 gen7_3DSTATE_DS(r
->builder
, NULL
, 0);
755 gen7_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
756 gen7_3DSTATE_GS(r
->builder
, NULL
, 0);
758 gen7_3DSTATE_STREAMOUT(r
->builder
, 0x0, 0, false);
760 gen6_3DSTATE_CLIP(r
->builder
, NULL
, NULL
, false, 0);
762 gen7_wa_pre_3dstate_sf_depth_bias(r
);
764 gen7_3DSTATE_SF(r
->builder
, NULL
, blitter
->fb
.dst
.base
.format
);
765 gen7_3DSTATE_SBE(r
->builder
, NULL
, NULL
);
769 gen7_rectlist_wm(struct ilo_render
*r
,
770 const struct ilo_blitter
*blitter
)
774 switch (blitter
->op
) {
775 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
776 hiz_op
= GEN7_WM_DW1_DEPTH_CLEAR
;
778 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
779 hiz_op
= GEN7_WM_DW1_DEPTH_RESOLVE
;
781 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
782 hiz_op
= GEN7_WM_DW1_HIZ_RESOLVE
;
789 gen7_3DSTATE_WM(r
->builder
, NULL
, NULL
, false, hiz_op
);
791 gen7_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
793 gen7_wa_pre_3dstate_ps_max_threads(r
);
794 gen7_3DSTATE_PS(r
->builder
, NULL
, 0, false);
798 gen7_rectlist_wm_depth(struct ilo_render
*r
,
799 const struct ilo_blitter
*blitter
)
801 gen7_wa_pre_depth(r
);
803 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
804 ILO_BLITTER_USE_FB_STENCIL
)) {
805 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
806 &blitter
->fb
.dst
.u
.zs
);
809 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
810 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
811 &blitter
->fb
.dst
.u
.zs
);
814 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
815 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
816 &blitter
->fb
.dst
.u
.zs
);
819 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
820 blitter
->depth_clear_value
);
824 gen7_rectlist_wm_multisample(struct ilo_render
*r
,
825 const struct ilo_blitter
*blitter
)
827 const uint32_t *packed_sample_pos
=
828 (blitter
->fb
.num_samples
> 4) ? r
->packed_sample_position_8x
:
829 (blitter
->fb
.num_samples
> 1) ? &r
->packed_sample_position_4x
:
830 &r
->packed_sample_position_1x
;
832 gen7_wa_pre_3dstate_multisample(r
);
834 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
835 packed_sample_pos
, true);
837 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
838 (1 << blitter
->fb
.num_samples
) - 1, blitter
->fb
.num_samples
);
842 gen7_rectlist_commands(struct ilo_render
*r
,
843 const struct ilo_blitter
*blitter
)
845 gen7_rectlist_wm_multisample(r
, blitter
);
847 gen6_state_base_address(r
->builder
, true);
849 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
,
850 &blitter
->ve
, &blitter
->vb
);
852 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
,
853 &blitter
->ve
, false, false);
855 gen7_rectlist_pcb_alloc(r
, blitter
);
857 /* needed for any VS-related commands */
860 gen7_rectlist_urb(r
, blitter
);
862 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
863 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
864 r
->state
.DEPTH_STENCIL_STATE
);
867 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
868 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
869 r
->state
.COLOR_CALC_STATE
);
872 gen7_rectlist_vs_to_sf(r
, blitter
);
873 gen7_rectlist_wm(r
, blitter
);
875 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
876 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
877 r
->state
.CC_VIEWPORT
);
880 gen7_rectlist_wm_depth(r
, blitter
);
882 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
883 blitter
->fb
.width
, blitter
->fb
.height
);
885 gen7_3DPRIMITIVE(r
->builder
, &blitter
->draw
, NULL
);
889 ilo_render_emit_rectlist_gen7(struct ilo_render
*render
,
890 const struct ilo_blitter
*blitter
)
892 ilo_render_emit_rectlist_dynamic_states(render
, blitter
);
893 gen7_rectlist_commands(render
, blitter
);
897 gen7_render_max_command_size(const struct ilo_render
*render
)
902 size
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
903 size
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
904 size
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
905 size
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
906 size
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
907 size
+= GEN6_PIPE_CONTROL__SIZE
* 5;
910 GEN6_STATE_BASE_ADDRESS__SIZE
+
911 GEN6_STATE_SIP__SIZE
+
912 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
913 GEN6_PIPELINE_SELECT__SIZE
+
914 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
915 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
916 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
917 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
918 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
919 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
920 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
921 GEN75_3DSTATE_VF__SIZE
+
922 GEN6_3DSTATE_VS__SIZE
+
923 GEN6_3DSTATE_GS__SIZE
+
924 GEN6_3DSTATE_CLIP__SIZE
+
925 GEN6_3DSTATE_SF__SIZE
+
926 GEN6_3DSTATE_WM__SIZE
+
927 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
928 GEN7_3DSTATE_HS__SIZE
+
929 GEN7_3DSTATE_TE__SIZE
+
930 GEN7_3DSTATE_DS__SIZE
+
931 GEN7_3DSTATE_STREAMOUT__SIZE
+
932 GEN7_3DSTATE_SBE__SIZE
+
933 GEN7_3DSTATE_PS__SIZE
+
934 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
935 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
936 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
937 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
938 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
939 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
940 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
941 GEN6_3DPRIMITIVE__SIZE
;
948 ilo_render_estimate_size_gen7(struct ilo_render
*render
,
949 enum ilo_render_action action
,
955 case ILO_RENDER_DRAW
:
957 const struct ilo_state_vector
*vec
= arg
;
959 size
= gen7_render_max_command_size(render
) +
960 ilo_render_get_draw_dynamic_states_len(render
, vec
) +
961 ilo_render_get_draw_surface_states_len(render
, vec
);
964 case ILO_RENDER_RECTLIST
:
966 const struct ilo_blitter
*blitter
= arg
;
968 size
= ilo_render_get_rectlist_dynamic_states_len(render
, blitter
);
969 size
+= 256; /* commands */
973 assert(!"unknown render action");
982 ilo_render_init_gen7(struct ilo_render
*render
)
984 render
->estimate_size
= ilo_render_estimate_size_gen7
;
985 render
->emit_draw
= ilo_render_emit_draw_gen7
;
986 render
->emit_rectlist
= ilo_render_emit_rectlist_gen7
;