2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
31 #include "ilo_blitter.h"
32 #include "ilo_builder_3d.h"
33 #include "ilo_builder_render.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
39 gen7_3dprimitive(struct ilo_render
*r
,
40 const struct pipe_draw_info
*info
,
41 const struct ilo_ib_state
*ib
)
43 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
45 if (r
->state
.deferred_pipe_control_dw1
)
46 ilo_render_pipe_control(r
, r
->state
.deferred_pipe_control_dw1
);
49 gen7_3DPRIMITIVE(r
->builder
, info
, ib
);
51 r
->state
.current_pipe_control_dw1
= 0;
52 r
->state
.deferred_pipe_control_dw1
= 0;
56 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render
*r
)
59 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
61 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
62 * in the ring after this instruction
63 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
65 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
67 ILO_DEV_ASSERT(r
->dev
, 7, 7);
69 r
->state
.deferred_pipe_control_dw1
|= dw1
;
73 gen7_wa_pre_vs(struct ilo_render
*r
)
76 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
78 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
79 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
80 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
81 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
82 * needs to be sent before any combination of VS associated 3DSTATE."
84 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
85 GEN6_PIPE_CONTROL_WRITE_IMM
;
87 ILO_DEV_ASSERT(r
->dev
, 7, 7);
89 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
90 ilo_render_pipe_control(r
, dw1
);
94 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render
*r
)
97 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
99 * "Due to an HW issue driver needs to send a pipe control with stall
100 * when ever there is state change in depth bias related state (in
103 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
105 ILO_DEV_ASSERT(r
->dev
, 7, 7);
107 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
108 ilo_render_pipe_control(r
, dw1
);
112 gen7_wa_pre_3dstate_multisample(struct ilo_render
*r
)
115 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
117 * "Driver must ierarchi that all the caches in the depth pipe are
118 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
119 * requires driver to send a PIPE_CONTROL with a CS stall along with a
120 * Depth Flush prior to this command.
122 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
123 GEN6_PIPE_CONTROL_CS_STALL
;
125 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
127 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
128 ilo_render_pipe_control(r
, dw1
);
132 gen7_wa_pre_depth(struct ilo_render
*r
)
134 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
136 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
138 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
140 * "Driver must send a least one PIPE_CONTROL command with CS Stall
141 * and a post sync operation prior to the group of depth
142 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
143 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
145 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
|
146 GEN6_PIPE_CONTROL_WRITE_IMM
;
148 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
149 ilo_render_pipe_control(r
, dw1
);
153 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
155 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
156 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
157 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
158 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
159 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
160 * Depth Flush Bit set, followed by another pipelined depth stall
161 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
162 * guarantee that the pipeline from WM onwards is already flushed
163 * (e.g., via a preceding MI_FLUSH)."
165 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
166 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
167 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
171 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render
*r
)
174 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
176 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
177 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
178 * Pixel Scoreboard set is required to be issued."
180 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
182 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
184 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
185 ilo_render_pipe_control(r
, dw1
);
189 gen7_wa_post_ps_and_later(struct ilo_render
*r
)
192 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
194 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
195 * Enable bit set after all the following states are programmed:
198 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
199 * - 3DSTATE_CONSTANT_PS
200 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
201 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
202 * - 3DSTATE_CC_STATE_POINTERS
203 * - 3DSTATE_BLEND_STATE_POINTERS
204 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
206 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
;
208 ILO_DEV_ASSERT(r
->dev
, 7, 7);
210 r
->state
.deferred_pipe_control_dw1
|= dw1
;
213 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
216 gen7_draw_common_urb(struct ilo_render
*r
,
217 const struct ilo_state_vector
*vec
,
218 struct ilo_render_draw_session
*session
)
220 /* 3DSTATE_URB_{VS,GS,HS,DS} */
221 if (DIRTY(VE
) || DIRTY(VS
)) {
222 /* the first 16KB are reserved for VS and PS PCBs */
224 (ilo_dev_gen(r
->dev
) >= ILO_GEN(8)) ||
225 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ?
227 int vs_entry_size
, vs_total_size
;
229 vs_entry_size
= (vec
->vs
) ?
230 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
233 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
235 * "Programming Restriction: As the VS URB entry serves as both the
236 * per-vertex input and output of the VS shader, the VS URB
237 * Allocation Size must be sized to the maximum of the vertex input
238 * and output structures."
240 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
241 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
243 vs_entry_size
*= sizeof(float) * 4;
244 vs_total_size
= r
->dev
->urb_size
- offset
;
246 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
249 gen7_3DSTATE_URB_VS(r
->builder
,
250 offset
, vs_total_size
, vs_entry_size
);
252 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
253 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
254 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
259 gen7_draw_common_pcb_alloc(struct ilo_render
*r
,
260 const struct ilo_state_vector
*vec
,
261 struct ilo_render_draw_session
*session
)
263 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
264 if (r
->hw_ctx_changed
) {
266 * Push constant buffers are only allowed to take up at most the first
267 * 16KB of the URB. Split the space evenly for VS and FS.
270 (ilo_dev_gen(r
->dev
) >= ILO_GEN(8)) ||
271 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ?
273 const int size
= max_size
/ 2;
276 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
279 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
281 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
282 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
287 gen7_draw_common_pointers_1(struct ilo_render
*r
,
288 const struct ilo_state_vector
*vec
,
289 struct ilo_render_draw_session
*session
)
291 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
292 if (session
->viewport_changed
) {
293 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
294 r
->state
.CC_VIEWPORT
);
296 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r
->builder
,
297 r
->state
.SF_CLIP_VIEWPORT
);
302 gen7_draw_common_pointers_2(struct ilo_render
*r
,
303 const struct ilo_state_vector
*vec
,
304 struct ilo_render_draw_session
*session
)
306 /* 3DSTATE_BLEND_STATE_POINTERS */
307 if (session
->blend_changed
) {
308 gen7_3DSTATE_BLEND_STATE_POINTERS(r
->builder
,
309 r
->state
.BLEND_STATE
);
312 /* 3DSTATE_CC_STATE_POINTERS */
313 if (session
->cc_changed
) {
314 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
315 r
->state
.COLOR_CALC_STATE
);
318 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
319 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8) && session
->dsa_changed
) {
320 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
321 r
->state
.DEPTH_STENCIL_STATE
);
326 gen7_draw_vs(struct ilo_render
*r
,
327 const struct ilo_state_vector
*vec
,
328 struct ilo_render_draw_session
*session
)
330 const bool emit_3dstate_binding_table
= session
->binding_table_vs_changed
;
331 const bool emit_3dstate_sampler_state
= session
->sampler_vs_changed
;
332 /* see gen6_draw_vs() */
333 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
334 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
336 /* emit depth stall before any of the VS commands */
337 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
338 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
339 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
343 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
344 if (emit_3dstate_binding_table
) {
345 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r
->builder
,
346 r
->state
.vs
.BINDING_TABLE_STATE
);
349 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
350 if (emit_3dstate_sampler_state
) {
351 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r
->builder
,
352 r
->state
.vs
.SAMPLER_STATE
);
355 /* 3DSTATE_CONSTANT_VS */
356 if (emit_3dstate_constant_vs
) {
357 gen7_3DSTATE_CONSTANT_VS(r
->builder
,
358 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
359 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
364 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8)) {
365 if (emit_3dstate_vs
|| DIRTY(RASTERIZER
)) {
366 gen8_3DSTATE_VS(r
->builder
, vec
->vs
,
367 vec
->rasterizer
->state
.clip_plane_enable
);
371 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
376 gen7_draw_hs(struct ilo_render
*r
,
377 const struct ilo_state_vector
*vec
,
378 struct ilo_render_draw_session
*session
)
380 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
381 if (r
->hw_ctx_changed
) {
382 gen7_3DSTATE_CONSTANT_HS(r
->builder
, 0, 0, 0);
383 gen7_disable_3DSTATE_HS(r
->builder
);
386 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
387 if (r
->hw_ctx_changed
)
388 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r
->builder
, 0);
392 gen7_draw_te(struct ilo_render
*r
,
393 const struct ilo_state_vector
*vec
,
394 struct ilo_render_draw_session
*session
)
397 if (r
->hw_ctx_changed
)
398 gen7_3DSTATE_TE(r
->builder
);
402 gen7_draw_ds(struct ilo_render
*r
,
403 const struct ilo_state_vector
*vec
,
404 struct ilo_render_draw_session
*session
)
406 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
407 if (r
->hw_ctx_changed
) {
408 gen7_3DSTATE_CONSTANT_DS(r
->builder
, 0, 0, 0);
409 gen7_disable_3DSTATE_DS(r
->builder
);
412 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
413 if (r
->hw_ctx_changed
)
414 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r
->builder
, 0);
419 gen7_draw_gs(struct ilo_render
*r
,
420 const struct ilo_state_vector
*vec
,
421 struct ilo_render_draw_session
*session
)
423 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
424 if (r
->hw_ctx_changed
) {
425 gen7_3DSTATE_CONSTANT_GS(r
->builder
, 0, 0, 0);
426 gen7_disable_3DSTATE_GS(r
->builder
);
429 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
430 if (session
->binding_table_gs_changed
) {
431 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r
->builder
,
432 r
->state
.gs
.BINDING_TABLE_STATE
);
437 gen7_draw_sol(struct ilo_render
*r
,
438 const struct ilo_state_vector
*vec
,
439 struct ilo_render_draw_session
*session
)
441 const struct pipe_stream_output_info
*so_info
;
442 const struct ilo_shader_state
*shader
;
443 bool dirty_sh
= false;
447 dirty_sh
= DIRTY(GS
);
451 dirty_sh
= DIRTY(VS
);
454 so_info
= ilo_shader_get_kernel_so_info(shader
);
456 /* 3DSTATE_SO_BUFFER */
457 if ((DIRTY(SO
) || dirty_sh
|| r
->batch_bo_changed
) &&
461 for (i
= 0; i
< vec
->so
.count
; i
++) {
462 const int stride
= so_info
->stride
[i
] * 4; /* in bytes */
464 gen7_3DSTATE_SO_BUFFER(r
->builder
, i
, stride
, vec
->so
.states
[i
]);
468 gen7_disable_3DSTATE_SO_BUFFER(r
->builder
, i
);
471 /* 3DSTATE_SO_DECL_LIST */
472 if (dirty_sh
&& vec
->so
.enabled
)
473 gen7_3DSTATE_SO_DECL_LIST(r
->builder
, so_info
);
475 /* 3DSTATE_STREAMOUT */
476 if (DIRTY(SO
) || DIRTY(RASTERIZER
) || dirty_sh
) {
477 const int output_count
= ilo_shader_get_kernel_param(shader
,
478 ILO_KERNEL_OUTPUT_COUNT
);
479 int buf_strides
[4] = { 0, 0, 0, 0 };
482 for (i
= 0; i
< vec
->so
.count
; i
++)
483 buf_strides
[i
] = so_info
->stride
[i
] * 4;
485 gen7_3DSTATE_STREAMOUT(r
->builder
, 0,
486 vec
->rasterizer
->state
.rasterizer_discard
,
487 output_count
, buf_strides
);
492 gen7_draw_sf(struct ilo_render
*r
,
493 const struct ilo_state_vector
*vec
,
494 struct ilo_render_draw_session
*session
)
497 if (DIRTY(RASTERIZER
) || DIRTY(FS
)) {
498 gen7_3DSTATE_SBE(r
->builder
, vec
->fs
, (vec
->rasterizer
) ?
499 vec
->rasterizer
->state
.sprite_coord_mode
: 0);
503 if (DIRTY(RASTERIZER
) || DIRTY(FB
)) {
504 struct pipe_surface
*zs
= vec
->fb
.state
.zsbuf
;
506 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
507 gen7_wa_pre_3dstate_sf_depth_bias(r
);
509 gen7_3DSTATE_SF(r
->builder
,
510 (vec
->rasterizer
) ? &vec
->rasterizer
->sf
: NULL
,
511 (zs
) ? zs
->format
: PIPE_FORMAT_NONE
,
512 vec
->fb
.num_samples
);
517 gen7_draw_wm(struct ilo_render
*r
,
518 const struct ilo_state_vector
*vec
,
519 struct ilo_render_draw_session
*session
)
522 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) || DIRTY(RASTERIZER
)) {
523 const bool cc_may_kill
= (vec
->dsa
->dw_blend_alpha
||
524 vec
->blend
->alpha_to_coverage
);
526 gen7_3DSTATE_WM(r
->builder
, vec
->fs
, vec
->rasterizer
, cc_may_kill
);
529 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
530 if (session
->binding_table_fs_changed
) {
531 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
532 r
->state
.wm
.BINDING_TABLE_STATE
);
535 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
536 if (session
->sampler_fs_changed
) {
537 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
538 r
->state
.wm
.SAMPLER_STATE
);
541 /* 3DSTATE_CONSTANT_PS */
542 if (session
->pcb_fs_changed
) {
543 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
544 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
545 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
550 if (DIRTY(FS
) || DIRTY(BLEND
) || r
->instruction_bo_changed
) {
551 const bool dual_blend
= vec
->blend
->dual_blend
;
553 if (r
->hw_ctx_changed
)
554 gen7_wa_pre_3dstate_ps_max_threads(r
);
556 gen7_3DSTATE_PS(r
->builder
, vec
->fs
, dual_blend
);
559 /* 3DSTATE_SCISSOR_STATE_POINTERS */
560 if (session
->scissor_changed
) {
561 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
562 r
->state
.SCISSOR_RECT
);
566 const bool emit_3dstate_ps
= (DIRTY(FS
) || DIRTY(BLEND
));
567 const bool emit_3dstate_depth_buffer
=
568 (DIRTY(FB
) || DIRTY(DSA
) || r
->state_bo_changed
);
570 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7)) {
571 /* XXX what is the best way to know if this workaround is needed? */
572 if (emit_3dstate_ps
||
573 session
->pcb_fs_changed
||
574 session
->viewport_changed
||
575 session
->binding_table_fs_changed
||
576 session
->sampler_fs_changed
||
577 session
->cc_changed
||
578 session
->blend_changed
||
579 session
->dsa_changed
)
580 gen7_wa_post_ps_and_later(r
);
583 if (emit_3dstate_depth_buffer
)
584 gen7_wa_pre_depth(r
);
587 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
588 if (DIRTY(FB
) || r
->batch_bo_changed
) {
589 const struct ilo_zs_surface
*zs
;
590 uint32_t clear_params
;
592 if (vec
->fb
.state
.zsbuf
) {
593 const struct ilo_surface_cso
*surface
=
594 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
595 const struct ilo_texture_slice
*slice
=
596 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
597 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
599 assert(!surface
->is_rt
);
601 clear_params
= slice
->clear_value
;
604 zs
= &vec
->fb
.null_zs
;
608 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
, false);
609 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
610 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
611 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
616 gen7_draw_wm_multisample(struct ilo_render
*r
,
617 const struct ilo_state_vector
*vec
,
618 struct ilo_render_draw_session
*session
)
620 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
621 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
622 const uint32_t *pattern
;
624 gen7_wa_pre_3dstate_multisample(r
);
626 pattern
= (vec
->fb
.num_samples
> 4) ? r
->sample_pattern_8x
:
627 (vec
->fb
.num_samples
> 1) ? &r
->sample_pattern_4x
:
628 &r
->sample_pattern_1x
;
630 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
631 vec
->fb
.num_samples
, pattern
,
632 vec
->rasterizer
->state
.half_pixel_center
);
634 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
635 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1,
636 vec
->fb
.num_samples
);
641 ilo_render_emit_draw_commands_gen7(struct ilo_render
*render
,
642 const struct ilo_state_vector
*vec
,
643 struct ilo_render_draw_session
*session
)
645 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
648 * We try to keep the order of the commands match, as closely as possible,
649 * that of the classic i965 driver. It allows us to compare the command
652 gen6_draw_common_select(render
, vec
, session
);
653 gen6_draw_common_sip(render
, vec
, session
);
654 gen6_draw_vf_statistics(render
, vec
, session
);
655 gen7_draw_common_pcb_alloc(render
, vec
, session
);
656 gen6_draw_common_base_address(render
, vec
, session
);
657 gen7_draw_common_pointers_1(render
, vec
, session
);
658 gen7_draw_common_urb(render
, vec
, session
);
659 gen7_draw_common_pointers_2(render
, vec
, session
);
660 gen7_draw_wm_multisample(render
, vec
, session
);
661 gen7_draw_gs(render
, vec
, session
);
662 gen7_draw_hs(render
, vec
, session
);
663 gen7_draw_te(render
, vec
, session
);
664 gen7_draw_ds(render
, vec
, session
);
665 gen7_draw_vs(render
, vec
, session
);
666 gen7_draw_sol(render
, vec
, session
);
667 gen6_draw_clip(render
, vec
, session
);
668 gen7_draw_sf(render
, vec
, session
);
669 gen7_draw_wm(render
, vec
, session
);
670 gen6_draw_wm_raster(render
, vec
, session
);
671 gen6_draw_sf_rect(render
, vec
, session
);
672 gen6_draw_vf(render
, vec
, session
);
674 gen7_3dprimitive(render
, vec
->draw
, &vec
->ib
);
678 gen7_rectlist_pcb_alloc(struct ilo_render
*r
,
679 const struct ilo_blitter
*blitter
)
682 * Push constant buffers are only allowed to take up at most the first
683 * 16KB of the URB. Split the space evenly for VS and FS.
686 (ilo_dev_gen(r
->dev
) >= ILO_GEN(8)) ||
687 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ?
689 const int size
= max_size
/ 2;
692 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
695 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
697 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
698 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
702 gen7_rectlist_urb(struct ilo_render
*r
,
703 const struct ilo_blitter
*blitter
)
705 /* the first 16KB are reserved for VS and PS PCBs */
707 (ilo_dev_gen(r
->dev
) >= ILO_GEN(8)) ||
708 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ?
711 gen7_3DSTATE_URB_VS(r
->builder
, offset
, r
->dev
->urb_size
- offset
,
712 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) *
715 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
716 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
717 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
721 gen7_rectlist_vs_to_sf(struct ilo_render
*r
,
722 const struct ilo_blitter
*blitter
)
724 gen7_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
725 gen6_disable_3DSTATE_VS(r
->builder
);
727 gen7_3DSTATE_CONSTANT_HS(r
->builder
, NULL
, NULL
, 0);
728 gen7_disable_3DSTATE_HS(r
->builder
);
730 gen7_3DSTATE_TE(r
->builder
);
732 gen7_3DSTATE_CONSTANT_DS(r
->builder
, NULL
, NULL
, 0);
733 gen7_disable_3DSTATE_DS(r
->builder
);
735 gen7_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
736 gen7_disable_3DSTATE_GS(r
->builder
);
738 gen7_3DSTATE_STREAMOUT(r
->builder
, 0, false, 0x0, 0);
740 gen6_disable_3DSTATE_CLIP(r
->builder
);
742 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
743 gen7_wa_pre_3dstate_sf_depth_bias(r
);
745 gen7_3DSTATE_SF(r
->builder
, NULL
, blitter
->fb
.dst
.base
.format
,
746 blitter
->fb
.num_samples
);
747 gen7_3DSTATE_SBE(r
->builder
, NULL
, 0);
751 gen7_rectlist_wm(struct ilo_render
*r
,
752 const struct ilo_blitter
*blitter
)
756 switch (blitter
->op
) {
757 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
758 hiz_op
= GEN7_WM_DW1_DEPTH_CLEAR
;
760 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
761 hiz_op
= GEN7_WM_DW1_DEPTH_RESOLVE
;
763 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
764 hiz_op
= GEN7_WM_DW1_HIZ_RESOLVE
;
771 gen7_hiz_3DSTATE_WM(r
->builder
, hiz_op
);
773 gen7_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
775 gen7_wa_pre_3dstate_ps_max_threads(r
);
776 gen7_disable_3DSTATE_PS(r
->builder
);
780 gen7_rectlist_wm_depth(struct ilo_render
*r
,
781 const struct ilo_blitter
*blitter
)
783 gen7_wa_pre_depth(r
);
785 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
786 ILO_BLITTER_USE_FB_STENCIL
)) {
787 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
788 &blitter
->fb
.dst
.u
.zs
, true);
791 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
792 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
793 &blitter
->fb
.dst
.u
.zs
);
796 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
797 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
798 &blitter
->fb
.dst
.u
.zs
);
801 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
802 blitter
->depth_clear_value
);
806 gen7_rectlist_wm_multisample(struct ilo_render
*r
,
807 const struct ilo_blitter
*blitter
)
809 const uint32_t *pattern
=
810 (blitter
->fb
.num_samples
> 4) ? r
->sample_pattern_8x
:
811 (blitter
->fb
.num_samples
> 1) ? &r
->sample_pattern_4x
:
812 &r
->sample_pattern_1x
;
814 gen7_wa_pre_3dstate_multisample(r
);
816 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
819 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
820 (1 << blitter
->fb
.num_samples
) - 1, blitter
->fb
.num_samples
);
824 ilo_render_emit_rectlist_commands_gen7(struct ilo_render
*r
,
825 const struct ilo_blitter
*blitter
,
826 const struct ilo_render_rectlist_session
*session
)
828 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
830 gen7_rectlist_wm_multisample(r
, blitter
);
832 gen6_state_base_address(r
->builder
, true);
834 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
835 session
->vb_start
, session
->vb_end
,
836 sizeof(blitter
->vertices
[0]));
838 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
840 gen7_rectlist_pcb_alloc(r
, blitter
);
842 /* needed for any VS-related commands */
843 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
846 gen7_rectlist_urb(r
, blitter
);
848 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
849 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
850 r
->state
.DEPTH_STENCIL_STATE
);
853 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
854 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
855 r
->state
.COLOR_CALC_STATE
);
858 gen7_rectlist_vs_to_sf(r
, blitter
);
859 gen7_rectlist_wm(r
, blitter
);
861 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
862 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
863 r
->state
.CC_VIEWPORT
);
866 gen7_rectlist_wm_depth(r
, blitter
);
868 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
869 blitter
->fb
.width
, blitter
->fb
.height
);
871 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
872 gen7_wa_post_ps_and_later(r
);
874 gen7_3dprimitive(r
, &blitter
->draw
, NULL
);
878 ilo_render_get_draw_commands_len_gen7(const struct ilo_render
*render
,
879 const struct ilo_state_vector
*vec
)
883 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
886 len
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
887 len
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
888 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
889 len
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
890 len
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
891 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
894 GEN6_STATE_BASE_ADDRESS__SIZE
+
895 GEN6_STATE_SIP__SIZE
+
896 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
897 GEN6_PIPELINE_SELECT__SIZE
+
898 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
899 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
900 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
901 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
902 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
903 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
904 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
905 GEN75_3DSTATE_VF__SIZE
+
906 GEN6_3DSTATE_VS__SIZE
+
907 GEN6_3DSTATE_GS__SIZE
+
908 GEN6_3DSTATE_CLIP__SIZE
+
909 GEN6_3DSTATE_SF__SIZE
+
910 GEN6_3DSTATE_WM__SIZE
+
911 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
912 GEN7_3DSTATE_HS__SIZE
+
913 GEN7_3DSTATE_TE__SIZE
+
914 GEN7_3DSTATE_DS__SIZE
+
915 GEN7_3DSTATE_STREAMOUT__SIZE
+
916 GEN7_3DSTATE_SBE__SIZE
+
917 GEN7_3DSTATE_PS__SIZE
+
918 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
919 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
920 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
921 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
922 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
923 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
924 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
925 GEN6_3DPRIMITIVE__SIZE
;