2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
31 #include "ilo_blitter.h"
32 #include "ilo_builder_3d.h"
33 #include "ilo_builder_render.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
39 * A wrapper for gen6_PIPE_CONTROL().
42 gen7_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
44 struct intel_bo
*bo
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) ?
45 r
->workaround_bo
: NULL
;
47 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
49 if (dw1
& GEN6_PIPE_CONTROL_CS_STALL
) {
50 /* CS stall cannot be set alone */
51 const uint32_t mask
= GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
|
52 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
53 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
|
54 GEN6_PIPE_CONTROL_DEPTH_STALL
|
55 GEN6_PIPE_CONTROL_WRITE__MASK
;
57 dw1
|= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
60 gen6_PIPE_CONTROL(r
->builder
, dw1
, bo
, 0, 0);
63 r
->state
.current_pipe_control_dw1
|= dw1
;
64 r
->state
.deferred_pipe_control_dw1
&= ~dw1
;
68 gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render
*r
)
71 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
73 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
74 * in the ring after this instruction
75 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
77 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
79 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
81 r
->state
.deferred_pipe_control_dw1
|= dw1
;
85 gen7_wa_pre_vs(struct ilo_render
*r
)
88 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
90 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
91 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
92 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
93 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
94 * needs to be sent before any combination of VS associated 3DSTATE."
96 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
97 GEN6_PIPE_CONTROL_WRITE_IMM
;
99 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
101 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
102 gen7_pipe_control(r
, dw1
);
106 gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render
*r
)
109 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
111 * "Due to an HW issue driver needs to send a pipe control with stall
112 * when ever there is state change in depth bias related state (in
115 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
117 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
119 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
120 gen7_pipe_control(r
, dw1
);
124 gen7_wa_pre_3dstate_multisample(struct ilo_render
*r
)
127 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
129 * "Driver must ierarchi that all the caches in the depth pipe are
130 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
131 * requires driver to send a PIPE_CONTROL with a CS stall along with a
132 * Depth Flush prior to this command.
134 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
135 GEN6_PIPE_CONTROL_CS_STALL
;
137 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
139 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
140 gen7_pipe_control(r
, dw1
);
144 gen7_wa_pre_depth(struct ilo_render
*r
)
147 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
149 * "Driver must send a least one PIPE_CONTROL command with CS Stall and
150 * a post sync operation prior to the group of depth
151 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
152 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
154 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
|
155 GEN6_PIPE_CONTROL_WRITE_IMM
;
157 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
159 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
160 gen7_pipe_control(r
, dw1
);
163 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
165 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
166 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
167 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
168 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
169 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
170 * Depth Flush Bit set, followed by another pipelined depth stall
171 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
172 * guarantee that the pipeline from WM onwards is already flushed
173 * (e.g., via a preceding MI_FLUSH)."
175 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
176 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
177 gen7_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
181 gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render
*r
)
184 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
186 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
187 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
188 * Pixel Scoreboard set is required to be issued."
190 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
192 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
194 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
195 gen7_pipe_control(r
, dw1
);
199 gen7_wa_post_ps_and_later(struct ilo_render
*r
)
202 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
204 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
205 * Enable bit set after all the following states are programmed:
208 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
209 * - 3DSTATE_CONSTANT_PS
210 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
211 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
212 * - 3DSTATE_CC_STATE_POINTERS
213 * - 3DSTATE_BLEND_STATE_POINTERS
214 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
216 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
;
218 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
220 r
->state
.deferred_pipe_control_dw1
|= dw1
;
223 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
226 gen7_draw_common_urb(struct ilo_render
*r
,
227 const struct ilo_state_vector
*vec
,
228 struct ilo_render_draw_session
*session
)
230 /* 3DSTATE_URB_{VS,GS,HS,DS} */
231 if (DIRTY(VE
) || DIRTY(VS
)) {
232 /* the first 16KB are reserved for VS and PS PCBs */
233 const int offset
= (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) &&
234 r
->dev
->gt
== 3) ? 32768 : 16384;
235 int vs_entry_size
, vs_total_size
;
237 vs_entry_size
= (vec
->vs
) ?
238 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
241 * From the Ivy Bridge PRM, volume 2 part 1, page 35:
243 * "Programming Restriction: As the VS URB entry serves as both the
244 * per-vertex input and output of the VS shader, the VS URB
245 * Allocation Size must be sized to the maximum of the vertex input
246 * and output structures."
248 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
249 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
251 vs_entry_size
*= sizeof(float) * 4;
252 vs_total_size
= r
->dev
->urb_size
- offset
;
256 gen7_3DSTATE_URB_VS(r
->builder
,
257 offset
, vs_total_size
, vs_entry_size
);
259 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
260 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
261 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
266 gen7_draw_common_pcb_alloc(struct ilo_render
*r
,
267 const struct ilo_state_vector
*vec
,
268 struct ilo_render_draw_session
*session
)
270 /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
271 if (r
->hw_ctx_changed
) {
273 * Push constant buffers are only allowed to take up at most the first
274 * 16KB of the URB. Split the space evenly for VS and FS.
276 const int max_size
= (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) &&
277 r
->dev
->gt
== 3) ? 32768 : 16384;
278 const int size
= max_size
/ 2;
281 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
284 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
286 if (ilo_dev_gen(r
->dev
) == ILO_GEN(7))
287 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
292 gen7_draw_common_pointers_1(struct ilo_render
*r
,
293 const struct ilo_state_vector
*vec
,
294 struct ilo_render_draw_session
*session
)
296 /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
297 if (session
->viewport_changed
) {
298 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
299 r
->state
.CC_VIEWPORT
);
301 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r
->builder
,
302 r
->state
.SF_CLIP_VIEWPORT
);
307 gen7_draw_common_pointers_2(struct ilo_render
*r
,
308 const struct ilo_state_vector
*vec
,
309 struct ilo_render_draw_session
*session
)
311 /* 3DSTATE_BLEND_STATE_POINTERS */
312 if (session
->blend_changed
) {
313 gen7_3DSTATE_BLEND_STATE_POINTERS(r
->builder
,
314 r
->state
.BLEND_STATE
);
317 /* 3DSTATE_CC_STATE_POINTERS */
318 if (session
->cc_changed
) {
319 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
320 r
->state
.COLOR_CALC_STATE
);
323 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
324 if (session
->dsa_changed
) {
325 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
326 r
->state
.DEPTH_STENCIL_STATE
);
331 gen7_draw_vs(struct ilo_render
*r
,
332 const struct ilo_state_vector
*vec
,
333 struct ilo_render_draw_session
*session
)
335 const bool emit_3dstate_binding_table
=
336 session
->binding_table_vs_changed
;
337 const bool emit_3dstate_sampler_state
=
338 session
->sampler_vs_changed
;
339 /* see gen6_draw_vs() */
340 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
341 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
343 /* emit depth stall before any of the VS commands */
344 if (emit_3dstate_binding_table
|| emit_3dstate_sampler_state
||
345 emit_3dstate_constant_vs
|| emit_3dstate_vs
)
348 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
349 if (emit_3dstate_binding_table
) {
350 gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r
->builder
,
351 r
->state
.vs
.BINDING_TABLE_STATE
);
354 /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
355 if (emit_3dstate_sampler_state
) {
356 gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r
->builder
,
357 r
->state
.vs
.SAMPLER_STATE
);
360 /* 3DSTATE_CONSTANT_VS */
361 if (emit_3dstate_constant_vs
) {
362 gen7_3DSTATE_CONSTANT_VS(r
->builder
,
363 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
364 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
370 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
374 gen7_draw_hs(struct ilo_render
*r
,
375 const struct ilo_state_vector
*vec
,
376 struct ilo_render_draw_session
*session
)
378 /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
379 if (r
->hw_ctx_changed
) {
380 gen7_3DSTATE_CONSTANT_HS(r
->builder
, 0, 0, 0);
381 gen7_disable_3DSTATE_HS(r
->builder
);
384 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
385 if (r
->hw_ctx_changed
)
386 gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r
->builder
, 0);
390 gen7_draw_te(struct ilo_render
*r
,
391 const struct ilo_state_vector
*vec
,
392 struct ilo_render_draw_session
*session
)
395 if (r
->hw_ctx_changed
)
396 gen7_3DSTATE_TE(r
->builder
);
400 gen7_draw_ds(struct ilo_render
*r
,
401 const struct ilo_state_vector
*vec
,
402 struct ilo_render_draw_session
*session
)
404 /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
405 if (r
->hw_ctx_changed
) {
406 gen7_3DSTATE_CONSTANT_DS(r
->builder
, 0, 0, 0);
407 gen7_disable_3DSTATE_DS(r
->builder
);
410 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
411 if (r
->hw_ctx_changed
)
412 gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r
->builder
, 0);
417 gen7_draw_gs(struct ilo_render
*r
,
418 const struct ilo_state_vector
*vec
,
419 struct ilo_render_draw_session
*session
)
421 /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
422 if (r
->hw_ctx_changed
) {
423 gen7_3DSTATE_CONSTANT_GS(r
->builder
, 0, 0, 0);
424 gen7_disable_3DSTATE_GS(r
->builder
);
427 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
428 if (session
->binding_table_gs_changed
) {
429 gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r
->builder
,
430 r
->state
.gs
.BINDING_TABLE_STATE
);
435 gen7_draw_sol(struct ilo_render
*r
,
436 const struct ilo_state_vector
*vec
,
437 struct ilo_render_draw_session
*session
)
439 const struct pipe_stream_output_info
*so_info
;
440 const struct ilo_shader_state
*shader
;
441 bool dirty_sh
= false;
445 dirty_sh
= DIRTY(GS
);
449 dirty_sh
= DIRTY(VS
);
452 so_info
= ilo_shader_get_kernel_so_info(shader
);
454 /* 3DSTATE_SO_BUFFER */
455 if ((DIRTY(SO
) || dirty_sh
|| r
->batch_bo_changed
) &&
459 for (i
= 0; i
< vec
->so
.count
; i
++) {
460 const int stride
= so_info
->stride
[i
] * 4; /* in bytes */
462 gen7_3DSTATE_SO_BUFFER(r
->builder
, i
, stride
, vec
->so
.states
[i
]);
466 gen7_disable_3DSTATE_SO_BUFFER(r
->builder
, i
);
469 /* 3DSTATE_SO_DECL_LIST */
470 if (dirty_sh
&& vec
->so
.enabled
)
471 gen7_3DSTATE_SO_DECL_LIST(r
->builder
, so_info
);
473 /* 3DSTATE_STREAMOUT */
474 if (DIRTY(SO
) || DIRTY(RASTERIZER
) || dirty_sh
) {
475 const int output_count
= ilo_shader_get_kernel_param(shader
,
476 ILO_KERNEL_OUTPUT_COUNT
);
477 int buf_strides
[4] = { 0, 0, 0, 0 };
480 for (i
= 0; i
< vec
->so
.count
; i
++)
481 buf_strides
[i
] = so_info
->stride
[i
] * 4;
483 gen7_3DSTATE_STREAMOUT(r
->builder
, 0,
484 vec
->rasterizer
->state
.rasterizer_discard
,
485 output_count
, buf_strides
);
490 gen7_draw_sf(struct ilo_render
*r
,
491 const struct ilo_state_vector
*vec
,
492 struct ilo_render_draw_session
*session
)
495 if (DIRTY(RASTERIZER
) || DIRTY(FS
)) {
496 gen7_3DSTATE_SBE(r
->builder
, vec
->fs
, (vec
->rasterizer
) ?
497 vec
->rasterizer
->state
.sprite_coord_mode
: 0);
501 if (DIRTY(RASTERIZER
) || DIRTY(FB
)) {
502 struct pipe_surface
*zs
= vec
->fb
.state
.zsbuf
;
504 gen7_wa_pre_3dstate_sf_depth_bias(r
);
505 gen7_3DSTATE_SF(r
->builder
,
506 (vec
->rasterizer
) ? &vec
->rasterizer
->sf
: NULL
,
507 (zs
) ? zs
->format
: PIPE_FORMAT_NONE
,
508 vec
->fb
.num_samples
);
513 gen7_draw_wm(struct ilo_render
*r
,
514 const struct ilo_state_vector
*vec
,
515 struct ilo_render_draw_session
*session
)
518 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) || DIRTY(RASTERIZER
)) {
519 const bool cc_may_kill
= (vec
->dsa
->dw_alpha
||
520 vec
->blend
->alpha_to_coverage
);
522 gen7_3DSTATE_WM(r
->builder
, vec
->fs
, vec
->rasterizer
, cc_may_kill
);
525 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
526 if (session
->binding_table_fs_changed
) {
527 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
528 r
->state
.wm
.BINDING_TABLE_STATE
);
531 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
532 if (session
->sampler_fs_changed
) {
533 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
534 r
->state
.wm
.SAMPLER_STATE
);
537 /* 3DSTATE_CONSTANT_PS */
538 if (session
->pcb_fs_changed
) {
539 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
540 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
541 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
546 if (DIRTY(FS
) || DIRTY(BLEND
) || r
->instruction_bo_changed
) {
547 const bool dual_blend
= vec
->blend
->dual_blend
;
549 if ((ilo_dev_gen(r
->dev
) == ILO_GEN(7) ||
550 ilo_dev_gen(r
->dev
) == ILO_GEN(7.5)) &&
552 gen7_wa_pre_3dstate_ps_max_threads(r
);
554 gen7_3DSTATE_PS(r
->builder
, vec
->fs
, dual_blend
);
557 /* 3DSTATE_SCISSOR_STATE_POINTERS */
558 if (session
->scissor_changed
) {
559 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
560 r
->state
.SCISSOR_RECT
);
563 /* XXX what is the best way to know if this workaround is needed? */
565 const bool emit_3dstate_ps
= (DIRTY(FS
) || DIRTY(BLEND
));
566 const bool emit_3dstate_depth_buffer
=
567 (DIRTY(FB
) || DIRTY(DSA
) || r
->state_bo_changed
);
569 if (emit_3dstate_ps
||
570 session
->pcb_fs_changed
||
571 session
->viewport_changed
||
572 session
->binding_table_fs_changed
||
573 session
->sampler_fs_changed
||
574 session
->cc_changed
||
575 session
->blend_changed
||
576 session
->dsa_changed
)
577 gen7_wa_post_ps_and_later(r
);
579 if (emit_3dstate_depth_buffer
)
580 gen7_wa_pre_depth(r
);
583 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
584 if (DIRTY(FB
) || r
->batch_bo_changed
) {
585 const struct ilo_zs_surface
*zs
;
586 uint32_t clear_params
;
588 if (vec
->fb
.state
.zsbuf
) {
589 const struct ilo_surface_cso
*surface
=
590 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
591 const struct ilo_texture_slice
*slice
=
592 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
593 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
595 assert(!surface
->is_rt
);
597 clear_params
= slice
->clear_value
;
600 zs
= &vec
->fb
.null_zs
;
604 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
, false);
605 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
606 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
607 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
612 gen7_draw_wm_multisample(struct ilo_render
*r
,
613 const struct ilo_state_vector
*vec
,
614 struct ilo_render_draw_session
*session
)
616 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
617 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
618 const uint32_t *pattern
;
620 gen7_wa_pre_3dstate_multisample(r
);
622 pattern
= (vec
->fb
.num_samples
> 4) ? r
->sample_pattern_8x
:
623 (vec
->fb
.num_samples
> 1) ? &r
->sample_pattern_4x
:
624 &r
->sample_pattern_1x
;
626 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
627 vec
->fb
.num_samples
, pattern
,
628 vec
->rasterizer
->state
.half_pixel_center
);
630 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
631 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1,
632 vec
->fb
.num_samples
);
637 gen7_draw_vf_draw(struct ilo_render
*r
,
638 const struct ilo_state_vector
*vec
,
639 struct ilo_render_draw_session
*session
)
641 if (r
->state
.deferred_pipe_control_dw1
)
642 gen7_pipe_control(r
, r
->state
.deferred_pipe_control_dw1
);
645 gen7_3DPRIMITIVE(r
->builder
, vec
->draw
, &vec
->ib
);
647 r
->state
.current_pipe_control_dw1
= 0;
648 r
->state
.deferred_pipe_control_dw1
= 0;
652 ilo_render_emit_draw_commands_gen7(struct ilo_render
*render
,
653 const struct ilo_state_vector
*vec
,
654 struct ilo_render_draw_session
*session
)
656 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
659 * We try to keep the order of the commands match, as closely as possible,
660 * that of the classic i965 driver. It allows us to compare the command
663 gen6_draw_common_select(render
, vec
, session
);
664 gen6_draw_common_sip(render
, vec
, session
);
665 gen6_draw_vf_statistics(render
, vec
, session
);
666 gen7_draw_common_pcb_alloc(render
, vec
, session
);
667 gen6_draw_common_base_address(render
, vec
, session
);
668 gen7_draw_common_pointers_1(render
, vec
, session
);
669 gen7_draw_common_urb(render
, vec
, session
);
670 gen7_draw_common_pointers_2(render
, vec
, session
);
671 gen7_draw_wm_multisample(render
, vec
, session
);
672 gen7_draw_gs(render
, vec
, session
);
673 gen7_draw_hs(render
, vec
, session
);
674 gen7_draw_te(render
, vec
, session
);
675 gen7_draw_ds(render
, vec
, session
);
676 gen7_draw_vs(render
, vec
, session
);
677 gen7_draw_sol(render
, vec
, session
);
678 gen6_draw_clip(render
, vec
, session
);
679 gen7_draw_sf(render
, vec
, session
);
680 gen7_draw_wm(render
, vec
, session
);
681 gen6_draw_wm_raster(render
, vec
, session
);
682 gen6_draw_sf_rect(render
, vec
, session
);
683 gen6_draw_vf(render
, vec
, session
);
684 gen7_draw_vf_draw(render
, vec
, session
);
688 gen7_rectlist_pcb_alloc(struct ilo_render
*r
,
689 const struct ilo_blitter
*blitter
)
692 * Push constant buffers are only allowed to take up at most the first
693 * 16KB of the URB. Split the space evenly for VS and FS.
696 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ? 32768 : 16384;
697 const int size
= max_size
/ 2;
700 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r
->builder
, offset
, size
);
703 gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r
->builder
, offset
, size
);
705 gen7_wa_post_3dstate_push_constant_alloc_ps(r
);
709 gen7_rectlist_urb(struct ilo_render
*r
,
710 const struct ilo_blitter
*blitter
)
712 /* the first 16KB are reserved for VS and PS PCBs */
714 (ilo_dev_gen(r
->dev
) == ILO_GEN(7.5) && r
->dev
->gt
== 3) ? 32768 : 16384;
716 gen7_3DSTATE_URB_VS(r
->builder
, offset
, r
->dev
->urb_size
- offset
,
717 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) *
720 gen7_3DSTATE_URB_GS(r
->builder
, offset
, 0, 0);
721 gen7_3DSTATE_URB_HS(r
->builder
, offset
, 0, 0);
722 gen7_3DSTATE_URB_DS(r
->builder
, offset
, 0, 0);
726 gen7_rectlist_vs_to_sf(struct ilo_render
*r
,
727 const struct ilo_blitter
*blitter
)
729 gen7_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
730 gen6_disable_3DSTATE_VS(r
->builder
);
732 gen7_3DSTATE_CONSTANT_HS(r
->builder
, NULL
, NULL
, 0);
733 gen7_disable_3DSTATE_HS(r
->builder
);
735 gen7_3DSTATE_TE(r
->builder
);
737 gen7_3DSTATE_CONSTANT_DS(r
->builder
, NULL
, NULL
, 0);
738 gen7_disable_3DSTATE_DS(r
->builder
);
740 gen7_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
741 gen7_disable_3DSTATE_GS(r
->builder
);
743 gen7_3DSTATE_STREAMOUT(r
->builder
, 0, false, 0x0, 0);
745 gen6_disable_3DSTATE_CLIP(r
->builder
);
747 gen7_wa_pre_3dstate_sf_depth_bias(r
);
749 gen7_3DSTATE_SF(r
->builder
, NULL
, blitter
->fb
.dst
.base
.format
,
750 blitter
->fb
.num_samples
);
751 gen7_3DSTATE_SBE(r
->builder
, NULL
, 0);
755 gen7_rectlist_wm(struct ilo_render
*r
,
756 const struct ilo_blitter
*blitter
)
760 switch (blitter
->op
) {
761 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
762 hiz_op
= GEN7_WM_DW1_DEPTH_CLEAR
;
764 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
765 hiz_op
= GEN7_WM_DW1_DEPTH_RESOLVE
;
767 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
768 hiz_op
= GEN7_WM_DW1_HIZ_RESOLVE
;
775 gen7_hiz_3DSTATE_WM(r
->builder
, hiz_op
);
777 gen7_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
779 gen7_wa_pre_3dstate_ps_max_threads(r
);
780 gen7_disable_3DSTATE_PS(r
->builder
);
784 gen7_rectlist_wm_depth(struct ilo_render
*r
,
785 const struct ilo_blitter
*blitter
)
787 gen7_wa_pre_depth(r
);
789 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
790 ILO_BLITTER_USE_FB_STENCIL
)) {
791 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
792 &blitter
->fb
.dst
.u
.zs
, true);
795 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
796 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
797 &blitter
->fb
.dst
.u
.zs
);
800 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
801 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
802 &blitter
->fb
.dst
.u
.zs
);
805 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
806 blitter
->depth_clear_value
);
810 gen7_rectlist_wm_multisample(struct ilo_render
*r
,
811 const struct ilo_blitter
*blitter
)
813 const uint32_t *pattern
=
814 (blitter
->fb
.num_samples
> 4) ? r
->sample_pattern_8x
:
815 (blitter
->fb
.num_samples
> 1) ? &r
->sample_pattern_4x
:
816 &r
->sample_pattern_1x
;
818 gen7_wa_pre_3dstate_multisample(r
);
820 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
823 gen7_3DSTATE_SAMPLE_MASK(r
->builder
,
824 (1 << blitter
->fb
.num_samples
) - 1, blitter
->fb
.num_samples
);
828 ilo_render_emit_rectlist_commands_gen7(struct ilo_render
*r
,
829 const struct ilo_blitter
*blitter
,
830 const struct ilo_render_rectlist_session
*session
)
832 ILO_DEV_ASSERT(r
->dev
, 7, 7.5);
834 gen7_rectlist_wm_multisample(r
, blitter
);
836 gen6_state_base_address(r
->builder
, true);
838 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
839 session
->vb_start
, session
->vb_end
,
840 sizeof(blitter
->vertices
[0]));
842 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
844 gen7_rectlist_pcb_alloc(r
, blitter
);
846 /* needed for any VS-related commands */
849 gen7_rectlist_urb(r
, blitter
);
851 if (blitter
->uses
& ILO_BLITTER_USE_DSA
) {
852 gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r
->builder
,
853 r
->state
.DEPTH_STENCIL_STATE
);
856 if (blitter
->uses
& ILO_BLITTER_USE_CC
) {
857 gen7_3DSTATE_CC_STATE_POINTERS(r
->builder
,
858 r
->state
.COLOR_CALC_STATE
);
861 gen7_rectlist_vs_to_sf(r
, blitter
);
862 gen7_rectlist_wm(r
, blitter
);
864 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
865 gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r
->builder
,
866 r
->state
.CC_VIEWPORT
);
869 gen7_rectlist_wm_depth(r
, blitter
);
871 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
872 blitter
->fb
.width
, blitter
->fb
.height
);
874 gen7_3DPRIMITIVE(r
->builder
, &blitter
->draw
, NULL
);
878 ilo_render_get_draw_commands_len_gen7(const struct ilo_render
*render
,
879 const struct ilo_state_vector
*vec
)
883 ILO_DEV_ASSERT(render
->dev
, 7, 7.5);
886 len
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
887 len
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
888 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
889 len
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
890 len
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
891 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
894 GEN6_STATE_BASE_ADDRESS__SIZE
+
895 GEN6_STATE_SIP__SIZE
+
896 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
897 GEN6_PIPELINE_SELECT__SIZE
+
898 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
899 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
900 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
901 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
902 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
903 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
904 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
905 GEN75_3DSTATE_VF__SIZE
+
906 GEN6_3DSTATE_VS__SIZE
+
907 GEN6_3DSTATE_GS__SIZE
+
908 GEN6_3DSTATE_CLIP__SIZE
+
909 GEN6_3DSTATE_SF__SIZE
+
910 GEN6_3DSTATE_WM__SIZE
+
911 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
912 GEN7_3DSTATE_HS__SIZE
+
913 GEN7_3DSTATE_TE__SIZE
+
914 GEN7_3DSTATE_DS__SIZE
+
915 GEN7_3DSTATE_STREAMOUT__SIZE
+
916 GEN7_3DSTATE_SBE__SIZE
+
917 GEN7_3DSTATE_PS__SIZE
+
918 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
919 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
920 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
921 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
922 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
923 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
924 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
925 GEN6_3DPRIMITIVE__SIZE
;