src/gallium/drivers/ilo/ilo_render_gen8.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "core/ilo_builder_3d.h"
  30 #include "core/ilo_builder_render.h"
  31
  32 #include "ilo_blitter.h"
  33 #include "ilo_shader.h"
  34 #include "ilo_state.h"
  35 #include "ilo_render_gen.h"
  36
  37 static void
  38 gen8_wa_pre_depth(struct ilo_render *r)
  39 {
  40    ILO_DEV_ASSERT(r->dev, 8, 8);
  41
  42    /*
  43     * From the Ivy Bridge PRM, volume 2 part 1, page 315:
  44     *
  45     *     "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
  46     *      any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
  47     *      3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
  48     *      issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
  49     *      set), followed by a pipelined depth cache flush (PIPE_CONTROL with
  50     *      Depth Flush Bit set, followed by another pipelined depth stall
  51     *      (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
  52     *      guarantee that the pipeline from WM onwards is already flushed
  53     *      (e.g., via a preceding MI_FLUSH)."
  54     */
  55    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
  56    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
  57    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
  58 }
  59
  60 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
  61
  62 static void
  63 gen8_draw_sf(struct ilo_render *r,
  64              const struct ilo_state_vector *vec,
  65              struct ilo_render_draw_session *session)
  66 {
  67    /* 3DSTATE_RASTER */
  68    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_RASTER)
  69       gen8_3DSTATE_RASTER(r->builder, &vec->rasterizer->rs);
  70
  71    /* 3DSTATE_SBE and 3DSTATE_SBE_SWIZ */
  72    if (DIRTY(FS)) {
  73       const struct ilo_state_sbe *sbe = ilo_shader_get_kernel_sbe(vec->fs);
  74
  75       gen8_3DSTATE_SBE(r->builder, sbe);
  76       gen8_3DSTATE_SBE_SWIZ(r->builder, sbe);
  77    }
  78
  79    /* 3DSTATE_SF */
  80    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SF)
  81       gen7_3DSTATE_SF(r->builder, &vec->rasterizer->rs);
  82 }
  83
  84 static void
  85 gen8_draw_wm(struct ilo_render *r,
  86              const struct ilo_state_vector *vec,
  87              struct ilo_render_draw_session *session)
  88 {
  89    const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
  90    const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
  91
  92    /* 3DSTATE_WM */
  93    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM)
  94       gen8_3DSTATE_WM(r->builder, &vec->rasterizer->rs);
  95
  96    if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL)
  97       gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, &vec->blend->cc);
  98
  99    /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
 100    if (r->hw_ctx_changed) {
 101       gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
 102       gen8_3DSTATE_WM_CHROMAKEY(r->builder);
 103    }
 104
 105    /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
 106    if (session->binding_table_fs_changed) {
 107       gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
 108             r->state.wm.BINDING_TABLE_STATE);
 109    }
 110
 111    /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
 112    if (session->sampler_fs_changed) {
 113       gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
 114             r->state.wm.SAMPLER_STATE);
 115    }
 116
 117    /* 3DSTATE_CONSTANT_PS */
 118    if (session->pcb_fs_changed) {
 119       gen7_3DSTATE_CONSTANT_PS(r->builder,
 120             &r->state.wm.PUSH_CONSTANT_BUFFER,
 121             &r->state.wm.PUSH_CONSTANT_BUFFER_size,
 122             1);
 123    }
 124
 125    /* 3DSTATE_PS */
 126    if (DIRTY(FS) || r->instruction_bo_changed)
 127       gen8_3DSTATE_PS(r->builder, &cso->ps, kernel_offset);
 128
 129    /* 3DSTATE_PS_EXTRA */
 130    if (DIRTY(FS))
 131       gen8_3DSTATE_PS_EXTRA(r->builder, &cso->ps);
 132
 133    /* 3DSTATE_PS_BLEND */
 134    if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_PS_BLEND)
 135       gen8_3DSTATE_PS_BLEND(r->builder, &vec->blend->cc);
 136
 137    /* 3DSTATE_SCISSOR_STATE_POINTERS */
 138    if (session->scissor_changed) {
 139       gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
 140             r->state.SCISSOR_RECT);
 141    }
 142
 143    /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
 144    if (DIRTY(FB) || r->batch_bo_changed) {
 145       const struct ilo_state_zs *zs;
 146       uint32_t clear_params;
 147
 148       if (vec->fb.state.zsbuf) {
 149          const struct ilo_surface_cso *surface =
 150             (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
 151          const struct ilo_texture_slice *slice =
 152             ilo_texture_get_slice(ilo_texture(surface->base.texture),
 153                   surface->base.u.tex.level, surface->base.u.tex.first_layer);
 154
 155          assert(!surface->is_rt);
 156          zs = &surface->u.zs;
 157          clear_params = slice->clear_value;
 158       }
 159       else {
 160          zs = &vec->fb.null_zs;
 161          clear_params = 0;
 162       }
 163
 164       gen8_wa_pre_depth(r);
 165
 166       gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
 167       gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
 168       gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
 169       gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
 170    }
 171 }
 172
 173 static void
 174 gen8_draw_wm_sample_pattern(struct ilo_render *r,
 175                             const struct ilo_state_vector *vec,
 176                             struct ilo_render_draw_session *session)
 177 {
 178    /* 3DSTATE_SAMPLE_PATTERN */
 179    if (r->hw_ctx_changed) {
 180       gen8_3DSTATE_SAMPLE_PATTERN(r->builder,
 181             &r->sample_pattern_1x,
 182             &r->sample_pattern_2x,
 183             &r->sample_pattern_4x,
 184             r->sample_pattern_8x,
 185             r->sample_pattern_16x);
 186    }
 187 }
 188
 189 static void
 190 gen8_draw_wm_multisample(struct ilo_render *r,
 191                          const struct ilo_state_vector *vec,
 192                          struct ilo_render_draw_session *session)
 193 {
 194    /* 3DSTATE_MULTISAMPLE */
 195    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_MULTISAMPLE)
 196       gen8_3DSTATE_MULTISAMPLE(r->builder, &vec->rasterizer->rs);
 197
 198    /* 3DSTATE_SAMPLE_MASK */
 199    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK)
 200       gen6_3DSTATE_SAMPLE_MASK(r->builder, &vec->rasterizer->rs);
 201 }
 202
 203 static void
 204 gen8_draw_vf(struct ilo_render *r,
 205              const struct ilo_state_vector *vec,
 206              struct ilo_render_draw_session *session)
 207 {
 208    int i;
 209
 210    /* 3DSTATE_INDEX_BUFFER */
 211    if (DIRTY(IB) || r->batch_bo_changed)
 212       gen8_3DSTATE_INDEX_BUFFER(r->builder, &vec->ib);
 213
 214    /* 3DSTATE_VF */
 215    if (session->primitive_restart_changed) {
 216       gen75_3DSTATE_VF(r->builder, vec->draw->primitive_restart,
 217             vec->draw->restart_index);
 218    }
 219
 220    /* 3DSTATE_VERTEX_BUFFERS */
 221    if (DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed) {
 222       gen6_3DSTATE_VERTEX_BUFFERS(r->builder, &vec->vb, vec->ve->vb_mapping,
 223             vec->ve->instance_divisors, vec->ve->vb_count);
 224    }
 225
 226    /* 3DSTATE_VERTEX_ELEMENTS */
 227    if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS)
 228       gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &vec->ve->vf);
 229
 230    gen8_3DSTATE_VF_TOPOLOGY(r->builder,
 231          gen6_3d_translate_pipe_prim(vec->draw->mode));
 232
 233    for (i = 0; i < vec->ve->vb_count; i++) {
 234       gen8_3DSTATE_VF_INSTANCING(r->builder, i,
 235             vec->ve->instance_divisors[i]);
 236    }
 237
 238    if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF_SGVS)
 239       gen8_3DSTATE_VF_SGVS(r->builder, &vec->ve->vf);
 240 }
 241
 242 void
 243 ilo_render_emit_draw_commands_gen8(struct ilo_render *render,
 244                                    const struct ilo_state_vector *vec,
 245                                    struct ilo_render_draw_session *session)
 246 {
 247    ILO_DEV_ASSERT(render->dev, 8, 8);
 248
 249    /*
 250     * We try to keep the order of the commands match, as closely as possible,
 251     * that of the classic i965 driver.  It allows us to compare the command
 252     * streams easily.
 253     */
 254    gen6_draw_common_select(render, vec, session);
 255    gen6_draw_common_sip(render, vec, session);
 256    gen6_draw_vf_statistics(render, vec, session);
 257    gen8_draw_wm_sample_pattern(render, vec, session);
 258    gen6_draw_common_base_address(render, vec, session);
 259    gen7_draw_common_pointers_1(render, vec, session);
 260    gen7_draw_common_pcb_alloc(render, vec, session);
 261    gen7_draw_common_urb(render, vec, session);
 262    gen7_draw_common_pointers_2(render, vec, session);
 263    gen8_draw_wm_multisample(render, vec, session);
 264    gen7_draw_gs(render, vec, session);
 265    gen7_draw_hs(render, vec, session);
 266    gen7_draw_te(render, vec, session);
 267    gen7_draw_ds(render, vec, session);
 268    gen7_draw_vs(render, vec, session);
 269    gen7_draw_sol(render, vec, session);
 270    gen6_draw_clip(render, vec, session);
 271    gen8_draw_sf(render, vec, session);
 272    gen8_draw_wm(render, vec, session);
 273    gen6_draw_wm_raster(render, vec, session);
 274    gen6_draw_sf_rect(render, vec, session);
 275    gen8_draw_vf(render, vec, session);
 276
 277    ilo_render_3dprimitive(render, vec->draw, &vec->ib);
 278 }
 279
 280 int
 281 ilo_render_get_draw_commands_len_gen8(const struct ilo_render *render,
 282                                       const struct ilo_state_vector *vec)
 283 {
 284    static int len;
 285
 286    ILO_DEV_ASSERT(render->dev, 8, 8);
 287
 288    if (!len) {
 289       len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
 290       len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
 291       len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
 292       len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
 293       len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
 294       len += GEN6_PIPE_CONTROL__SIZE * 5;
 295
 296       len +=
 297          GEN6_STATE_BASE_ADDRESS__SIZE +
 298          GEN6_STATE_SIP__SIZE +
 299          GEN6_3DSTATE_VF_STATISTICS__SIZE +
 300          GEN6_PIPELINE_SELECT__SIZE +
 301          GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
 302          GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
 303          GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
 304          GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
 305          GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
 306          GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
 307          GEN6_3DSTATE_INDEX_BUFFER__SIZE +
 308          GEN75_3DSTATE_VF__SIZE +
 309          GEN6_3DSTATE_VS__SIZE +
 310          GEN6_3DSTATE_GS__SIZE +
 311          GEN6_3DSTATE_CLIP__SIZE +
 312          GEN6_3DSTATE_SF__SIZE +
 313          GEN6_3DSTATE_WM__SIZE +
 314          GEN6_3DSTATE_SAMPLE_MASK__SIZE +
 315          GEN7_3DSTATE_HS__SIZE +
 316          GEN7_3DSTATE_TE__SIZE +
 317          GEN7_3DSTATE_DS__SIZE +
 318          GEN7_3DSTATE_STREAMOUT__SIZE +
 319          GEN7_3DSTATE_SBE__SIZE +
 320          GEN7_3DSTATE_PS__SIZE +
 321          GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
 322          GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
 323          GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
 324          GEN6_3DSTATE_LINE_STIPPLE__SIZE +
 325          GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
 326          GEN6_3DSTATE_MULTISAMPLE__SIZE +
 327          GEN7_3DSTATE_SO_DECL_LIST__SIZE +
 328          GEN6_3DPRIMITIVE__SIZE;
 329
 330       len +=
 331          GEN8_3DSTATE_VF_INSTANCING__SIZE * 33 +
 332          GEN8_3DSTATE_VF_SGVS__SIZE +
 333          GEN8_3DSTATE_VF_TOPOLOGY__SIZE +
 334          GEN8_3DSTATE_SBE_SWIZ__SIZE +
 335          GEN8_3DSTATE_RASTER__SIZE +
 336          GEN8_3DSTATE_WM_CHROMAKEY__SIZE +
 337          GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE +
 338          GEN8_3DSTATE_WM_HZ_OP__SIZE +
 339          GEN8_3DSTATE_PS_EXTRA__SIZE +
 340          GEN8_3DSTATE_PS_BLEND__SIZE +
 341          GEN8_3DSTATE_SAMPLE_PATTERN__SIZE;
 342    }
 343
 344    return len;
 345 }
 346
 347 int
 348 ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render *render,
 349                                           const struct ilo_blitter *blitter)
 350 {
 351    ILO_DEV_ASSERT(render->dev, 8, 8);
 352
 353    return 96;
 354 }
 355
 356 void
 357 ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
 358                                        const struct ilo_blitter *blitter,
 359                                        const struct ilo_render_rectlist_session *session)
 360 {
 361    ILO_DEV_ASSERT(r->dev, 8, 8);
 362
 363    gen8_wa_pre_depth(r);
 364
 365    if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
 366                         ILO_BLITTER_USE_FB_STENCIL))
 367       gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
 368
 369    if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
 370       gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
 371             &blitter->fb.dst.u.zs);
 372    }
 373
 374    if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
 375       gen6_3DSTATE_STENCIL_BUFFER(r->builder,
 376             &blitter->fb.dst.u.zs);
 377    }
 378
 379    gen7_3DSTATE_CLEAR_PARAMS(r->builder,
 380          blitter->depth_clear_value);
 381
 382    gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
 383          blitter->fb.width, blitter->fb.height);
 384
 385    gen8_3DSTATE_WM_HZ_OP(r->builder, &blitter->fb.rs,
 386          blitter->fb.width, blitter->fb.height);
 387
 388    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
 389
 390    gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
 391 }