2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_render.h"
31 #include "util/u_dual_blend.h"
33 #include "ilo_blitter.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
39 gen8_wa_pre_depth(struct ilo_render
*r
)
41 ILO_DEV_ASSERT(r
->dev
, 8, 8);
44 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
46 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
47 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
48 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
49 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
50 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
51 * Depth Flush Bit set, followed by another pipelined depth stall
52 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
53 * guarantee that the pipeline from WM onwards is already flushed
54 * (e.g., via a preceding MI_FLUSH)."
56 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
57 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
58 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
61 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
64 gen8_draw_sf(struct ilo_render
*r
,
65 const struct ilo_state_vector
*vec
,
66 struct ilo_render_draw_session
*session
)
69 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_RASTER
)
70 gen8_3DSTATE_RASTER(r
->builder
, &vec
->rasterizer
->rs
);
73 if (DIRTY(RASTERIZER
) || DIRTY(FS
)) {
74 gen8_3DSTATE_SBE(r
->builder
, vec
->fs
, (vec
->rasterizer
) ?
75 vec
->rasterizer
->state
.sprite_coord_mode
: 0);
78 /* 3DSTATE_SBE_SWIZ */
80 gen8_3DSTATE_SBE_SWIZ(r
->builder
, vec
->fs
);
83 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SF
)
84 gen7_3DSTATE_SF(r
->builder
, &vec
->rasterizer
->rs
);
88 gen8_draw_wm(struct ilo_render
*r
,
89 const struct ilo_state_vector
*vec
,
90 struct ilo_render_draw_session
*session
)
93 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_WM
)
94 gen8_3DSTATE_WM(r
->builder
, &vec
->rasterizer
->rs
);
97 gen8_3DSTATE_WM_DEPTH_STENCIL(r
->builder
, vec
->dsa
);
99 /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
100 if (r
->hw_ctx_changed
) {
101 gen8_disable_3DSTATE_WM_HZ_OP(r
->builder
);
102 gen8_3DSTATE_WM_CHROMAKEY(r
->builder
);
105 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
106 if (session
->binding_table_fs_changed
) {
107 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r
->builder
,
108 r
->state
.wm
.BINDING_TABLE_STATE
);
111 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
112 if (session
->sampler_fs_changed
) {
113 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r
->builder
,
114 r
->state
.wm
.SAMPLER_STATE
);
117 /* 3DSTATE_CONSTANT_PS */
118 if (session
->pcb_fs_changed
) {
119 gen7_3DSTATE_CONSTANT_PS(r
->builder
,
120 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
121 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
126 if (DIRTY(FS
) || r
->instruction_bo_changed
)
127 gen8_3DSTATE_PS(r
->builder
, vec
->fs
);
129 /* 3DSTATE_PS_EXTRA */
130 if (DIRTY(FS
) || DIRTY(DSA
) || DIRTY(BLEND
)) {
131 const bool cc_may_kill
= (vec
->dsa
->dw_blend_alpha
||
132 vec
->blend
->alpha_to_coverage
);
133 gen8_3DSTATE_PS_EXTRA(r
->builder
, vec
->fs
, cc_may_kill
, false);
136 /* 3DSTATE_PS_BLEND */
137 if (DIRTY(BLEND
) || DIRTY(FB
) || DIRTY(DSA
))
138 gen8_3DSTATE_PS_BLEND(r
->builder
, vec
->blend
, &vec
->fb
, vec
->dsa
);
140 /* 3DSTATE_SCISSOR_STATE_POINTERS */
141 if (session
->scissor_changed
) {
142 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
143 r
->state
.SCISSOR_RECT
);
146 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
147 if (DIRTY(FB
) || r
->batch_bo_changed
) {
148 const struct ilo_state_zs
*zs
;
149 uint32_t clear_params
;
151 if (vec
->fb
.state
.zsbuf
) {
152 const struct ilo_surface_cso
*surface
=
153 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
154 const struct ilo_texture_slice
*slice
=
155 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
156 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
158 assert(!surface
->is_rt
);
160 clear_params
= slice
->clear_value
;
163 zs
= &vec
->fb
.null_zs
;
167 gen8_wa_pre_depth(r
);
169 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
170 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
171 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
172 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
177 gen8_draw_wm_sample_pattern(struct ilo_render
*r
,
178 const struct ilo_state_vector
*vec
,
179 struct ilo_render_draw_session
*session
)
181 /* 3DSTATE_SAMPLE_PATTERN */
182 if (r
->hw_ctx_changed
) {
183 gen8_3DSTATE_SAMPLE_PATTERN(r
->builder
,
184 &r
->sample_pattern_1x
,
185 &r
->sample_pattern_2x
,
186 &r
->sample_pattern_4x
,
187 r
->sample_pattern_8x
,
188 r
->sample_pattern_16x
);
193 gen8_draw_wm_multisample(struct ilo_render
*r
,
194 const struct ilo_state_vector
*vec
,
195 struct ilo_render_draw_session
*session
)
197 /* 3DSTATE_MULTISAMPLE */
198 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_MULTISAMPLE
)
199 gen8_3DSTATE_MULTISAMPLE(r
->builder
, &vec
->rasterizer
->rs
);
201 /* 3DSTATE_SAMPLE_MASK */
202 if (session
->rs_delta
.dirty
& ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK
)
203 gen6_3DSTATE_SAMPLE_MASK(r
->builder
, &vec
->rasterizer
->rs
);
207 gen8_draw_vf(struct ilo_render
*r
,
208 const struct ilo_state_vector
*vec
,
209 struct ilo_render_draw_session
*session
)
213 /* 3DSTATE_INDEX_BUFFER */
214 if (DIRTY(IB
) || r
->batch_bo_changed
)
215 gen8_3DSTATE_INDEX_BUFFER(r
->builder
, &vec
->ib
);
218 if (session
->primitive_restart_changed
) {
219 gen75_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
220 vec
->draw
->restart_index
);
223 /* 3DSTATE_VERTEX_BUFFERS */
224 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
225 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
227 /* 3DSTATE_VERTEX_ELEMENTS */
229 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, vec
->ve
);
231 gen8_3DSTATE_VF_TOPOLOGY(r
->builder
, vec
->draw
->mode
);
233 for (i
= 0; i
< vec
->ve
->vb_count
; i
++) {
234 gen8_3DSTATE_VF_INSTANCING(r
->builder
, i
,
235 vec
->ve
->instance_divisors
[i
]);
238 gen8_3DSTATE_VF_SGVS(r
->builder
,
244 ilo_render_emit_draw_commands_gen8(struct ilo_render
*render
,
245 const struct ilo_state_vector
*vec
,
246 struct ilo_render_draw_session
*session
)
248 ILO_DEV_ASSERT(render
->dev
, 8, 8);
251 * We try to keep the order of the commands match, as closely as possible,
252 * that of the classic i965 driver. It allows us to compare the command
255 gen6_draw_common_select(render
, vec
, session
);
256 gen6_draw_common_sip(render
, vec
, session
);
257 gen6_draw_vf_statistics(render
, vec
, session
);
258 gen8_draw_wm_sample_pattern(render
, vec
, session
);
259 gen6_draw_common_base_address(render
, vec
, session
);
260 gen7_draw_common_pointers_1(render
, vec
, session
);
261 gen7_draw_common_pcb_alloc(render
, vec
, session
);
262 gen7_draw_common_urb(render
, vec
, session
);
263 gen7_draw_common_pointers_2(render
, vec
, session
);
264 gen8_draw_wm_multisample(render
, vec
, session
);
265 gen7_draw_gs(render
, vec
, session
);
266 gen7_draw_hs(render
, vec
, session
);
267 gen7_draw_te(render
, vec
, session
);
268 gen7_draw_ds(render
, vec
, session
);
269 gen7_draw_vs(render
, vec
, session
);
270 gen7_draw_sol(render
, vec
, session
);
271 gen6_draw_clip(render
, vec
, session
);
272 gen8_draw_sf(render
, vec
, session
);
273 gen8_draw_wm(render
, vec
, session
);
274 gen6_draw_wm_raster(render
, vec
, session
);
275 gen6_draw_sf_rect(render
, vec
, session
);
276 gen8_draw_vf(render
, vec
, session
);
278 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
282 ilo_render_get_draw_commands_len_gen8(const struct ilo_render
*render
,
283 const struct ilo_state_vector
*vec
)
287 ILO_DEV_ASSERT(render
->dev
, 8, 8);
290 len
+= GEN7_3DSTATE_URB_ANY__SIZE
* 4;
291 len
+= GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE
* 5;
292 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 5;
293 len
+= GEN7_3DSTATE_POINTERS_ANY__SIZE
* (5 + 5 + 4);
294 len
+= GEN7_3DSTATE_SO_BUFFER__SIZE
* 4;
295 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
298 GEN6_STATE_BASE_ADDRESS__SIZE
+
299 GEN6_STATE_SIP__SIZE
+
300 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
301 GEN6_PIPELINE_SELECT__SIZE
+
302 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
303 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
304 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
305 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
306 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
307 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
308 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
309 GEN75_3DSTATE_VF__SIZE
+
310 GEN6_3DSTATE_VS__SIZE
+
311 GEN6_3DSTATE_GS__SIZE
+
312 GEN6_3DSTATE_CLIP__SIZE
+
313 GEN6_3DSTATE_SF__SIZE
+
314 GEN6_3DSTATE_WM__SIZE
+
315 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
316 GEN7_3DSTATE_HS__SIZE
+
317 GEN7_3DSTATE_TE__SIZE
+
318 GEN7_3DSTATE_DS__SIZE
+
319 GEN7_3DSTATE_STREAMOUT__SIZE
+
320 GEN7_3DSTATE_SBE__SIZE
+
321 GEN7_3DSTATE_PS__SIZE
+
322 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
323 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
324 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
325 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
326 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
327 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
328 GEN7_3DSTATE_SO_DECL_LIST__SIZE
+
329 GEN6_3DPRIMITIVE__SIZE
;
332 GEN8_3DSTATE_VF_INSTANCING__SIZE
* 33 +
333 GEN8_3DSTATE_VF_SGVS__SIZE
+
334 GEN8_3DSTATE_VF_TOPOLOGY__SIZE
+
335 GEN8_3DSTATE_SBE_SWIZ__SIZE
+
336 GEN8_3DSTATE_RASTER__SIZE
+
337 GEN8_3DSTATE_WM_CHROMAKEY__SIZE
+
338 GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE
+
339 GEN8_3DSTATE_WM_HZ_OP__SIZE
+
340 GEN8_3DSTATE_PS_EXTRA__SIZE
+
341 GEN8_3DSTATE_PS_BLEND__SIZE
+
342 GEN8_3DSTATE_SAMPLE_PATTERN__SIZE
;
349 ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render
*render
,
350 const struct ilo_blitter
*blitter
)
352 ILO_DEV_ASSERT(render
->dev
, 8, 8);
358 ilo_render_emit_rectlist_commands_gen8(struct ilo_render
*r
,
359 const struct ilo_blitter
*blitter
,
360 const struct ilo_render_rectlist_session
*session
)
362 ILO_DEV_ASSERT(r
->dev
, 8, 8);
364 gen8_wa_pre_depth(r
);
366 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
367 ILO_BLITTER_USE_FB_STENCIL
))
368 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
370 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
371 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
372 &blitter
->fb
.dst
.u
.zs
);
375 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
376 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
377 &blitter
->fb
.dst
.u
.zs
);
380 gen7_3DSTATE_CLEAR_PARAMS(r
->builder
,
381 blitter
->depth_clear_value
);
383 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
384 blitter
->fb
.width
, blitter
->fb
.height
);
386 gen8_3DSTATE_WM_HZ_OP(r
->builder
, &blitter
->fb
.rs
,
387 blitter
->fb
.width
, blitter
->fb
.height
);
389 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_WRITE_IMM
);
391 gen8_disable_3DSTATE_WM_HZ_OP(r
->builder
);