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[mesa.git] / src / gallium / drivers / ilo / ilo_render_gen8.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_render.h"
31 #include "util/u_dual_blend.h"
32
33 #include "ilo_blitter.h"
34 #include "ilo_shader.h"
35 #include "ilo_state.h"
36 #include "ilo_render_gen.h"
37
38 static void
39 gen8_wa_pre_depth(struct ilo_render *r)
40 {
41 ILO_DEV_ASSERT(r->dev, 8, 8);
42
43 /*
44 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
45 *
46 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
47 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
48 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
49 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
50 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
51 * Depth Flush Bit set, followed by another pipelined depth stall
52 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
53 * guarantee that the pipeline from WM onwards is already flushed
54 * (e.g., via a preceding MI_FLUSH)."
55 */
56 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
57 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
58 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
59 }
60
61 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
62
63 static void
64 gen8_draw_sf(struct ilo_render *r,
65 const struct ilo_state_vector *vec,
66 struct ilo_render_draw_session *session)
67 {
68 /* 3DSTATE_RASTER */
69 if (DIRTY(RASTERIZER)) {
70 gen8_3DSTATE_RASTER(r->builder, (vec->rasterizer) ?
71 &vec->rasterizer->sf : NULL);
72 }
73
74 /* 3DSTATE_SBE */
75 if (DIRTY(RASTERIZER) || DIRTY(FS)) {
76 gen8_3DSTATE_SBE(r->builder, vec->fs, (vec->rasterizer) ?
77 vec->rasterizer->state.sprite_coord_mode : 0);
78 }
79
80 /* 3DSTATE_SBE_SWIZ */
81 if (DIRTY(FS))
82 gen8_3DSTATE_SBE_SWIZ(r->builder, vec->fs);
83
84 /* 3DSTATE_SF */
85 if (DIRTY(RASTERIZER)) {
86 gen8_3DSTATE_SF(r->builder, (vec->rasterizer) ?
87 &vec->rasterizer->sf : NULL);
88 }
89 }
90
91 static void
92 gen8_draw_wm(struct ilo_render *r,
93 const struct ilo_state_vector *vec,
94 struct ilo_render_draw_session *session)
95 {
96 /* 3DSTATE_WM */
97 if (DIRTY(FS) || DIRTY(RASTERIZER))
98 gen8_3DSTATE_WM(r->builder, vec->fs, vec->rasterizer);
99
100 if (DIRTY(DSA))
101 gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, vec->dsa);
102
103 /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
104 if (r->hw_ctx_changed) {
105 gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
106 gen8_3DSTATE_WM_CHROMAKEY(r->builder);
107 }
108
109 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
110 if (session->binding_table_fs_changed) {
111 gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
112 r->state.wm.BINDING_TABLE_STATE);
113 }
114
115 /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
116 if (session->sampler_fs_changed) {
117 gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
118 r->state.wm.SAMPLER_STATE);
119 }
120
121 /* 3DSTATE_CONSTANT_PS */
122 if (session->pcb_fs_changed) {
123 gen7_3DSTATE_CONSTANT_PS(r->builder,
124 &r->state.wm.PUSH_CONSTANT_BUFFER,
125 &r->state.wm.PUSH_CONSTANT_BUFFER_size,
126 1);
127 }
128
129 /* 3DSTATE_PS */
130 if (DIRTY(FS) || r->instruction_bo_changed)
131 gen8_3DSTATE_PS(r->builder, vec->fs);
132
133 /* 3DSTATE_PS_EXTRA */
134 if (DIRTY(FS) || DIRTY(DSA) || DIRTY(BLEND)) {
135 const bool cc_may_kill = (vec->dsa->dw_blend_alpha ||
136 vec->blend->alpha_to_coverage);
137 gen8_3DSTATE_PS_EXTRA(r->builder, vec->fs, cc_may_kill, false);
138 }
139
140 /* 3DSTATE_PS_BLEND */
141 if (DIRTY(BLEND) || DIRTY(FB) || DIRTY(DSA))
142 gen8_3DSTATE_PS_BLEND(r->builder, vec->blend, &vec->fb, vec->dsa);
143
144 /* 3DSTATE_SCISSOR_STATE_POINTERS */
145 if (session->scissor_changed) {
146 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
147 r->state.SCISSOR_RECT);
148 }
149
150 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
151 if (DIRTY(FB) || r->batch_bo_changed) {
152 const struct ilo_state_zs *zs;
153 uint32_t clear_params;
154
155 if (vec->fb.state.zsbuf) {
156 const struct ilo_surface_cso *surface =
157 (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
158 const struct ilo_texture_slice *slice =
159 ilo_texture_get_slice(ilo_texture(surface->base.texture),
160 surface->base.u.tex.level, surface->base.u.tex.first_layer);
161
162 assert(!surface->is_rt);
163 zs = &surface->u.zs;
164 clear_params = slice->clear_value;
165 }
166 else {
167 zs = &vec->fb.null_zs;
168 clear_params = 0;
169 }
170
171 gen8_wa_pre_depth(r);
172
173 gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
174 gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
175 gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
176 gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
177 }
178 }
179
180 static void
181 gen8_draw_wm_sample_pattern(struct ilo_render *r,
182 const struct ilo_state_vector *vec,
183 struct ilo_render_draw_session *session)
184 {
185 /* 3DSTATE_SAMPLE_PATTERN */
186 if (r->hw_ctx_changed) {
187 gen8_3DSTATE_SAMPLE_PATTERN(r->builder,
188 &r->sample_pattern_1x,
189 &r->sample_pattern_2x,
190 &r->sample_pattern_4x,
191 r->sample_pattern_8x,
192 r->sample_pattern_16x);
193 }
194 }
195
196 static void
197 gen8_draw_wm_multisample(struct ilo_render *r,
198 const struct ilo_state_vector *vec,
199 struct ilo_render_draw_session *session)
200 {
201 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
202 if (DIRTY(SAMPLE_MASK) || DIRTY(FB) || DIRTY(RASTERIZER)) {
203 gen8_3DSTATE_MULTISAMPLE(r->builder, vec->fb.num_samples,
204 vec->rasterizer->state.half_pixel_center);
205
206 gen7_3DSTATE_SAMPLE_MASK(r->builder,
207 (vec->fb.num_samples > 1) ? vec->sample_mask : 0x1,
208 vec->fb.num_samples);
209 }
210 }
211
212 static void
213 gen8_draw_vf(struct ilo_render *r,
214 const struct ilo_state_vector *vec,
215 struct ilo_render_draw_session *session)
216 {
217 int i;
218
219 /* 3DSTATE_INDEX_BUFFER */
220 if (DIRTY(IB) || r->batch_bo_changed)
221 gen8_3DSTATE_INDEX_BUFFER(r->builder, &vec->ib);
222
223 /* 3DSTATE_VF */
224 if (session->primitive_restart_changed) {
225 gen75_3DSTATE_VF(r->builder, vec->draw->primitive_restart,
226 vec->draw->restart_index);
227 }
228
229 /* 3DSTATE_VERTEX_BUFFERS */
230 if (DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed)
231 gen6_3DSTATE_VERTEX_BUFFERS(r->builder, vec->ve, &vec->vb);
232
233 /* 3DSTATE_VERTEX_ELEMENTS */
234 if (DIRTY(VE))
235 gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, vec->ve);
236
237 gen8_3DSTATE_VF_TOPOLOGY(r->builder, vec->draw->mode);
238
239 for (i = 0; i < vec->ve->vb_count; i++) {
240 gen8_3DSTATE_VF_INSTANCING(r->builder, i,
241 vec->ve->instance_divisors[i]);
242 }
243
244 gen8_3DSTATE_VF_SGVS(r->builder,
245 false, 0, 0,
246 false, 0, 0);
247 }
248
249 void
250 ilo_render_emit_draw_commands_gen8(struct ilo_render *render,
251 const struct ilo_state_vector *vec,
252 struct ilo_render_draw_session *session)
253 {
254 ILO_DEV_ASSERT(render->dev, 8, 8);
255
256 /*
257 * We try to keep the order of the commands match, as closely as possible,
258 * that of the classic i965 driver. It allows us to compare the command
259 * streams easily.
260 */
261 gen6_draw_common_select(render, vec, session);
262 gen6_draw_common_sip(render, vec, session);
263 gen6_draw_vf_statistics(render, vec, session);
264 gen8_draw_wm_sample_pattern(render, vec, session);
265 gen6_draw_common_base_address(render, vec, session);
266 gen7_draw_common_pointers_1(render, vec, session);
267 gen7_draw_common_pcb_alloc(render, vec, session);
268 gen7_draw_common_urb(render, vec, session);
269 gen7_draw_common_pointers_2(render, vec, session);
270 gen8_draw_wm_multisample(render, vec, session);
271 gen7_draw_gs(render, vec, session);
272 gen7_draw_hs(render, vec, session);
273 gen7_draw_te(render, vec, session);
274 gen7_draw_ds(render, vec, session);
275 gen7_draw_vs(render, vec, session);
276 gen7_draw_sol(render, vec, session);
277 gen6_draw_clip(render, vec, session);
278 gen8_draw_sf(render, vec, session);
279 gen8_draw_wm(render, vec, session);
280 gen6_draw_wm_raster(render, vec, session);
281 gen6_draw_sf_rect(render, vec, session);
282 gen8_draw_vf(render, vec, session);
283
284 ilo_render_3dprimitive(render, vec->draw, &vec->ib);
285 }
286
287 int
288 ilo_render_get_draw_commands_len_gen8(const struct ilo_render *render,
289 const struct ilo_state_vector *vec)
290 {
291 static int len;
292
293 ILO_DEV_ASSERT(render->dev, 8, 8);
294
295 if (!len) {
296 len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
297 len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
298 len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
299 len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
300 len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
301 len += GEN6_PIPE_CONTROL__SIZE * 5;
302
303 len +=
304 GEN6_STATE_BASE_ADDRESS__SIZE +
305 GEN6_STATE_SIP__SIZE +
306 GEN6_3DSTATE_VF_STATISTICS__SIZE +
307 GEN6_PIPELINE_SELECT__SIZE +
308 GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
309 GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
310 GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
311 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
312 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
313 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
314 GEN6_3DSTATE_INDEX_BUFFER__SIZE +
315 GEN75_3DSTATE_VF__SIZE +
316 GEN6_3DSTATE_VS__SIZE +
317 GEN6_3DSTATE_GS__SIZE +
318 GEN6_3DSTATE_CLIP__SIZE +
319 GEN6_3DSTATE_SF__SIZE +
320 GEN6_3DSTATE_WM__SIZE +
321 GEN6_3DSTATE_SAMPLE_MASK__SIZE +
322 GEN7_3DSTATE_HS__SIZE +
323 GEN7_3DSTATE_TE__SIZE +
324 GEN7_3DSTATE_DS__SIZE +
325 GEN7_3DSTATE_STREAMOUT__SIZE +
326 GEN7_3DSTATE_SBE__SIZE +
327 GEN7_3DSTATE_PS__SIZE +
328 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
329 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
330 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
331 GEN6_3DSTATE_LINE_STIPPLE__SIZE +
332 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
333 GEN6_3DSTATE_MULTISAMPLE__SIZE +
334 GEN7_3DSTATE_SO_DECL_LIST__SIZE +
335 GEN6_3DPRIMITIVE__SIZE;
336
337 len +=
338 GEN8_3DSTATE_VF_INSTANCING__SIZE * 33 +
339 GEN8_3DSTATE_VF_SGVS__SIZE +
340 GEN8_3DSTATE_VF_TOPOLOGY__SIZE +
341 GEN8_3DSTATE_SBE_SWIZ__SIZE +
342 GEN8_3DSTATE_RASTER__SIZE +
343 GEN8_3DSTATE_WM_CHROMAKEY__SIZE +
344 GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE +
345 GEN8_3DSTATE_WM_HZ_OP__SIZE +
346 GEN8_3DSTATE_PS_EXTRA__SIZE +
347 GEN8_3DSTATE_PS_BLEND__SIZE +
348 GEN8_3DSTATE_SAMPLE_PATTERN__SIZE;
349 }
350
351 return len;
352 }
353
354 int
355 ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render *render,
356 const struct ilo_blitter *blitter)
357 {
358 ILO_DEV_ASSERT(render->dev, 8, 8);
359
360 return 96;
361 }
362
363 void
364 ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
365 const struct ilo_blitter *blitter,
366 const struct ilo_render_rectlist_session *session)
367 {
368 uint32_t op;
369
370 ILO_DEV_ASSERT(r->dev, 8, 8);
371
372 gen8_wa_pre_depth(r);
373
374 if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
375 ILO_BLITTER_USE_FB_STENCIL))
376 gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
377
378 if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
379 gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
380 &blitter->fb.dst.u.zs);
381 }
382
383 if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
384 gen6_3DSTATE_STENCIL_BUFFER(r->builder,
385 &blitter->fb.dst.u.zs);
386 }
387
388 gen7_3DSTATE_CLEAR_PARAMS(r->builder,
389 blitter->depth_clear_value);
390
391 gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
392 blitter->fb.width, blitter->fb.height);
393
394 switch (blitter->op) {
395 case ILO_BLITTER_RECTLIST_CLEAR_ZS:
396 op = 0;
397 if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH)
398 op |= GEN8_WM_HZ_DW1_DEPTH_CLEAR;
399 if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL)
400 op |= GEN8_WM_HZ_DW1_STENCIL_CLEAR;
401 break;
402 case ILO_BLITTER_RECTLIST_RESOLVE_Z:
403 op = GEN8_WM_HZ_DW1_DEPTH_RESOLVE;
404 break;
405 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
406 op = GEN8_WM_HZ_DW1_HIZ_RESOLVE;
407 break;
408 default:
409 op = 0;
410 break;
411 }
412
413 gen8_3DSTATE_WM_HZ_OP(r->builder, op, blitter->fb.width,
414 blitter->fb.height, blitter->fb.num_samples);
415
416 ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
417
418 gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
419 }