src/gallium/drivers/ilo/ilo_render_gen8.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "core/ilo_builder_3d.h"
  30 #include "core/ilo_builder_render.h"
  31
  32 #include "ilo_blitter.h"
  33 #include "ilo_shader.h"
  34 #include "ilo_state.h"
  35 #include "ilo_render_gen.h"
  36
  37 static void
  38 gen8_wa_pre_depth(struct ilo_render *r)
  39 {
  40    ILO_DEV_ASSERT(r->dev, 8, 8);
  41
  42    /*
  43     * From the Ivy Bridge PRM, volume 2 part 1, page 315:
  44     *
  45     *     "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
  46     *      any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
  47     *      3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
  48     *      issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
  49     *      set), followed by a pipelined depth cache flush (PIPE_CONTROL with
  50     *      Depth Flush Bit set, followed by another pipelined depth stall
  51     *      (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
  52     *      guarantee that the pipeline from WM onwards is already flushed
  53     *      (e.g., via a preceding MI_FLUSH)."
  54     */
  55    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
  56    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
  57    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
  58 }
  59
  60 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
  61
  62 static void
  63 gen8_draw_sf(struct ilo_render *r,
  64              const struct ilo_state_vector *vec,
  65              struct ilo_render_draw_session *session)
  66 {
  67    /* 3DSTATE_RASTER */
  68    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_RASTER)
  69       gen8_3DSTATE_RASTER(r->builder, &vec->rasterizer->rs);
  70
  71    /* 3DSTATE_SBE and 3DSTATE_SBE_SWIZ */
  72    if (DIRTY(FS)) {
  73       const struct ilo_state_sbe *sbe = ilo_shader_get_kernel_sbe(vec->fs);
  74
  75       gen8_3DSTATE_SBE(r->builder, sbe);
  76       gen8_3DSTATE_SBE_SWIZ(r->builder, sbe);
  77    }
  78
  79    /* 3DSTATE_SF */
  80    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SF)
  81       gen7_3DSTATE_SF(r->builder, &vec->rasterizer->rs);
  82 }
  83
  84 static void
  85 gen8_draw_wm(struct ilo_render *r,
  86              const struct ilo_state_vector *vec,
  87              struct ilo_render_draw_session *session)
  88 {
  89    const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
  90    const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
  91
  92    /* 3DSTATE_WM */
  93    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM)
  94       gen8_3DSTATE_WM(r->builder, &vec->rasterizer->rs);
  95
  96    if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL)
  97       gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, &vec->blend->cc);
  98
  99    /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
 100    if (r->hw_ctx_changed) {
 101       gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
 102       gen8_3DSTATE_WM_CHROMAKEY(r->builder);
 103    }
 104
 105    /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
 106    if (session->binding_table_fs_changed) {
 107       gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
 108             r->state.wm.BINDING_TABLE_STATE);
 109    }
 110
 111    /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
 112    if (session->sampler_fs_changed) {
 113       gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
 114             r->state.wm.SAMPLER_STATE);
 115    }
 116
 117    /* 3DSTATE_CONSTANT_PS */
 118    if (session->pcb_fs_changed) {
 119       gen7_3DSTATE_CONSTANT_PS(r->builder,
 120             &r->state.wm.PUSH_CONSTANT_BUFFER,
 121             &r->state.wm.PUSH_CONSTANT_BUFFER_size,
 122             1);
 123    }
 124
 125    /* 3DSTATE_PS */
 126    if (DIRTY(FS) || r->instruction_bo_changed)
 127       gen8_3DSTATE_PS(r->builder, &cso->ps, kernel_offset);
 128
 129    /* 3DSTATE_PS_EXTRA */
 130    if (DIRTY(FS))
 131       gen8_3DSTATE_PS_EXTRA(r->builder, &cso->ps);
 132
 133    /* 3DSTATE_PS_BLEND */
 134    if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_PS_BLEND)
 135       gen8_3DSTATE_PS_BLEND(r->builder, &vec->blend->cc);
 136
 137    /* 3DSTATE_SCISSOR_STATE_POINTERS */
 138    if (session->scissor_changed) {
 139       gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
 140             r->state.SCISSOR_RECT);
 141    }
 142
 143    /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
 144    if (DIRTY(FB) || r->batch_bo_changed) {
 145       const struct ilo_state_zs *zs;
 146       uint32_t clear_params;
 147
 148       if (vec->fb.state.zsbuf) {
 149          const struct ilo_surface_cso *surface =
 150             (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
 151          const struct ilo_texture_slice *slice =
 152             ilo_texture_get_slice(ilo_texture(surface->base.texture),
 153                   surface->base.u.tex.level, surface->base.u.tex.first_layer);
 154
 155          assert(!surface->is_rt);
 156          zs = &surface->u.zs;
 157          clear_params = slice->clear_value;
 158       }
 159       else {
 160          zs = &vec->fb.null_zs;
 161          clear_params = 0;
 162       }
 163
 164       gen8_wa_pre_depth(r);
 165
 166       gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
 167       gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
 168       gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
 169       gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
 170    }
 171 }
 172
 173 static void
 174 gen8_draw_wm_sample_pattern(struct ilo_render *r,
 175                             const struct ilo_state_vector *vec,
 176                             struct ilo_render_draw_session *session)
 177 {
 178    /* 3DSTATE_SAMPLE_PATTERN */
 179    if (r->hw_ctx_changed)
 180       gen8_3DSTATE_SAMPLE_PATTERN(r->builder, &r->sample_pattern);
 181 }
 182
 183 static void
 184 gen8_draw_wm_multisample(struct ilo_render *r,
 185                          const struct ilo_state_vector *vec,
 186                          struct ilo_render_draw_session *session)
 187 {
 188    /* 3DSTATE_MULTISAMPLE */
 189    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_MULTISAMPLE)
 190       gen8_3DSTATE_MULTISAMPLE(r->builder, &vec->rasterizer->rs);
 191
 192    /* 3DSTATE_SAMPLE_MASK */
 193    if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK)
 194       gen6_3DSTATE_SAMPLE_MASK(r->builder, &vec->rasterizer->rs);
 195 }
 196
 197 static void
 198 gen8_draw_vf(struct ilo_render *r,
 199              const struct ilo_state_vector *vec,
 200              struct ilo_render_draw_session *session)
 201 {
 202    int i;
 203
 204    /* 3DSTATE_INDEX_BUFFER */
 205    if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_INDEX_BUFFER) ||
 206        DIRTY(IB) || r->batch_bo_changed)
 207       gen8_3DSTATE_INDEX_BUFFER(r->builder, &vec->ve->vf, &vec->ib);
 208
 209    /* 3DSTATE_VF */
 210    if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF)
 211       gen75_3DSTATE_VF(r->builder, &vec->ve->vf);
 212
 213    /* 3DSTATE_VERTEX_BUFFERS */
 214    if (DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed) {
 215       gen6_3DSTATE_VERTEX_BUFFERS(r->builder, &vec->vb, vec->ve->vb_mapping,
 216             vec->ve->instance_divisors, vec->ve->vb_count);
 217    }
 218
 219    /* 3DSTATE_VERTEX_ELEMENTS */
 220    if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS)
 221       gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &vec->ve->vf);
 222
 223    gen8_3DSTATE_VF_TOPOLOGY(r->builder,
 224          gen6_3d_translate_pipe_prim(vec->draw->mode));
 225
 226    for (i = 0; i < vec->ve->vb_count; i++) {
 227       gen8_3DSTATE_VF_INSTANCING(r->builder, i,
 228             vec->ve->instance_divisors[i]);
 229    }
 230
 231    if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF_SGVS)
 232       gen8_3DSTATE_VF_SGVS(r->builder, &vec->ve->vf);
 233 }
 234
 235 void
 236 ilo_render_emit_draw_commands_gen8(struct ilo_render *render,
 237                                    const struct ilo_state_vector *vec,
 238                                    struct ilo_render_draw_session *session)
 239 {
 240    ILO_DEV_ASSERT(render->dev, 8, 8);
 241
 242    /*
 243     * We try to keep the order of the commands match, as closely as possible,
 244     * that of the classic i965 driver.  It allows us to compare the command
 245     * streams easily.
 246     */
 247    gen6_draw_common_select(render, vec, session);
 248    gen6_draw_common_sip(render, vec, session);
 249    gen6_draw_vf_statistics(render, vec, session);
 250    gen8_draw_wm_sample_pattern(render, vec, session);
 251    gen6_draw_common_base_address(render, vec, session);
 252    gen7_draw_common_pointers_1(render, vec, session);
 253    gen7_draw_common_pcb_alloc(render, vec, session);
 254    gen7_draw_common_urb(render, vec, session);
 255    gen7_draw_common_pointers_2(render, vec, session);
 256    gen8_draw_wm_multisample(render, vec, session);
 257    gen7_draw_gs(render, vec, session);
 258    gen7_draw_hs(render, vec, session);
 259    gen7_draw_te(render, vec, session);
 260    gen7_draw_ds(render, vec, session);
 261    gen7_draw_vs(render, vec, session);
 262    gen7_draw_sol(render, vec, session);
 263    gen6_draw_clip(render, vec, session);
 264    gen8_draw_sf(render, vec, session);
 265    gen8_draw_wm(render, vec, session);
 266    gen6_draw_wm_raster(render, vec, session);
 267    gen6_draw_sf_rect(render, vec, session);
 268    gen8_draw_vf(render, vec, session);
 269
 270    ilo_render_3dprimitive(render, vec->draw, &vec->ib);
 271 }
 272
 273 int
 274 ilo_render_get_draw_commands_len_gen8(const struct ilo_render *render,
 275                                       const struct ilo_state_vector *vec)
 276 {
 277    static int len;
 278
 279    ILO_DEV_ASSERT(render->dev, 8, 8);
 280
 281    if (!len) {
 282       len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
 283       len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
 284       len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
 285       len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
 286       len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
 287       len += GEN6_PIPE_CONTROL__SIZE * 5;
 288
 289       len +=
 290          GEN6_STATE_BASE_ADDRESS__SIZE +
 291          GEN6_STATE_SIP__SIZE +
 292          GEN6_3DSTATE_VF_STATISTICS__SIZE +
 293          GEN6_PIPELINE_SELECT__SIZE +
 294          GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
 295          GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
 296          GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
 297          GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
 298          GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
 299          GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
 300          GEN6_3DSTATE_INDEX_BUFFER__SIZE +
 301          GEN75_3DSTATE_VF__SIZE +
 302          GEN6_3DSTATE_VS__SIZE +
 303          GEN6_3DSTATE_GS__SIZE +
 304          GEN6_3DSTATE_CLIP__SIZE +
 305          GEN6_3DSTATE_SF__SIZE +
 306          GEN6_3DSTATE_WM__SIZE +
 307          GEN6_3DSTATE_SAMPLE_MASK__SIZE +
 308          GEN7_3DSTATE_HS__SIZE +
 309          GEN7_3DSTATE_TE__SIZE +
 310          GEN7_3DSTATE_DS__SIZE +
 311          GEN7_3DSTATE_STREAMOUT__SIZE +
 312          GEN7_3DSTATE_SBE__SIZE +
 313          GEN7_3DSTATE_PS__SIZE +
 314          GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
 315          GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
 316          GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
 317          GEN6_3DSTATE_LINE_STIPPLE__SIZE +
 318          GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
 319          GEN6_3DSTATE_MULTISAMPLE__SIZE +
 320          GEN7_3DSTATE_SO_DECL_LIST__SIZE +
 321          GEN6_3DPRIMITIVE__SIZE;
 322
 323       len +=
 324          GEN8_3DSTATE_VF_INSTANCING__SIZE * 33 +
 325          GEN8_3DSTATE_VF_SGVS__SIZE +
 326          GEN8_3DSTATE_VF_TOPOLOGY__SIZE +
 327          GEN8_3DSTATE_SBE_SWIZ__SIZE +
 328          GEN8_3DSTATE_RASTER__SIZE +
 329          GEN8_3DSTATE_WM_CHROMAKEY__SIZE +
 330          GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE +
 331          GEN8_3DSTATE_WM_HZ_OP__SIZE +
 332          GEN8_3DSTATE_PS_EXTRA__SIZE +
 333          GEN8_3DSTATE_PS_BLEND__SIZE +
 334          GEN8_3DSTATE_SAMPLE_PATTERN__SIZE;
 335    }
 336
 337    return len;
 338 }
 339
 340 int
 341 ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render *render,
 342                                           const struct ilo_blitter *blitter)
 343 {
 344    ILO_DEV_ASSERT(render->dev, 8, 8);
 345
 346    return 96;
 347 }
 348
 349 void
 350 ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
 351                                        const struct ilo_blitter *blitter,
 352                                        const struct ilo_render_rectlist_session *session)
 353 {
 354    ILO_DEV_ASSERT(r->dev, 8, 8);
 355
 356    gen8_wa_pre_depth(r);
 357
 358    if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
 359                         ILO_BLITTER_USE_FB_STENCIL))
 360       gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
 361
 362    if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
 363       gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
 364             &blitter->fb.dst.u.zs);
 365    }
 366
 367    if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
 368       gen6_3DSTATE_STENCIL_BUFFER(r->builder,
 369             &blitter->fb.dst.u.zs);
 370    }
 371
 372    gen7_3DSTATE_CLEAR_PARAMS(r->builder,
 373          blitter->depth_clear_value);
 374
 375    gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
 376          blitter->fb.width, blitter->fb.height);
 377
 378    gen8_3DSTATE_WM_HZ_OP(r->builder, &blitter->fb.rs,
 379          blitter->fb.width, blitter->fb.height);
 380
 381    ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
 382
 383    gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
 384 }