ilo: move ilo_layout.[ch] to core as ilo_image.[ch]
[mesa.git] / src / gallium / drivers / ilo / ilo_resource.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2012-2013 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "ilo_screen.h"
29 #include "ilo_resource.h"
30
31 /*
32 * From the Ivy Bridge PRM, volume 1 part 1, page 105:
33 *
34 * "In addition to restrictions on maximum height, width, and depth,
35 * surfaces are also restricted to a maximum size in bytes. This
36 * maximum is 2 GB for all products and all surface types."
37 */
38 static const size_t ilo_max_resource_size = 1u << 31;
39
40 static const char *
41 resource_get_bo_name(const struct pipe_resource *templ)
42 {
43 static const char *target_names[PIPE_MAX_TEXTURE_TYPES] = {
44 [PIPE_BUFFER] = "buf",
45 [PIPE_TEXTURE_1D] = "tex-1d",
46 [PIPE_TEXTURE_2D] = "tex-2d",
47 [PIPE_TEXTURE_3D] = "tex-3d",
48 [PIPE_TEXTURE_CUBE] = "tex-cube",
49 [PIPE_TEXTURE_RECT] = "tex-rect",
50 [PIPE_TEXTURE_1D_ARRAY] = "tex-1d-array",
51 [PIPE_TEXTURE_2D_ARRAY] = "tex-2d-array",
52 [PIPE_TEXTURE_CUBE_ARRAY] = "tex-cube-array",
53 };
54 const char *name = target_names[templ->target];
55
56 if (templ->target == PIPE_BUFFER) {
57 switch (templ->bind) {
58 case PIPE_BIND_VERTEX_BUFFER:
59 name = "buf-vb";
60 break;
61 case PIPE_BIND_INDEX_BUFFER:
62 name = "buf-ib";
63 break;
64 case PIPE_BIND_CONSTANT_BUFFER:
65 name = "buf-cb";
66 break;
67 case PIPE_BIND_STREAM_OUTPUT:
68 name = "buf-so";
69 break;
70 default:
71 break;
72 }
73 }
74
75 return name;
76 }
77
78 static bool
79 resource_get_cpu_init(const struct pipe_resource *templ)
80 {
81 return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
82 PIPE_BIND_RENDER_TARGET |
83 PIPE_BIND_STREAM_OUTPUT)) ? false : true;
84 }
85
86 static enum gen_surface_tiling
87 winsys_to_surface_tiling(enum intel_tiling_mode tiling)
88 {
89 switch (tiling) {
90 case INTEL_TILING_NONE:
91 return GEN6_TILING_NONE;
92 case INTEL_TILING_X:
93 return GEN6_TILING_X;
94 case INTEL_TILING_Y:
95 return GEN6_TILING_Y;
96 default:
97 assert(!"unknown tiling");
98 return GEN6_TILING_NONE;
99 }
100 }
101
102 static inline enum intel_tiling_mode
103 surface_to_winsys_tiling(enum gen_surface_tiling tiling)
104 {
105 switch (tiling) {
106 case GEN6_TILING_NONE:
107 return INTEL_TILING_NONE;
108 case GEN6_TILING_X:
109 return INTEL_TILING_X;
110 case GEN6_TILING_Y:
111 return INTEL_TILING_Y;
112 default:
113 assert(!"unknown tiling");
114 return GEN6_TILING_NONE;
115 }
116 }
117
118 static void
119 tex_free_slices(struct ilo_texture *tex)
120 {
121 FREE(tex->slices[0]);
122 }
123
124 static bool
125 tex_alloc_slices(struct ilo_texture *tex)
126 {
127 const struct pipe_resource *templ = &tex->base;
128 struct ilo_texture_slice *slices;
129 int depth, lv;
130
131 /* sum the depths of all levels */
132 depth = 0;
133 for (lv = 0; lv <= templ->last_level; lv++)
134 depth += u_minify(templ->depth0, lv);
135
136 /*
137 * There are (depth * tex->base.array_size) slices in total. Either depth
138 * is one (non-3D) or templ->array_size is one (non-array), but it does
139 * not matter.
140 */
141 slices = CALLOC(depth * templ->array_size, sizeof(*slices));
142 if (!slices)
143 return false;
144
145 tex->slices[0] = slices;
146
147 /* point to the respective positions in the buffer */
148 for (lv = 1; lv <= templ->last_level; lv++) {
149 tex->slices[lv] = tex->slices[lv - 1] +
150 u_minify(templ->depth0, lv - 1) * templ->array_size;
151 }
152
153 return true;
154 }
155
156 static bool
157 tex_import_handle(struct ilo_texture *tex,
158 const struct winsys_handle *handle)
159 {
160 struct ilo_screen *is = ilo_screen(tex->base.screen);
161 const char *name = resource_get_bo_name(&tex->base);
162 enum intel_tiling_mode tiling;
163 unsigned long pitch;
164
165 tex->bo = intel_winsys_import_handle(is->dev.winsys, name, handle,
166 tex->image.bo_height, &tiling, &pitch);
167 if (!tex->bo)
168 return false;
169
170 if (!ilo_image_update_for_imported_bo(&tex->image,
171 winsys_to_surface_tiling(tiling), pitch)) {
172 ilo_err("imported handle has incompatible tiling/pitch\n");
173 intel_bo_unref(tex->bo);
174 tex->bo = NULL;
175 return false;
176 }
177
178 return true;
179 }
180
181 static bool
182 tex_create_bo(struct ilo_texture *tex)
183 {
184 struct ilo_screen *is = ilo_screen(tex->base.screen);
185 const char *name = resource_get_bo_name(&tex->base);
186 const bool cpu_init = resource_get_cpu_init(&tex->base);
187 struct intel_bo *bo;
188
189 bo = intel_winsys_alloc_bo(is->dev.winsys, name,
190 tex->image.bo_stride * tex->image.bo_height, cpu_init);
191
192 /* set the tiling for transfer and export */
193 if (bo && (tex->image.tiling == GEN6_TILING_X ||
194 tex->image.tiling == GEN6_TILING_Y)) {
195 const enum intel_tiling_mode tiling =
196 surface_to_winsys_tiling(tex->image.tiling);
197
198 if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) {
199 intel_bo_unref(bo);
200 bo = NULL;
201 }
202 }
203
204 tex->bo = bo;
205
206 return (tex->bo != NULL);
207 }
208
209 static bool
210 tex_create_separate_stencil(struct ilo_texture *tex)
211 {
212 struct pipe_resource templ = tex->base;
213 struct pipe_resource *s8;
214
215 /*
216 * Unless PIPE_BIND_DEPTH_STENCIL is set, the resource may have other
217 * tilings. But that should be fine since it will never be bound as the
218 * stencil buffer, and our transfer code can handle all tilings.
219 */
220 templ.format = PIPE_FORMAT_S8_UINT;
221
222 /* no stencil texturing */
223 templ.bind &= ~PIPE_BIND_SAMPLER_VIEW;
224
225 s8 = tex->base.screen->resource_create(tex->base.screen, &templ);
226 if (!s8)
227 return false;
228
229 tex->separate_s8 = ilo_texture(s8);
230
231 assert(tex->separate_s8->image.format == PIPE_FORMAT_S8_UINT);
232
233 return true;
234 }
235
236 static bool
237 tex_create_hiz(struct ilo_texture *tex)
238 {
239 const struct pipe_resource *templ = &tex->base;
240 struct ilo_screen *is = ilo_screen(tex->base.screen);
241 unsigned lv;
242
243 tex->aux_bo = intel_winsys_alloc_bo(is->dev.winsys, "hiz texture",
244 tex->image.aux_stride * tex->image.aux_height, false);
245 if (!tex->aux_bo)
246 return false;
247
248 for (lv = 0; lv <= templ->last_level; lv++) {
249 if (tex->image.aux_enables & (1 << lv)) {
250 const unsigned num_slices = (templ->target == PIPE_TEXTURE_3D) ?
251 u_minify(templ->depth0, lv) : templ->array_size;
252 unsigned flags = ILO_TEXTURE_HIZ;
253
254 /* this will trigger a HiZ resolve */
255 if (tex->imported)
256 flags |= ILO_TEXTURE_CPU_WRITE;
257
258 ilo_texture_set_slice_flags(tex, lv, 0, num_slices, flags, flags);
259 }
260 }
261
262 return true;
263 }
264
265 static bool
266 tex_create_mcs(struct ilo_texture *tex)
267 {
268 struct ilo_screen *is = ilo_screen(tex->base.screen);
269
270 assert(tex->image.aux_enables == (1 << (tex->base.last_level + 1)) - 1);
271
272 tex->aux_bo = intel_winsys_alloc_bo(is->dev.winsys, "mcs texture",
273 tex->image.aux_stride * tex->image.aux_height, false);
274 if (!tex->aux_bo)
275 return false;
276
277 return true;
278 }
279
280 static void
281 tex_destroy(struct ilo_texture *tex)
282 {
283 if (tex->separate_s8)
284 tex_destroy(tex->separate_s8);
285
286 intel_bo_unref(tex->aux_bo);
287 intel_bo_unref(tex->bo);
288
289 tex_free_slices(tex);
290 FREE(tex);
291 }
292
293 static bool
294 tex_alloc_bos(struct ilo_texture *tex,
295 const struct winsys_handle *handle)
296 {
297 struct ilo_screen *is = ilo_screen(tex->base.screen);
298
299 if (handle) {
300 if (!tex_import_handle(tex, handle))
301 return false;
302 } else {
303 if (!tex_create_bo(tex))
304 return false;
305 }
306
307 /* allocate separate stencil resource */
308 if (tex->image.separate_stencil && !tex_create_separate_stencil(tex))
309 return false;
310
311 switch (tex->image.aux) {
312 case ILO_IMAGE_AUX_HIZ:
313 if (!tex_create_hiz(tex)) {
314 /* Separate Stencil Buffer requires HiZ to be enabled */
315 if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
316 tex->image.separate_stencil)
317 return false;
318 }
319 break;
320 case ILO_IMAGE_AUX_MCS:
321 if (!tex_create_mcs(tex))
322 return false;
323 break;
324 default:
325 break;
326 }
327
328 return true;
329 }
330
331 static bool
332 tex_init_image(struct ilo_texture *tex)
333 {
334 struct ilo_screen *is = ilo_screen(tex->base.screen);
335 const struct pipe_resource *templ = &tex->base;
336 struct ilo_image *img = &tex->image;
337
338 ilo_image_init(img, &is->dev, templ);
339
340 if (img->bo_height > ilo_max_resource_size / img->bo_stride)
341 return false;
342
343 if (templ->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
344 /* require on-the-fly tiling/untiling or format conversion */
345 if (img->tiling == GEN8_TILING_W || img->separate_stencil ||
346 img->format != templ->format)
347 return false;
348 }
349
350 if (!tex_alloc_slices(tex))
351 return false;
352
353 return true;
354 }
355
356 static struct pipe_resource *
357 tex_create(struct pipe_screen *screen,
358 const struct pipe_resource *templ,
359 const struct winsys_handle *handle)
360 {
361 struct ilo_texture *tex;
362
363 tex = CALLOC_STRUCT(ilo_texture);
364 if (!tex)
365 return NULL;
366
367 tex->base = *templ;
368 tex->base.screen = screen;
369 pipe_reference_init(&tex->base.reference, 1);
370
371 tex->imported = (handle != NULL);
372
373 if (!tex_init_image(tex)) {
374 FREE(tex);
375 return NULL;
376 }
377
378 if (!tex_alloc_bos(tex, handle)) {
379 tex_destroy(tex);
380 return NULL;
381 }
382
383 return &tex->base;
384 }
385
386 static bool
387 tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle)
388 {
389 struct ilo_screen *is = ilo_screen(tex->base.screen);
390 enum intel_tiling_mode tiling;
391 int err;
392
393 /* must match what tex_create_bo() sets */
394 if (tex->image.tiling == GEN8_TILING_W)
395 tiling = INTEL_TILING_NONE;
396 else
397 tiling = surface_to_winsys_tiling(tex->image.tiling);
398
399 err = intel_winsys_export_handle(is->dev.winsys, tex->bo, tiling,
400 tex->image.bo_stride, tex->image.bo_height, handle);
401
402 return !err;
403 }
404
405 static bool
406 buf_create_bo(struct ilo_buffer *buf)
407 {
408 struct ilo_screen *is = ilo_screen(buf->base.screen);
409 const char *name = resource_get_bo_name(&buf->base);
410 const bool cpu_init = resource_get_cpu_init(&buf->base);
411
412 buf->bo = intel_winsys_alloc_bo(is->dev.winsys, name, buf->bo_size, cpu_init);
413
414 return (buf->bo != NULL);
415 }
416
417 static void
418 buf_destroy(struct ilo_buffer *buf)
419 {
420 intel_bo_unref(buf->bo);
421 FREE(buf);
422 }
423
424 static struct pipe_resource *
425 buf_create(struct pipe_screen *screen, const struct pipe_resource *templ)
426 {
427 const struct ilo_screen *is = ilo_screen(screen);
428 struct ilo_buffer *buf;
429
430 buf = CALLOC_STRUCT(ilo_buffer);
431 if (!buf)
432 return NULL;
433
434 buf->base = *templ;
435 buf->base.screen = screen;
436 pipe_reference_init(&buf->base.reference, 1);
437
438 buf->bo_size = templ->width0;
439
440 /*
441 * From the Sandy Bridge PRM, volume 1 part 1, page 118:
442 *
443 * "For buffers, which have no inherent "height," padding requirements
444 * are different. A buffer must be padded to the next multiple of 256
445 * array elements, with an additional 16 bytes added beyond that to
446 * account for the L1 cache line."
447 */
448 if (templ->bind & PIPE_BIND_SAMPLER_VIEW)
449 buf->bo_size = align(buf->bo_size, 256) + 16;
450
451 if ((templ->bind & PIPE_BIND_VERTEX_BUFFER) &&
452 ilo_dev_gen(&is->dev) < ILO_GEN(7.5)) {
453 /*
454 * As noted in ilo_format_translate(), we treat some 3-component formats
455 * as 4-component formats to work around hardware limitations. Imagine
456 * the case where the vertex buffer holds a single
457 * PIPE_FORMAT_R16G16B16_FLOAT vertex, and buf->bo_size is 6. The
458 * hardware would fail to fetch it at boundary check because the vertex
459 * buffer is expected to hold a PIPE_FORMAT_R16G16B16A16_FLOAT vertex
460 * and that takes at least 8 bytes.
461 *
462 * For the workaround to work, we should add 2 to the bo size. But that
463 * would waste a page when the bo size is already page aligned. Let's
464 * round it to page size for now and revisit this when needed.
465 */
466 buf->bo_size = align(buf->bo_size, 4096);
467 }
468
469 if (buf->bo_size < templ->width0 ||
470 buf->bo_size > ilo_max_resource_size ||
471 !buf_create_bo(buf)) {
472 FREE(buf);
473 return NULL;
474 }
475
476 return &buf->base;
477 }
478
479 static boolean
480 ilo_can_create_resource(struct pipe_screen *screen,
481 const struct pipe_resource *templ)
482 {
483 struct ilo_image img;
484
485 if (templ->target == PIPE_BUFFER)
486 return (templ->width0 <= ilo_max_resource_size);
487
488 memset(&img, 0, sizeof(img));
489 ilo_image_init(&img, &ilo_screen(screen)->dev, templ);
490
491 return (img.bo_height <= ilo_max_resource_size / img.bo_stride);
492 }
493
494 static struct pipe_resource *
495 ilo_resource_create(struct pipe_screen *screen,
496 const struct pipe_resource *templ)
497 {
498 if (templ->target == PIPE_BUFFER)
499 return buf_create(screen, templ);
500 else
501 return tex_create(screen, templ, NULL);
502 }
503
504 static struct pipe_resource *
505 ilo_resource_from_handle(struct pipe_screen *screen,
506 const struct pipe_resource *templ,
507 struct winsys_handle *handle)
508 {
509 if (templ->target == PIPE_BUFFER)
510 return NULL;
511 else
512 return tex_create(screen, templ, handle);
513 }
514
515 static boolean
516 ilo_resource_get_handle(struct pipe_screen *screen,
517 struct pipe_resource *res,
518 struct winsys_handle *handle)
519 {
520 if (res->target == PIPE_BUFFER)
521 return false;
522 else
523 return tex_get_handle(ilo_texture(res), handle);
524
525 }
526
527 static void
528 ilo_resource_destroy(struct pipe_screen *screen,
529 struct pipe_resource *res)
530 {
531 if (res->target == PIPE_BUFFER)
532 buf_destroy(ilo_buffer(res));
533 else
534 tex_destroy(ilo_texture(res));
535 }
536
537 /**
538 * Initialize resource-related functions.
539 */
540 void
541 ilo_init_resource_functions(struct ilo_screen *is)
542 {
543 is->base.can_create_resource = ilo_can_create_resource;
544 is->base.resource_create = ilo_resource_create;
545 is->base.resource_from_handle = ilo_resource_from_handle;
546 is->base.resource_get_handle = ilo_resource_get_handle;
547 is->base.resource_destroy = ilo_resource_destroy;
548 }
549
550 bool
551 ilo_buffer_rename_bo(struct ilo_buffer *buf)
552 {
553 struct intel_bo *old_bo = buf->bo;
554
555 if (buf_create_bo(buf)) {
556 intel_bo_unref(old_bo);
557 return true;
558 }
559 else {
560 buf->bo = old_bo;
561 return false;
562 }
563 }
564
565 bool
566 ilo_texture_rename_bo(struct ilo_texture *tex)
567 {
568 struct intel_bo *old_bo = tex->bo;
569
570 /* an imported texture cannot be renamed */
571 if (tex->imported)
572 return false;
573
574 if (tex_create_bo(tex)) {
575 intel_bo_unref(old_bo);
576 return true;
577 }
578 else {
579 tex->bo = old_bo;
580 return false;
581 }
582 }