2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "pipe/p_state.h"
29 #include "os/os_misc.h"
30 #include "util/u_format_s3tc.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
34 #include "core/intel_winsys.h"
36 #include "ilo_context.h"
37 #include "ilo_format.h"
38 #include "ilo_resource.h"
39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
40 #include "ilo_public.h"
41 #include "ilo_screen.h"
44 struct pipe_reference reference
;
49 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
52 case PIPE_CAPF_MAX_LINE_WIDTH
:
53 /* in U3.7, defined in 3DSTATE_SF */
55 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
56 /* line width minus one, which is reserved for AA region */
58 case PIPE_CAPF_MAX_POINT_WIDTH
:
59 /* in U8.3, defined in 3DSTATE_SF */
61 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
62 /* same as point width, as we ignore rasterizer->point_smooth */
64 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
65 /* [2.0, 16.0], defined in SAMPLER_STATE */
67 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
68 /* [-16.0, 16.0), defined in SAMPLER_STATE */
70 case PIPE_CAPF_GUARD_BAND_LEFT
:
71 case PIPE_CAPF_GUARD_BAND_TOP
:
72 case PIPE_CAPF_GUARD_BAND_RIGHT
:
73 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
74 /* what are these for? */
83 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
84 enum pipe_shader_cap param
)
87 case PIPE_SHADER_FRAGMENT
:
88 case PIPE_SHADER_VERTEX
:
89 case PIPE_SHADER_GEOMETRY
:
96 /* the limits are copied from the classic driver */
97 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
98 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
99 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
100 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
101 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
102 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
103 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
104 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
105 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
107 case PIPE_SHADER_CAP_MAX_INPUTS
:
108 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
109 /* this is limited by how many attributes SF can remap */
111 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
112 return 1024 * sizeof(float[4]);
113 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
114 return ILO_MAX_CONST_BUFFERS
;
115 case PIPE_SHADER_CAP_MAX_TEMPS
:
117 case PIPE_SHADER_CAP_MAX_PREDS
:
119 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
121 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
123 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
125 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
126 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
127 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
129 case PIPE_SHADER_CAP_SUBROUTINES
:
131 case PIPE_SHADER_CAP_INTEGERS
:
133 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
134 return ILO_MAX_SAMPLERS
;
135 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
136 return ILO_MAX_SAMPLER_VIEWS
;
137 case PIPE_SHADER_CAP_PREFERRED_IR
:
138 return PIPE_SHADER_IR_TGSI
;
139 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
148 ilo_get_video_param(struct pipe_screen
*screen
,
149 enum pipe_video_profile profile
,
150 enum pipe_video_entrypoint entrypoint
,
151 enum pipe_video_cap param
)
154 case PIPE_VIDEO_CAP_SUPPORTED
:
155 return vl_profile_supported(screen
, profile
, entrypoint
);
156 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
158 case PIPE_VIDEO_CAP_MAX_WIDTH
:
159 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
160 return vl_video_buffer_max_size(screen
);
161 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
162 return PIPE_FORMAT_NV12
;
163 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
165 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
167 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
169 case PIPE_VIDEO_CAP_MAX_LEVEL
:
170 return vl_level_supported(screen
, profile
);
177 ilo_get_compute_param(struct pipe_screen
*screen
,
178 enum pipe_compute_cap param
,
181 struct ilo_screen
*is
= ilo_screen(screen
);
183 const char *ir_target
;
184 uint64_t grid_dimension
;
185 uint64_t max_grid_size
[3];
186 uint64_t max_block_size
[3];
187 uint64_t max_threads_per_block
;
188 uint64_t max_global_size
;
189 uint64_t max_local_size
;
190 uint64_t max_private_size
;
191 uint64_t max_input_size
;
192 uint64_t max_mem_alloc_size
;
193 uint32_t max_clock_frequency
;
194 uint32_t max_compute_units
;
195 uint32_t images_supported
;
201 case PIPE_COMPUTE_CAP_IR_TARGET
:
202 val
.ir_target
= "ilog";
205 size
= strlen(val
.ir_target
) + 1;
207 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
208 val
.grid_dimension
= Elements(val
.max_grid_size
);
210 ptr
= &val
.grid_dimension
;
211 size
= sizeof(val
.grid_dimension
);
213 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
214 val
.max_grid_size
[0] = 0xffffffffu
;
215 val
.max_grid_size
[1] = 0xffffffffu
;
216 val
.max_grid_size
[2] = 0xffffffffu
;
218 ptr
= &val
.max_grid_size
;
219 size
= sizeof(val
.max_grid_size
);
221 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
222 val
.max_block_size
[0] = 1024;
223 val
.max_block_size
[1] = 1024;
224 val
.max_block_size
[2] = 1024;
226 ptr
= &val
.max_block_size
;
227 size
= sizeof(val
.max_block_size
);
230 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
231 val
.max_threads_per_block
= 1024;
233 ptr
= &val
.max_threads_per_block
;
234 size
= sizeof(val
.max_threads_per_block
);
236 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
237 /* \see ilo_max_resource_size */
238 val
.max_global_size
= 1u << 31;
240 ptr
= &val
.max_global_size
;
241 size
= sizeof(val
.max_global_size
);
243 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
244 /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
245 val
.max_local_size
= 64 * 1024;
247 ptr
= &val
.max_local_size
;
248 size
= sizeof(val
.max_local_size
);
250 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
252 val
.max_private_size
= 12 * 1024;
254 ptr
= &val
.max_private_size
;
255 size
= sizeof(val
.max_private_size
);
257 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
258 val
.max_input_size
= 1024;
260 ptr
= &val
.max_input_size
;
261 size
= sizeof(val
.max_input_size
);
263 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
264 val
.max_mem_alloc_size
= 1u << 31;
266 ptr
= &val
.max_mem_alloc_size
;
267 size
= sizeof(val
.max_mem_alloc_size
);
269 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
270 val
.max_clock_frequency
= 1000;
272 ptr
= &val
.max_clock_frequency
;
273 size
= sizeof(val
.max_clock_frequency
);
275 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
276 val
.max_compute_units
= is
->dev
.eu_count
;
278 ptr
= &val
.max_compute_units
;
279 size
= sizeof(val
.max_compute_units
);
281 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
282 val
.images_supported
= 1;
284 ptr
= &val
.images_supported
;
285 size
= sizeof(val
.images_supported
);
294 memcpy(ret
, ptr
, size
);
300 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
302 struct ilo_screen
*is
= ilo_screen(screen
);
305 case PIPE_CAP_NPOT_TEXTURES
:
306 case PIPE_CAP_TWO_SIDED_STENCIL
:
308 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
310 case PIPE_CAP_ANISOTROPIC_FILTER
:
311 case PIPE_CAP_POINT_SPRITE
:
313 case PIPE_CAP_MAX_RENDER_TARGETS
:
314 return ILO_MAX_DRAW_BUFFERS
;
315 case PIPE_CAP_OCCLUSION_QUERY
:
316 case PIPE_CAP_QUERY_TIME_ELAPSED
:
317 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
318 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
320 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
322 * As defined in SURFACE_STATE, we have
324 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
325 * GEN6 8192x8192x512 2048x2048x2048
326 * GEN7 16384x16384x2048 2048x2048x2048
328 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
329 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
331 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
332 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
333 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
335 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
338 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
339 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
341 return ILO_MAX_SO_BUFFERS
;
342 case PIPE_CAP_PRIMITIVE_RESTART
:
344 case PIPE_CAP_INDEP_BLEND_ENABLE
:
345 case PIPE_CAP_INDEP_BLEND_FUNC
:
347 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
348 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 2048 : 512;
349 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
350 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
351 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
352 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
353 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
355 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
357 case PIPE_CAP_TGSI_INSTANCEID
:
358 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
360 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
362 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
364 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
365 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
367 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
368 case PIPE_CAP_MIN_TEXEL_OFFSET
:
370 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
371 case PIPE_CAP_MAX_TEXEL_OFFSET
:
373 case PIPE_CAP_CONDITIONAL_RENDER
:
374 case PIPE_CAP_TEXTURE_BARRIER
:
376 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
377 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
378 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
379 return ILO_MAX_SO_BINDINGS
;
380 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
381 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7))
382 return is
->dev
.has_gen7_sol_reset
;
384 return false; /* TODO */
385 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
387 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
389 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
391 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
393 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
394 case PIPE_CAP_USER_VERTEX_BUFFERS
:
396 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
397 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
398 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
400 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
402 case PIPE_CAP_COMPUTE
:
403 return false; /* TODO */
404 case PIPE_CAP_USER_INDEX_BUFFERS
:
405 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
407 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
408 /* imposed by OWord (Dual) Block Read */
410 case PIPE_CAP_START_INSTANCE
:
412 case PIPE_CAP_QUERY_TIMESTAMP
:
413 return is
->dev
.has_timestamp
;
414 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
415 return false; /* TODO */
416 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
417 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
418 case PIPE_CAP_CUBE_MAP_ARRAY
:
419 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
421 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
423 case PIPE_CAP_TGSI_TEXCOORD
:
425 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
426 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
428 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
430 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
431 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
433 case PIPE_CAP_MAX_VIEWPORTS
:
434 return ILO_MAX_VIEWPORTS
;
435 case PIPE_CAP_ENDIANNESS
:
436 return PIPE_ENDIAN_LITTLE
;
437 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
439 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
440 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
441 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
442 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
443 case PIPE_CAP_TEXTURE_GATHER_SM5
:
445 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
447 case PIPE_CAP_FAKE_SW_MSAA
:
448 case PIPE_CAP_TEXTURE_QUERY_LOD
:
449 case PIPE_CAP_SAMPLE_SHADING
:
450 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
451 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
452 case PIPE_CAP_MAX_VERTEX_STREAMS
:
453 case PIPE_CAP_DRAW_INDIRECT
:
454 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
455 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
456 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
457 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
458 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
461 case PIPE_CAP_VENDOR_ID
:
463 case PIPE_CAP_DEVICE_ID
:
464 return is
->dev
.devid
;
465 case PIPE_CAP_ACCELERATED
:
467 case PIPE_CAP_VIDEO_MEMORY
: {
468 /* Once a batch uses more than 75% of the maximum mappable size, we
469 * assume that there's some fragmentation, and we start doing extra
470 * flushing, etc. That's the big cliff apps will care about.
472 const uint64_t gpu_memory
= is
->dev
.aperture_total
* 3 / 4;
473 uint64_t system_memory
;
475 if (!os_get_total_physical_memory(&system_memory
))
478 return (int) (MIN2(gpu_memory
, system_memory
) >> 20);
482 case PIPE_CAP_CLIP_HALFZ
:
484 case PIPE_CAP_VERTEXID_NOBASE
:
486 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
495 ilo_get_vendor(struct pipe_screen
*screen
)
497 return "LunarG, Inc.";
501 ilo_get_device_vendor(struct pipe_screen
*screen
)
507 ilo_get_name(struct pipe_screen
*screen
)
509 struct ilo_screen
*is
= ilo_screen(screen
);
510 const char *chipset
= NULL
;
512 if (gen_is_chv(is
->dev
.devid
)) {
513 chipset
= "Intel(R) Cherryview";
514 } else if (gen_is_bdw(is
->dev
.devid
)) {
515 /* this is likely wrong */
516 if (gen_is_desktop(is
->dev
.devid
))
517 chipset
= "Intel(R) Broadwell Desktop";
518 else if (gen_is_mobile(is
->dev
.devid
))
519 chipset
= "Intel(R) Broadwell Mobile";
520 else if (gen_is_server(is
->dev
.devid
))
521 chipset
= "Intel(R) Broadwell Server";
522 } else if (gen_is_vlv(is
->dev
.devid
)) {
523 chipset
= "Intel(R) Bay Trail";
524 } else if (gen_is_hsw(is
->dev
.devid
)) {
525 if (gen_is_desktop(is
->dev
.devid
))
526 chipset
= "Intel(R) Haswell Desktop";
527 else if (gen_is_mobile(is
->dev
.devid
))
528 chipset
= "Intel(R) Haswell Mobile";
529 else if (gen_is_server(is
->dev
.devid
))
530 chipset
= "Intel(R) Haswell Server";
531 } else if (gen_is_ivb(is
->dev
.devid
)) {
532 if (gen_is_desktop(is
->dev
.devid
))
533 chipset
= "Intel(R) Ivybridge Desktop";
534 else if (gen_is_mobile(is
->dev
.devid
))
535 chipset
= "Intel(R) Ivybridge Mobile";
536 else if (gen_is_server(is
->dev
.devid
))
537 chipset
= "Intel(R) Ivybridge Server";
538 } else if (gen_is_snb(is
->dev
.devid
)) {
539 if (gen_is_desktop(is
->dev
.devid
))
540 chipset
= "Intel(R) Sandybridge Desktop";
541 else if (gen_is_mobile(is
->dev
.devid
))
542 chipset
= "Intel(R) Sandybridge Mobile";
543 else if (gen_is_server(is
->dev
.devid
))
544 chipset
= "Intel(R) Sandybridge Server";
548 chipset
= "Unknown Intel Chipset";
554 ilo_get_timestamp(struct pipe_screen
*screen
)
556 struct ilo_screen
*is
= ilo_screen(screen
);
562 intel_winsys_read_reg(is
->winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
565 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
567 * "Note: This timestamp register reflects the value of the PCU TSC.
568 * The PCU TSC counts 10ns increments; this timestamp reflects bits
569 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
572 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
573 * of the timestamp. We will have to live with a timestamp that rolls over
574 * every ~343 seconds.
576 * See also brw_get_timestamp().
578 return (uint64_t) timestamp
.dw
[1] * 80;
582 ilo_fence_reference(struct pipe_screen
*screen
,
583 struct pipe_fence_handle
**p
,
584 struct pipe_fence_handle
*f
)
586 struct ilo_fence
*fence
= ilo_fence(f
);
587 struct ilo_fence
*old
;
596 STATIC_ASSERT(&((struct ilo_fence
*) NULL
)->reference
== NULL
);
597 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
598 intel_bo_unref(old
->bo
);
604 ilo_fence_signalled(struct pipe_screen
*screen
,
605 struct pipe_fence_handle
*f
)
607 struct ilo_fence
*fence
= ilo_fence(f
);
609 /* mark signalled if the bo is idle */
610 if (fence
->bo
&& !intel_bo_is_busy(fence
->bo
)) {
611 intel_bo_unref(fence
->bo
);
615 return (fence
->bo
== NULL
);
619 ilo_fence_finish(struct pipe_screen
*screen
,
620 struct pipe_fence_handle
*f
,
623 struct ilo_fence
*fence
= ilo_fence(f
);
624 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
626 /* already signalled */
630 /* wait and see if it returns error */
631 if (intel_bo_wait(fence
->bo
, wait_timeout
))
635 intel_bo_unref(fence
->bo
);
642 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
643 * before waited on or checked.
646 ilo_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
648 struct ilo_fence
*fence
;
650 fence
= CALLOC_STRUCT(ilo_fence
);
654 pipe_reference_init(&fence
->reference
, 1);
656 fence
->bo
= intel_bo_ref(bo
);
662 ilo_screen_destroy(struct pipe_screen
*screen
)
664 struct ilo_screen
*is
= ilo_screen(screen
);
666 /* as it seems, winsys is owned by the screen */
667 intel_winsys_destroy(is
->winsys
);
673 init_dev(struct ilo_dev_info
*dev
, const struct intel_winsys_info
*info
)
675 dev
->devid
= info
->devid
;
676 dev
->aperture_total
= info
->aperture_total
;
677 dev
->aperture_mappable
= info
->aperture_mappable
;
678 dev
->has_llc
= info
->has_llc
;
679 dev
->has_address_swizzling
= info
->has_address_swizzling
;
680 dev
->has_logical_context
= info
->has_logical_context
;
681 dev
->has_ppgtt
= info
->has_ppgtt
;
682 dev
->has_timestamp
= info
->has_timestamp
;
683 dev
->has_gen7_sol_reset
= info
->has_gen7_sol_reset
;
685 if (!dev
->has_logical_context
) {
686 ilo_err("missing hardware logical context support\n");
691 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
694 * From the Sandy Bridge PRM, volume 1 part 3, page 101:
696 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
697 * code is in a secure environment, independent of address space.
698 * Under this condition, this bit only specifies the address space
699 * (GGTT or PPGTT). All commands are executed "as-is""
701 * We need PPGTT to be enabled on GEN6 too.
703 if (!dev
->has_ppgtt
) {
704 /* experiments show that it does not really matter... */
705 ilo_warn("PPGTT disabled\n");
708 if (gen_is_bdw(info
->devid
) || gen_is_chv(info
->devid
)) {
709 dev
->gen_opaque
= ILO_GEN(8);
710 dev
->gt
= (gen_is_bdw(info
->devid
)) ? gen_get_bdw_gt(info
->devid
) : 1;
711 /* XXX random values */
714 dev
->thread_count
= 336;
715 dev
->urb_size
= 384 * 1024;
716 } else if (dev
->gt
== 2) {
718 dev
->thread_count
= 168;
719 dev
->urb_size
= 384 * 1024;
722 dev
->thread_count
= 84;
723 dev
->urb_size
= 192 * 1024;
725 } else if (gen_is_hsw(info
->devid
)) {
727 * From the Haswell PRM, volume 4, page 8:
729 * "Description GT3 GT2 GT1.5 GT1
731 * EUs (Total) 40 20 12 10
732 * Threads (Total) 280 140 84 70
734 * URB Size (max, within L3$) 512KB 256KB 256KB 128KB
736 dev
->gen_opaque
= ILO_GEN(7.5);
737 dev
->gt
= gen_get_hsw_gt(info
->devid
);
740 dev
->thread_count
= 280;
741 dev
->urb_size
= 512 * 1024;
742 } else if (dev
->gt
== 2) {
744 dev
->thread_count
= 140;
745 dev
->urb_size
= 256 * 1024;
748 dev
->thread_count
= 70;
749 dev
->urb_size
= 128 * 1024;
751 } else if (gen_is_ivb(info
->devid
) || gen_is_vlv(info
->devid
)) {
753 * From the Ivy Bridge PRM, volume 1 part 1, page 18:
755 * "Device # of EUs #Threads/EU
756 * Ivy Bridge (GT2) 16 8
757 * Ivy Bridge (GT1) 6 6"
759 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
761 * "URB Size URB Rows URB Rows when SLM Enabled
765 dev
->gen_opaque
= ILO_GEN(7);
766 dev
->gt
= (gen_is_ivb(info
->devid
)) ? gen_get_ivb_gt(info
->devid
) : 1;
769 dev
->thread_count
= 128;
770 dev
->urb_size
= 256 * 1024;
773 dev
->thread_count
= 36;
774 dev
->urb_size
= 128 * 1024;
776 } else if (gen_is_snb(info
->devid
)) {
778 * From the Sandy Bridge PRM, volume 1 part 1, page 22:
780 * "Device # of EUs #Threads/EU
784 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
786 * "[DevSNB]: The GT1 product's URB provides 32KB of storage,
787 * arranged as 1024 256-bit rows. The GT2 product's URB provides
788 * 64KB of storage, arranged as 2048 256-bit rows. A row
789 * corresponds in size to an EU GRF register. Read/write access to
790 * the URB is generally supported on a row-granular basis."
792 dev
->gen_opaque
= ILO_GEN(6);
793 dev
->gt
= gen_get_snb_gt(info
->devid
);
796 dev
->thread_count
= 60;
797 dev
->urb_size
= 64 * 1024;
800 dev
->thread_count
= 24;
801 dev
->urb_size
= 32 * 1024;
804 ilo_err("unknown GPU generation\n");
812 ilo_screen_create(struct intel_winsys
*ws
)
814 struct ilo_screen
*is
;
815 const struct intel_winsys_info
*info
;
817 ilo_debug_init("ILO_DEBUG");
819 is
= CALLOC_STRUCT(ilo_screen
);
825 info
= intel_winsys_get_info(is
->winsys
);
826 if (!init_dev(&is
->dev
, info
)) {
831 util_format_s3tc_init();
833 is
->base
.destroy
= ilo_screen_destroy
;
834 is
->base
.get_name
= ilo_get_name
;
835 is
->base
.get_vendor
= ilo_get_vendor
;
836 is
->base
.get_device_vendor
= ilo_get_device_vendor
;
837 is
->base
.get_param
= ilo_get_param
;
838 is
->base
.get_paramf
= ilo_get_paramf
;
839 is
->base
.get_shader_param
= ilo_get_shader_param
;
840 is
->base
.get_video_param
= ilo_get_video_param
;
841 is
->base
.get_compute_param
= ilo_get_compute_param
;
843 is
->base
.get_timestamp
= ilo_get_timestamp
;
845 is
->base
.flush_frontbuffer
= NULL
;
847 is
->base
.fence_reference
= ilo_fence_reference
;
848 is
->base
.fence_signalled
= ilo_fence_signalled
;
849 is
->base
.fence_finish
= ilo_fence_finish
;
851 is
->base
.get_driver_query_info
= NULL
;
853 ilo_init_format_functions(is
);
854 ilo_init_context_functions(is
);
855 ilo_init_resource_functions(is
);