src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "intel_chipset.h"
  32 #include "intel_reg.h" /* for TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_public.h"
  39 #include "ilo_screen.h"
  40
  41 int ilo_debug;
  42
  43 static const struct debug_named_value ilo_debug_flags[] = {
  44    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  50    { "flush",     ILO_DEBUG_FLUSH,    "Show batch buffer flushes" },
  51    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  52    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  53    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  54    DEBUG_NAMED_VALUE_END
  55 };
  56
  57 static float
  58 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  59 {
  60    switch (param) {
  61    case PIPE_CAPF_MAX_LINE_WIDTH:
  62       /* in U3.7, defined in 3DSTATE_SF */
  63       return 7.0f;
  64    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  65       /* line width minus one, which is reserved for AA region */
  66       return 6.0f;
  67    case PIPE_CAPF_MAX_POINT_WIDTH:
  68       /* in U8.3, defined in 3DSTATE_SF */
  69       return 255.0f;
  70    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  71       /* same as point width, as we ignore rasterizer->point_smooth */
  72       return 255.0f;
  73    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  74       /* [2.0, 16.0], defined in SAMPLER_STATE */
  75       return 16.0f;
  76    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  77       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  78       return 15.0f;
  79    case PIPE_CAPF_GUARD_BAND_LEFT:
  80    case PIPE_CAPF_GUARD_BAND_TOP:
  81    case PIPE_CAPF_GUARD_BAND_RIGHT:
  82    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  83       /* what are these for? */
  84       return 0.0f;
  85
  86    default:
  87       return 0.0f;
  88    }
  89 }
  90
  91 static int
  92 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  93                      enum pipe_shader_cap param)
  94 {
  95    switch (shader) {
  96    case PIPE_SHADER_FRAGMENT:
  97    case PIPE_SHADER_VERTEX:
  98    case PIPE_SHADER_GEOMETRY:
  99       break;
 100    default:
 101       return 0;
 102    }
 103
 104    switch (param) {
 105    /* the limits are copied from the classic driver */
 106    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 107       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 108    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 109       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 110    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 111       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 112    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 113       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 114    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 115       return UINT_MAX;
 116    case PIPE_SHADER_CAP_MAX_INPUTS:
 117       /* this is limited by how many attributes SF can remap */
 118       return 16;
 119    case PIPE_SHADER_CAP_MAX_CONSTS:
 120       return 1024;
 121    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 122       return ILO_MAX_CONST_BUFFERS;
 123    case PIPE_SHADER_CAP_MAX_TEMPS:
 124       return 256;
 125    case PIPE_SHADER_CAP_MAX_ADDRS:
 126       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 127    case PIPE_SHADER_CAP_MAX_PREDS:
 128       return 0;
 129    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 130       return 1;
 131    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 132       return 0;
 133    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 134       return 0;
 135    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 136       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 137    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 138       return 1;
 139    case PIPE_SHADER_CAP_SUBROUTINES:
 140       return 0;
 141    case PIPE_SHADER_CAP_INTEGERS:
 142       return 1;
 143    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 144       return ILO_MAX_SAMPLERS;
 145    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 146       return ILO_MAX_SAMPLER_VIEWS;
 147    case PIPE_SHADER_CAP_PREFERRED_IR:
 148       return PIPE_SHADER_IR_TGSI;
 149    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 150       return 1;
 151
 152    default:
 153       return 0;
 154    }
 155 }
 156
 157 static int
 158 ilo_get_video_param(struct pipe_screen *screen,
 159                     enum pipe_video_profile profile,
 160                     enum pipe_video_entrypoint entrypoint,
 161                     enum pipe_video_cap param)
 162 {
 163    switch (param) {
 164    case PIPE_VIDEO_CAP_SUPPORTED:
 165       return vl_profile_supported(screen, profile, entrypoint);
 166    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 167       return 1;
 168    case PIPE_VIDEO_CAP_MAX_WIDTH:
 169    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 170       return vl_video_buffer_max_size(screen);
 171    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 172       return PIPE_FORMAT_NV12;
 173    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 174       return 1;
 175    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 176       return 1;
 177    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 178       return 0;
 179    case PIPE_VIDEO_CAP_MAX_LEVEL:
 180       return vl_level_supported(screen, profile);
 181    default:
 182       return 0;
 183    }
 184 }
 185
 186 static int
 187 ilo_get_compute_param(struct pipe_screen *screen,
 188                       enum pipe_compute_cap param,
 189                       void *ret)
 190 {
 191    union {
 192       const char *ir_target;
 193       uint64_t grid_dimension;
 194       uint64_t max_grid_size[3];
 195       uint64_t max_block_size[3];
 196       uint64_t max_threads_per_block;
 197       uint64_t max_global_size;
 198       uint64_t max_local_size;
 199       uint64_t max_private_size;
 200       uint64_t max_input_size;
 201       uint64_t max_mem_alloc_size;
 202    } val;
 203    const void *ptr;
 204    int size;
 205
 206    /* XXX some randomly chosen values */
 207    switch (param) {
 208    case PIPE_COMPUTE_CAP_IR_TARGET:
 209       val.ir_target = "ilog";
 210
 211       ptr = val.ir_target;
 212       size = strlen(val.ir_target) + 1;
 213       break;
 214    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 215       val.grid_dimension = Elements(val.max_grid_size);
 216
 217       ptr = &val.grid_dimension;
 218       size = sizeof(val.grid_dimension);
 219       break;
 220    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 221       val.max_grid_size[0] = 65535;
 222       val.max_grid_size[1] = 65535;
 223       val.max_grid_size[2] = 1;
 224
 225       ptr = &val.max_grid_size;
 226       size = sizeof(val.max_grid_size);
 227       break;
 228    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 229       val.max_block_size[0] = 512;
 230       val.max_block_size[1] = 512;
 231       val.max_block_size[2] = 512;
 232
 233       ptr = &val.max_block_size;
 234       size = sizeof(val.max_block_size);
 235       break;
 236
 237    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 238       val.max_threads_per_block = 512;
 239
 240       ptr = &val.max_threads_per_block;
 241       size = sizeof(val.max_threads_per_block);
 242       break;
 243    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 244       val.max_global_size = 4;
 245
 246       ptr = &val.max_global_size;
 247       size = sizeof(val.max_global_size);
 248       break;
 249    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 250       val.max_local_size = 64 * 1024;
 251
 252       ptr = &val.max_local_size;
 253       size = sizeof(val.max_local_size);
 254       break;
 255    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 256       val.max_private_size = 32768;
 257
 258       ptr = &val.max_private_size;
 259       size = sizeof(val.max_private_size);
 260       break;
 261    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 262       val.max_input_size = 256;
 263
 264       ptr = &val.max_input_size;
 265       size = sizeof(val.max_input_size);
 266       break;
 267    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 268       val.max_mem_alloc_size = 128 * 1024 * 1024;
 269
 270       ptr = &val.max_mem_alloc_size;
 271       size = sizeof(val.max_mem_alloc_size);
 272       break;
 273    default:
 274       ptr = NULL;
 275       size = 0;
 276       break;
 277    }
 278
 279    if (ret)
 280       memcpy(ret, ptr, size);
 281
 282    return size;
 283 }
 284
 285 static int
 286 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 287 {
 288    struct ilo_screen *is = ilo_screen(screen);
 289
 290    switch (param) {
 291    case PIPE_CAP_NPOT_TEXTURES:
 292    case PIPE_CAP_TWO_SIDED_STENCIL:
 293       return true;
 294    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 295       return 0; /* TODO */
 296    case PIPE_CAP_ANISOTROPIC_FILTER:
 297    case PIPE_CAP_POINT_SPRITE:
 298       return true;
 299    case PIPE_CAP_MAX_RENDER_TARGETS:
 300       return ILO_MAX_DRAW_BUFFERS;
 301    case PIPE_CAP_OCCLUSION_QUERY:
 302    case PIPE_CAP_QUERY_TIME_ELAPSED:
 303    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 304    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 305       return true;
 306    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 307       /*
 308        * As defined in SURFACE_STATE, we have
 309        *
 310        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 311        *  GEN6           8192x8192x512            2048x2048x2048
 312        *  GEN7         16384x16384x2048           2048x2048x2048
 313        *
 314        * However, when the texutre size is large, things become unstable.  We
 315        * require the maximum texture size to be 2^30 bytes in
 316        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 317        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 318        * than 2^26 pixels.
 319        *
 320        * For 3D textures, we have to set the maximum number of levels to 9,
 321        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 322        * which has at most 2^26 pixels.  And for cube textures, we has to set
 323        * it to 12.
 324        */
 325       return 14;
 326    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 327       return 9;
 328    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 329       return 12;
 330    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 331       return false;
 332    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 333    case PIPE_CAP_SM3:
 334       return true;
 335    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 336       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 337          return 0;
 338       return ILO_MAX_SO_BUFFERS;
 339    case PIPE_CAP_PRIMITIVE_RESTART:
 340       return true;
 341    case PIPE_CAP_INDEP_BLEND_ENABLE:
 342    case PIPE_CAP_INDEP_BLEND_FUNC:
 343       return true;
 344    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 345       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 346    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 347    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 348    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 349    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 350    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 351       return true;
 352    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 353       return false;
 354    case PIPE_CAP_TGSI_INSTANCEID:
 355    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 356       return true;
 357    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 358       return false;
 359    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 360       return true;
 361    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 362    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 363       return true;
 364    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 365    case PIPE_CAP_MIN_TEXEL_OFFSET:
 366       return -8;
 367    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 368    case PIPE_CAP_MAX_TEXEL_OFFSET:
 369       return 7;
 370    case PIPE_CAP_CONDITIONAL_RENDER:
 371    case PIPE_CAP_TEXTURE_BARRIER:
 372       return true;
 373    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 374       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 375    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 376       return ILO_MAX_SO_BINDINGS;
 377    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 378    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 379       return 0;
 380    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 381       if (is->dev.gen >= ILO_GEN(7))
 382          return is->dev.has_gen7_sol_reset;
 383       else
 384          return false; /* TODO */
 385    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 386       return false;
 387    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 388       return true;
 389    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 390       return false;
 391    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 392       return 140;
 393    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 394    case PIPE_CAP_USER_VERTEX_BUFFERS:
 395       return false;
 396    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 397    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 398    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 399       return false;
 400    case PIPE_CAP_COMPUTE:
 401       return false; /* TODO */
 402    case PIPE_CAP_USER_INDEX_BUFFERS:
 403    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 404       return true;
 405    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 406       /* imposed by OWord (Dual) Block Read */
 407       return 16;
 408    case PIPE_CAP_START_INSTANCE:
 409       return true;
 410    case PIPE_CAP_QUERY_TIMESTAMP:
 411       return is->dev.has_timestamp;
 412    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 413       return false; /* TODO */
 414    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 415       return 64;
 416    case PIPE_CAP_CUBE_MAP_ARRAY:
 417    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 418       return true;
 419    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 420       return 1;
 421    case PIPE_CAP_TGSI_TEXCOORD:
 422       return false;
 423    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 424    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 425       return true;
 426    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 427       return 0;
 428    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 429       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
 430       return 1 << 27;
 431    case PIPE_CAP_MAX_VIEWPORTS:
 432       return ILO_MAX_VIEWPORTS;
 433    case PIPE_CAP_ENDIANNESS:
 434       return PIPE_ENDIAN_LITTLE;
 435    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 436       return true;
 437    case PIPE_CAP_TGSI_VS_LAYER:
 438    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 439    case PIPE_CAP_TEXTURE_GATHER_SM5:
 440    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 441    case PIPE_CAP_FAKE_SW_MSAA:
 442    case PIPE_CAP_TEXTURE_QUERY_LOD:
 443       return 0;
 444
 445    default:
 446       return 0;
 447    }
 448 }
 449
 450 static const char *
 451 ilo_get_vendor(struct pipe_screen *screen)
 452 {
 453    return "LunarG, Inc.";
 454 }
 455
 456 static const char *
 457 ilo_get_name(struct pipe_screen *screen)
 458 {
 459    struct ilo_screen *is = ilo_screen(screen);
 460    const char *chipset;
 461
 462    /* stolen from classic i965 */
 463    switch (is->dev.devid) {
 464    case PCI_CHIP_SANDYBRIDGE_GT1:
 465    case PCI_CHIP_SANDYBRIDGE_GT2:
 466    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 467       chipset = "Intel(R) Sandybridge Desktop";
 468       break;
 469    case PCI_CHIP_SANDYBRIDGE_M_GT1:
 470    case PCI_CHIP_SANDYBRIDGE_M_GT2:
 471    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 472       chipset = "Intel(R) Sandybridge Mobile";
 473       break;
 474    case PCI_CHIP_SANDYBRIDGE_S:
 475       chipset = "Intel(R) Sandybridge Server";
 476       break;
 477    case PCI_CHIP_IVYBRIDGE_GT1:
 478    case PCI_CHIP_IVYBRIDGE_GT2:
 479       chipset = "Intel(R) Ivybridge Desktop";
 480       break;
 481    case PCI_CHIP_IVYBRIDGE_M_GT1:
 482    case PCI_CHIP_IVYBRIDGE_M_GT2:
 483       chipset = "Intel(R) Ivybridge Mobile";
 484       break;
 485    case PCI_CHIP_IVYBRIDGE_S_GT1:
 486    case PCI_CHIP_IVYBRIDGE_S_GT2:
 487       chipset = "Intel(R) Ivybridge Server";
 488       break;
 489    case PCI_CHIP_BAYTRAIL_M_1:
 490    case PCI_CHIP_BAYTRAIL_M_2:
 491    case PCI_CHIP_BAYTRAIL_M_3:
 492    case PCI_CHIP_BAYTRAIL_M_4:
 493    case PCI_CHIP_BAYTRAIL_D:
 494       chipset = "Intel(R) Bay Trail";
 495       break;
 496    case PCI_CHIP_HASWELL_GT1:
 497    case PCI_CHIP_HASWELL_GT2:
 498    case PCI_CHIP_HASWELL_GT3:
 499    case PCI_CHIP_HASWELL_SDV_GT1:
 500    case PCI_CHIP_HASWELL_SDV_GT2:
 501    case PCI_CHIP_HASWELL_SDV_GT3:
 502    case PCI_CHIP_HASWELL_ULT_GT1:
 503    case PCI_CHIP_HASWELL_ULT_GT2:
 504    case PCI_CHIP_HASWELL_ULT_GT3:
 505    case PCI_CHIP_HASWELL_CRW_GT1:
 506    case PCI_CHIP_HASWELL_CRW_GT2:
 507    case PCI_CHIP_HASWELL_CRW_GT3:
 508       chipset = "Intel(R) Haswell Desktop";
 509       break;
 510    case PCI_CHIP_HASWELL_M_GT1:
 511    case PCI_CHIP_HASWELL_M_GT2:
 512    case PCI_CHIP_HASWELL_M_GT3:
 513    case PCI_CHIP_HASWELL_SDV_M_GT1:
 514    case PCI_CHIP_HASWELL_SDV_M_GT2:
 515    case PCI_CHIP_HASWELL_SDV_M_GT3:
 516    case PCI_CHIP_HASWELL_ULT_M_GT1:
 517    case PCI_CHIP_HASWELL_ULT_M_GT2:
 518    case PCI_CHIP_HASWELL_ULT_M_GT3:
 519    case PCI_CHIP_HASWELL_CRW_M_GT1:
 520    case PCI_CHIP_HASWELL_CRW_M_GT2:
 521    case PCI_CHIP_HASWELL_CRW_M_GT3:
 522       chipset = "Intel(R) Haswell Mobile";
 523       break;
 524    case PCI_CHIP_HASWELL_S_GT1:
 525    case PCI_CHIP_HASWELL_S_GT2:
 526    case PCI_CHIP_HASWELL_S_GT3:
 527    case PCI_CHIP_HASWELL_SDV_S_GT1:
 528    case PCI_CHIP_HASWELL_SDV_S_GT2:
 529    case PCI_CHIP_HASWELL_SDV_S_GT3:
 530    case PCI_CHIP_HASWELL_ULT_S_GT1:
 531    case PCI_CHIP_HASWELL_ULT_S_GT2:
 532    case PCI_CHIP_HASWELL_ULT_S_GT3:
 533    case PCI_CHIP_HASWELL_CRW_S_GT1:
 534    case PCI_CHIP_HASWELL_CRW_S_GT2:
 535    case PCI_CHIP_HASWELL_CRW_S_GT3:
 536       chipset = "Intel(R) Haswell Server";
 537       break;
 538    default:
 539       chipset = "Unknown Intel Chipset";
 540       break;
 541    }
 542
 543    return chipset;
 544 }
 545
 546 static uint64_t
 547 ilo_get_timestamp(struct pipe_screen *screen)
 548 {
 549    struct ilo_screen *is = ilo_screen(screen);
 550    union {
 551       uint64_t val;
 552       uint32_t dw[2];
 553    } timestamp;
 554
 555    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 556
 557    /*
 558     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 559     *
 560     *     "Note: This timestamp register reflects the value of the PCU TSC.
 561     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 562     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 563     *      hours)."
 564     *
 565     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 566     * of the timestamp.  We will have to live with a timestamp that rolls over
 567     * every ~343 seconds.
 568     *
 569     * See also brw_get_timestamp().
 570     */
 571    return (uint64_t) timestamp.dw[1] * 80;
 572 }
 573
 574 static void
 575 ilo_fence_reference(struct pipe_screen *screen,
 576                     struct pipe_fence_handle **p,
 577                     struct pipe_fence_handle *f)
 578 {
 579    struct ilo_fence **ptr = (struct ilo_fence **) p;
 580    struct ilo_fence *fence = ilo_fence(f);
 581
 582    if (!ptr) {
 583       /* still need to reference fence */
 584       if (fence)
 585          pipe_reference(NULL, &fence->reference);
 586       return;
 587    }
 588
 589    /* reference fence and dereference the one pointed to by ptr */
 590    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
 591       struct ilo_fence *old = *ptr;
 592
 593       if (old->bo)
 594          intel_bo_unreference(old->bo);
 595       FREE(old);
 596    }
 597
 598    *ptr = fence;
 599 }
 600
 601 static boolean
 602 ilo_fence_signalled(struct pipe_screen *screen,
 603                     struct pipe_fence_handle *f)
 604 {
 605    struct ilo_fence *fence = ilo_fence(f);
 606
 607    /* mark signalled if the bo is idle */
 608    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 609       intel_bo_unreference(fence->bo);
 610       fence->bo = NULL;
 611    }
 612
 613    return (fence->bo == NULL);
 614 }
 615
 616 static boolean
 617 ilo_fence_finish(struct pipe_screen *screen,
 618                  struct pipe_fence_handle *f,
 619                  uint64_t timeout)
 620 {
 621    struct ilo_fence *fence = ilo_fence(f);
 622    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 623
 624    /* already signalled */
 625    if (!fence->bo)
 626       return true;
 627
 628    /* wait and see if it returns error */
 629    if (intel_bo_wait(fence->bo, wait_timeout))
 630       return false;
 631
 632    /* mark signalled */
 633    intel_bo_unreference(fence->bo);
 634    fence->bo = NULL;
 635
 636    return true;
 637 }
 638
 639 static void
 640 ilo_screen_destroy(struct pipe_screen *screen)
 641 {
 642    struct ilo_screen *is = ilo_screen(screen);
 643
 644    /* as it seems, winsys is owned by the screen */
 645    intel_winsys_destroy(is->winsys);
 646
 647    FREE(is);
 648 }
 649
 650 static bool
 651 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 652 {
 653    dev->devid = info->devid;
 654    dev->max_batch_size = info->max_batch_size;
 655    dev->has_llc = info->has_llc;
 656    dev->has_address_swizzling = info->has_address_swizzling;
 657    dev->has_logical_context = info->has_logical_context;
 658    dev->has_ppgtt = info->has_ppgtt;
 659    dev->has_timestamp = info->has_timestamp;
 660    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 661
 662    if (!dev->has_logical_context) {
 663       ilo_err("missing hardware logical context support\n");
 664       return false;
 665    }
 666
 667    /*
 668     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 669     * writes on GEN6.
 670     *
 671     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 672     *
 673     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 674     *      code is in a secure environment, independent of address space.
 675     *      Under this condition, this bit only specifies the address space
 676     *      (GGTT or PPGTT). All commands are executed "as-is""
 677     *
 678     * We need PPGTT to be enabled on GEN6 too.
 679     */
 680    if (!dev->has_ppgtt) {
 681       /* experiments show that it does not really matter... */
 682       ilo_warn("PPGTT disabled\n");
 683    }
 684
 685    /*
 686     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 687     *
 688     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 689     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 690     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 691     *      to an EU GRF register. Read/write access to the URB is generally
 692     *      supported on a row-granular basis."
 693     *
 694     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 695     *
 696     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 697     *      128k        4096        2048
 698     *      256k        8096        4096"
 699     */
 700
 701    if (IS_HASWELL(info->devid)) {
 702       dev->gen = ILO_GEN(7.5);
 703
 704       if (IS_HSW_GT3(info->devid)) {
 705          dev->gt = 3;
 706          dev->urb_size = 512 * 1024;
 707       }
 708       else if (IS_HSW_GT2(info->devid)) {
 709          dev->gt = 2;
 710          dev->urb_size = 256 * 1024;
 711       }
 712       else {
 713          dev->gt = 1;
 714          dev->urb_size = 128 * 1024;
 715       }
 716    }
 717    else if (IS_GEN7(info->devid)) {
 718       dev->gen = ILO_GEN(7);
 719
 720       if (IS_IVB_GT2(info->devid)) {
 721          dev->gt = 2;
 722          dev->urb_size = 256 * 1024;
 723       }
 724       else {
 725          dev->gt = 1;
 726          dev->urb_size = 128 * 1024;
 727       }
 728    }
 729    else if (IS_GEN6(info->devid)) {
 730       dev->gen = ILO_GEN(6);
 731
 732       if (IS_SNB_GT2(info->devid)) {
 733          dev->gt = 2;
 734          dev->urb_size = 64 * 1024;
 735       }
 736       else {
 737          dev->gt = 1;
 738          dev->urb_size = 32 * 1024;
 739       }
 740    }
 741    else {
 742       ilo_err("unknown GPU generation\n");
 743       return false;
 744    }
 745
 746    return true;
 747 }
 748
 749 struct pipe_screen *
 750 ilo_screen_create(struct intel_winsys *ws)
 751 {
 752    struct ilo_screen *is;
 753    const struct intel_winsys_info *info;
 754
 755    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 756
 757    is = CALLOC_STRUCT(ilo_screen);
 758    if (!is)
 759       return NULL;
 760
 761    is->winsys = ws;
 762
 763    info = intel_winsys_get_info(is->winsys);
 764    if (!init_dev(&is->dev, info)) {
 765       FREE(is);
 766       return NULL;
 767    }
 768
 769    util_format_s3tc_init();
 770
 771    is->base.destroy = ilo_screen_destroy;
 772    is->base.get_name = ilo_get_name;
 773    is->base.get_vendor = ilo_get_vendor;
 774    is->base.get_param = ilo_get_param;
 775    is->base.get_paramf = ilo_get_paramf;
 776    is->base.get_shader_param = ilo_get_shader_param;
 777    is->base.get_video_param = ilo_get_video_param;
 778    is->base.get_compute_param = ilo_get_compute_param;
 779
 780    is->base.get_timestamp = ilo_get_timestamp;
 781
 782    is->base.flush_frontbuffer = NULL;
 783
 784    is->base.fence_reference = ilo_fence_reference;
 785    is->base.fence_signalled = ilo_fence_signalled;
 786    is->base.fence_finish = ilo_fence_finish;
 787
 788    is->base.get_driver_query_info = NULL;
 789
 790    ilo_init_format_functions(is);
 791    ilo_init_context_functions(is);
 792    ilo_init_resource_functions(is);
 793
 794    return &is->base;
 795 }