src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "intel_winsys.h"
  35
  36 #include "ilo_context.h"
  37 #include "ilo_format.h"
  38 #include "ilo_resource.h"
  39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  40 #include "ilo_public.h"
  41 #include "ilo_screen.h"
  42
  43 struct ilo_fence {
  44    struct pipe_reference reference;
  45    struct intel_bo *bo;
  46 };
  47
  48 int ilo_debug;
  49
  50 static const struct debug_named_value ilo_debug_flags[] = {
  51    { "batch",     ILO_DEBUG_BATCH,    "Dump batch/state/surface/instruction buffers" },
  52    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  53    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  54    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  55    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  56    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  57    { "submit",    ILO_DEBUG_SUBMIT,   "Show batch buffer submissions" },
  58    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  59    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  60    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  61    DEBUG_NAMED_VALUE_END
  62 };
  63
  64 static float
  65 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  66 {
  67    switch (param) {
  68    case PIPE_CAPF_MAX_LINE_WIDTH:
  69       /* in U3.7, defined in 3DSTATE_SF */
  70       return 7.0f;
  71    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  72       /* line width minus one, which is reserved for AA region */
  73       return 6.0f;
  74    case PIPE_CAPF_MAX_POINT_WIDTH:
  75       /* in U8.3, defined in 3DSTATE_SF */
  76       return 255.0f;
  77    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  78       /* same as point width, as we ignore rasterizer->point_smooth */
  79       return 255.0f;
  80    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  81       /* [2.0, 16.0], defined in SAMPLER_STATE */
  82       return 16.0f;
  83    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  84       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  85       return 15.0f;
  86    case PIPE_CAPF_GUARD_BAND_LEFT:
  87    case PIPE_CAPF_GUARD_BAND_TOP:
  88    case PIPE_CAPF_GUARD_BAND_RIGHT:
  89    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  90       /* what are these for? */
  91       return 0.0f;
  92
  93    default:
  94       return 0.0f;
  95    }
  96 }
  97
  98 static int
  99 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
 100                      enum pipe_shader_cap param)
 101 {
 102    switch (shader) {
 103    case PIPE_SHADER_FRAGMENT:
 104    case PIPE_SHADER_VERTEX:
 105    case PIPE_SHADER_GEOMETRY:
 106       break;
 107    default:
 108       return 0;
 109    }
 110
 111    switch (param) {
 112    /* the limits are copied from the classic driver */
 113    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 114       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 115    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 116       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 117    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 118       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 119    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 120       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 121    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 122       return UINT_MAX;
 123    case PIPE_SHADER_CAP_MAX_INPUTS:
 124    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 125       /* this is limited by how many attributes SF can remap */
 126       return 16;
 127    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 128       return 1024 * sizeof(float[4]);
 129    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 130       return ILO_MAX_CONST_BUFFERS;
 131    case PIPE_SHADER_CAP_MAX_TEMPS:
 132       return 256;
 133    case PIPE_SHADER_CAP_MAX_PREDS:
 134       return 0;
 135    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 136       return 1;
 137    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 138       return 0;
 139    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 140       return 0;
 141    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 142       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 143    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 144       return 1;
 145    case PIPE_SHADER_CAP_SUBROUTINES:
 146       return 0;
 147    case PIPE_SHADER_CAP_INTEGERS:
 148       return 1;
 149    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 150       return ILO_MAX_SAMPLERS;
 151    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 152       return ILO_MAX_SAMPLER_VIEWS;
 153    case PIPE_SHADER_CAP_PREFERRED_IR:
 154       return PIPE_SHADER_IR_TGSI;
 155    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 156       return 1;
 157
 158    default:
 159       return 0;
 160    }
 161 }
 162
 163 static int
 164 ilo_get_video_param(struct pipe_screen *screen,
 165                     enum pipe_video_profile profile,
 166                     enum pipe_video_entrypoint entrypoint,
 167                     enum pipe_video_cap param)
 168 {
 169    switch (param) {
 170    case PIPE_VIDEO_CAP_SUPPORTED:
 171       return vl_profile_supported(screen, profile, entrypoint);
 172    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 173       return 1;
 174    case PIPE_VIDEO_CAP_MAX_WIDTH:
 175    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 176       return vl_video_buffer_max_size(screen);
 177    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 178       return PIPE_FORMAT_NV12;
 179    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 180       return 1;
 181    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 182       return 1;
 183    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 184       return 0;
 185    case PIPE_VIDEO_CAP_MAX_LEVEL:
 186       return vl_level_supported(screen, profile);
 187    default:
 188       return 0;
 189    }
 190 }
 191
 192 static int
 193 ilo_get_compute_param(struct pipe_screen *screen,
 194                       enum pipe_compute_cap param,
 195                       void *ret)
 196 {
 197    struct ilo_screen *is = ilo_screen(screen);
 198    union {
 199       const char *ir_target;
 200       uint64_t grid_dimension;
 201       uint64_t max_grid_size[3];
 202       uint64_t max_block_size[3];
 203       uint64_t max_threads_per_block;
 204       uint64_t max_global_size;
 205       uint64_t max_local_size;
 206       uint64_t max_private_size;
 207       uint64_t max_input_size;
 208       uint64_t max_mem_alloc_size;
 209       uint32_t max_clock_frequency;
 210       uint32_t max_compute_units;
 211       uint32_t images_supported;
 212    } val;
 213    const void *ptr;
 214    int size;
 215
 216    switch (param) {
 217    case PIPE_COMPUTE_CAP_IR_TARGET:
 218       val.ir_target = "ilog";
 219
 220       ptr = val.ir_target;
 221       size = strlen(val.ir_target) + 1;
 222       break;
 223    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 224       val.grid_dimension = Elements(val.max_grid_size);
 225
 226       ptr = &val.grid_dimension;
 227       size = sizeof(val.grid_dimension);
 228       break;
 229    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 230       val.max_grid_size[0] = 0xffffffffu;
 231       val.max_grid_size[1] = 0xffffffffu;
 232       val.max_grid_size[2] = 0xffffffffu;
 233
 234       ptr = &val.max_grid_size;
 235       size = sizeof(val.max_grid_size);
 236       break;
 237    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 238       val.max_block_size[0] = 1024;
 239       val.max_block_size[1] = 1024;
 240       val.max_block_size[2] = 1024;
 241
 242       ptr = &val.max_block_size;
 243       size = sizeof(val.max_block_size);
 244       break;
 245
 246    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 247       val.max_threads_per_block = 1024;
 248
 249       ptr = &val.max_threads_per_block;
 250       size = sizeof(val.max_threads_per_block);
 251       break;
 252    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 253       /* \see ilo_max_resource_size */
 254       val.max_global_size = 1u << 31;
 255
 256       ptr = &val.max_global_size;
 257       size = sizeof(val.max_global_size);
 258       break;
 259    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 260       /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
 261       val.max_local_size = 64 * 1024;
 262
 263       ptr = &val.max_local_size;
 264       size = sizeof(val.max_local_size);
 265       break;
 266    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 267       /* scratch size */
 268       val.max_private_size = 12 * 1024;
 269
 270       ptr = &val.max_private_size;
 271       size = sizeof(val.max_private_size);
 272       break;
 273    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 274       val.max_input_size = 1024;
 275
 276       ptr = &val.max_input_size;
 277       size = sizeof(val.max_input_size);
 278       break;
 279    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 280       val.max_mem_alloc_size = 1u << 31;
 281
 282       ptr = &val.max_mem_alloc_size;
 283       size = sizeof(val.max_mem_alloc_size);
 284       break;
 285    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 286       val.max_clock_frequency = 1000;
 287
 288       ptr = &val.max_clock_frequency;
 289       size = sizeof(val.max_clock_frequency);
 290       break;
 291    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 292       val.max_compute_units = is->dev.eu_count;
 293
 294       ptr = &val.max_compute_units;
 295       size = sizeof(val.max_compute_units);
 296       break;
 297    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 298       val.images_supported = 1;
 299
 300       ptr = &val.images_supported;
 301       size = sizeof(val.images_supported);
 302       break;
 303    default:
 304       ptr = NULL;
 305       size = 0;
 306       break;
 307    }
 308
 309    if (ret)
 310       memcpy(ret, ptr, size);
 311
 312    return size;
 313 }
 314
 315 static int
 316 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 317 {
 318    struct ilo_screen *is = ilo_screen(screen);
 319
 320    switch (param) {
 321    case PIPE_CAP_NPOT_TEXTURES:
 322    case PIPE_CAP_TWO_SIDED_STENCIL:
 323       return true;
 324    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 325       return 0; /* TODO */
 326    case PIPE_CAP_ANISOTROPIC_FILTER:
 327    case PIPE_CAP_POINT_SPRITE:
 328       return true;
 329    case PIPE_CAP_MAX_RENDER_TARGETS:
 330       return ILO_MAX_DRAW_BUFFERS;
 331    case PIPE_CAP_OCCLUSION_QUERY:
 332    case PIPE_CAP_QUERY_TIME_ELAPSED:
 333    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 334    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 335       return true;
 336    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 337       /*
 338        * As defined in SURFACE_STATE, we have
 339        *
 340        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 341        *  GEN6           8192x8192x512            2048x2048x2048
 342        *  GEN7         16384x16384x2048           2048x2048x2048
 343        */
 344       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 345    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 346       return 12;
 347    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 348       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 349    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 350       return false;
 351    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 352    case PIPE_CAP_SM3:
 353       return true;
 354    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 355       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 356          return 0;
 357       return ILO_MAX_SO_BUFFERS;
 358    case PIPE_CAP_PRIMITIVE_RESTART:
 359       return true;
 360    case PIPE_CAP_INDEP_BLEND_ENABLE:
 361    case PIPE_CAP_INDEP_BLEND_FUNC:
 362       return true;
 363    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 364       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
 365    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 366    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 367    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 368    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 369    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 370       return true;
 371    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 372       return false;
 373    case PIPE_CAP_TGSI_INSTANCEID:
 374    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 375       return true;
 376    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 377       return false;
 378    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 379       return true;
 380    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 381    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 382       return true;
 383    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 384    case PIPE_CAP_MIN_TEXEL_OFFSET:
 385       return -8;
 386    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 387    case PIPE_CAP_MAX_TEXEL_OFFSET:
 388       return 7;
 389    case PIPE_CAP_CONDITIONAL_RENDER:
 390    case PIPE_CAP_TEXTURE_BARRIER:
 391       return true;
 392    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 393       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 394    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 395       return ILO_MAX_SO_BINDINGS;
 396    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 397       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 398          return is->dev.has_gen7_sol_reset;
 399       else
 400          return false; /* TODO */
 401    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 402       return false;
 403    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 404       return true;
 405    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 406       return false;
 407    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 408       return 140;
 409    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 410    case PIPE_CAP_USER_VERTEX_BUFFERS:
 411       return false;
 412    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 413    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 414    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 415       return false;
 416    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 417       return 2048;
 418    case PIPE_CAP_COMPUTE:
 419       return false; /* TODO */
 420    case PIPE_CAP_USER_INDEX_BUFFERS:
 421    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 422       return true;
 423    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 424       /* imposed by OWord (Dual) Block Read */
 425       return 16;
 426    case PIPE_CAP_START_INSTANCE:
 427       return true;
 428    case PIPE_CAP_QUERY_TIMESTAMP:
 429       return is->dev.has_timestamp;
 430    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 431       return false; /* TODO */
 432    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 433       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 434    case PIPE_CAP_CUBE_MAP_ARRAY:
 435    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 436       return true;
 437    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 438       return 1;
 439    case PIPE_CAP_TGSI_TEXCOORD:
 440       return false;
 441    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 442    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 443       return true;
 444    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 445       return 0;
 446    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 447       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 448       return 1 << 27;
 449    case PIPE_CAP_MAX_VIEWPORTS:
 450       return ILO_MAX_VIEWPORTS;
 451    case PIPE_CAP_ENDIANNESS:
 452       return PIPE_ENDIAN_LITTLE;
 453    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 454       return true;
 455    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 456    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 457    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 458    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 459    case PIPE_CAP_TEXTURE_GATHER_SM5:
 460       return 0;
 461    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 462       return true;
 463    case PIPE_CAP_FAKE_SW_MSAA:
 464    case PIPE_CAP_TEXTURE_QUERY_LOD:
 465    case PIPE_CAP_SAMPLE_SHADING:
 466    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 467    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 468    case PIPE_CAP_MAX_VERTEX_STREAMS:
 469    case PIPE_CAP_DRAW_INDIRECT:
 470    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 471    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 472    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 473       return 0;
 474
 475    case PIPE_CAP_VENDOR_ID:
 476       return 0x8086;
 477    case PIPE_CAP_DEVICE_ID:
 478       return is->dev.devid;
 479    case PIPE_CAP_ACCELERATED:
 480       return true;
 481    case PIPE_CAP_VIDEO_MEMORY: {
 482       /* Once a batch uses more than 75% of the maximum mappable size, we
 483        * assume that there's some fragmentation, and we start doing extra
 484        * flushing, etc.  That's the big cliff apps will care about.
 485        */
 486       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 487       uint64_t system_memory;
 488
 489       if (!os_get_total_physical_memory(&system_memory))
 490          return 0;
 491
 492       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 493    }
 494    case PIPE_CAP_UMA:
 495       return true;
 496    case PIPE_CAP_CLIP_HALFZ:
 497       return true;
 498    case PIPE_CAP_VERTEXID_NOBASE:
 499       return false;
 500    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 501       return true;
 502
 503    default:
 504       return 0;
 505    }
 506 }
 507
 508 static const char *
 509 ilo_get_vendor(struct pipe_screen *screen)
 510 {
 511    return "LunarG, Inc.";
 512 }
 513
 514 static const char *
 515 ilo_get_name(struct pipe_screen *screen)
 516 {
 517    struct ilo_screen *is = ilo_screen(screen);
 518    const char *chipset = NULL;
 519
 520    if (gen_is_vlv(is->dev.devid)) {
 521       chipset = "Intel(R) Bay Trail";
 522    }
 523    else if (gen_is_hsw(is->dev.devid)) {
 524       if (gen_is_desktop(is->dev.devid))
 525          chipset = "Intel(R) Haswell Desktop";
 526       else if (gen_is_mobile(is->dev.devid))
 527          chipset = "Intel(R) Haswell Mobile";
 528       else if (gen_is_server(is->dev.devid))
 529          chipset = "Intel(R) Haswell Server";
 530    }
 531    else if (gen_is_ivb(is->dev.devid)) {
 532       if (gen_is_desktop(is->dev.devid))
 533          chipset = "Intel(R) Ivybridge Desktop";
 534       else if (gen_is_mobile(is->dev.devid))
 535          chipset = "Intel(R) Ivybridge Mobile";
 536       else if (gen_is_server(is->dev.devid))
 537          chipset = "Intel(R) Ivybridge Server";
 538    }
 539    else if (gen_is_snb(is->dev.devid)) {
 540       if (gen_is_desktop(is->dev.devid))
 541          chipset = "Intel(R) Sandybridge Desktop";
 542       else if (gen_is_mobile(is->dev.devid))
 543          chipset = "Intel(R) Sandybridge Mobile";
 544       else if (gen_is_server(is->dev.devid))
 545          chipset = "Intel(R) Sandybridge Server";
 546    }
 547
 548    if (!chipset)
 549       chipset = "Unknown Intel Chipset";
 550
 551    return chipset;
 552 }
 553
 554 static uint64_t
 555 ilo_get_timestamp(struct pipe_screen *screen)
 556 {
 557    struct ilo_screen *is = ilo_screen(screen);
 558    union {
 559       uint64_t val;
 560       uint32_t dw[2];
 561    } timestamp;
 562
 563    intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 564
 565    /*
 566     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 567     *
 568     *     "Note: This timestamp register reflects the value of the PCU TSC.
 569     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 570     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 571     *      hours)."
 572     *
 573     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 574     * of the timestamp.  We will have to live with a timestamp that rolls over
 575     * every ~343 seconds.
 576     *
 577     * See also brw_get_timestamp().
 578     */
 579    return (uint64_t) timestamp.dw[1] * 80;
 580 }
 581
 582 static void
 583 ilo_fence_reference(struct pipe_screen *screen,
 584                     struct pipe_fence_handle **p,
 585                     struct pipe_fence_handle *f)
 586 {
 587    struct ilo_fence *fence = ilo_fence(f);
 588    struct ilo_fence *old;
 589
 590    if (likely(p)) {
 591       old = ilo_fence(*p);
 592       *p = f;
 593    }
 594    else {
 595       old = NULL;
 596    }
 597
 598    STATIC_ASSERT(&((struct ilo_fence *) NULL)->reference == NULL);
 599    if (pipe_reference(&old->reference, &fence->reference)) {
 600       if (old->bo)
 601          intel_bo_unreference(old->bo);
 602       FREE(old);
 603    }
 604 }
 605
 606 static boolean
 607 ilo_fence_signalled(struct pipe_screen *screen,
 608                     struct pipe_fence_handle *f)
 609 {
 610    struct ilo_fence *fence = ilo_fence(f);
 611
 612    /* mark signalled if the bo is idle */
 613    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 614       intel_bo_unreference(fence->bo);
 615       fence->bo = NULL;
 616    }
 617
 618    return (fence->bo == NULL);
 619 }
 620
 621 static boolean
 622 ilo_fence_finish(struct pipe_screen *screen,
 623                  struct pipe_fence_handle *f,
 624                  uint64_t timeout)
 625 {
 626    struct ilo_fence *fence = ilo_fence(f);
 627    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 628
 629    /* already signalled */
 630    if (!fence->bo)
 631       return true;
 632
 633    /* wait and see if it returns error */
 634    if (intel_bo_wait(fence->bo, wait_timeout))
 635       return false;
 636
 637    /* mark signalled */
 638    intel_bo_unreference(fence->bo);
 639    fence->bo = NULL;
 640
 641    return true;
 642 }
 643
 644 /**
 645  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 646  * before waited on or checked.
 647  */
 648 struct ilo_fence *
 649 ilo_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 650 {
 651    struct ilo_fence *fence;
 652
 653    fence = CALLOC_STRUCT(ilo_fence);
 654    if (!fence)
 655       return NULL;
 656
 657    pipe_reference_init(&fence->reference, 1);
 658
 659    if (bo)
 660       intel_bo_reference(bo);
 661    fence->bo = bo;
 662
 663    return fence;
 664 }
 665
 666 static void
 667 ilo_screen_destroy(struct pipe_screen *screen)
 668 {
 669    struct ilo_screen *is = ilo_screen(screen);
 670
 671    /* as it seems, winsys is owned by the screen */
 672    intel_winsys_destroy(is->winsys);
 673
 674    FREE(is);
 675 }
 676
 677 static bool
 678 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 679 {
 680    dev->devid = info->devid;
 681    dev->aperture_total = info->aperture_total;
 682    dev->aperture_mappable = info->aperture_mappable;
 683    dev->has_llc = info->has_llc;
 684    dev->has_address_swizzling = info->has_address_swizzling;
 685    dev->has_logical_context = info->has_logical_context;
 686    dev->has_ppgtt = info->has_ppgtt;
 687    dev->has_timestamp = info->has_timestamp;
 688    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 689
 690    if (!dev->has_logical_context) {
 691       ilo_err("missing hardware logical context support\n");
 692       return false;
 693    }
 694
 695    /*
 696     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 697     * writes on GEN6.
 698     *
 699     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 700     *
 701     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 702     *      code is in a secure environment, independent of address space.
 703     *      Under this condition, this bit only specifies the address space
 704     *      (GGTT or PPGTT). All commands are executed "as-is""
 705     *
 706     * We need PPGTT to be enabled on GEN6 too.
 707     */
 708    if (!dev->has_ppgtt) {
 709       /* experiments show that it does not really matter... */
 710       ilo_warn("PPGTT disabled\n");
 711    }
 712
 713    if (gen_is_hsw(info->devid)) {
 714       /*
 715        * From the Haswell PRM, volume 4, page 8:
 716        *
 717        *     "Description                    GT3      GT2      GT1.5    GT1
 718        *      (...)
 719        *      EUs (Total)                    40       20       12       10
 720        *      Threads (Total)                280      140      84       70
 721        *      (...)
 722        *      URB Size (max, within L3$)     512KB    256KB    256KB    128KB
 723        */
 724       dev->gen_opaque = ILO_GEN(7.5);
 725       dev->gt = gen_get_hsw_gt(info->devid);
 726       if (dev->gt == 3) {
 727          dev->eu_count = 40;
 728          dev->thread_count = 280;
 729          dev->urb_size = 512 * 1024;
 730       } else if (dev->gt == 2) {
 731          dev->eu_count = 20;
 732          dev->thread_count = 140;
 733          dev->urb_size = 256 * 1024;
 734       } else {
 735          dev->eu_count = 10;
 736          dev->thread_count = 70;
 737          dev->urb_size = 128 * 1024;
 738       }
 739    } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 740       /*
 741        * From the Ivy Bridge PRM, volume 1 part 1, page 18:
 742        *
 743        *     "Device             # of EUs        #Threads/EU
 744        *      Ivy Bridge (GT2)   16              8
 745        *      Ivy Bridge (GT1)   6               6"
 746        *
 747        * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 748        *
 749        *     "URB Size    URB Rows    URB Rows when SLM Enabled
 750        *      128k        4096        2048
 751        *      256k        8096        4096"
 752        */
 753       dev->gen_opaque = ILO_GEN(7);
 754       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 755       if (dev->gt == 2) {
 756          dev->eu_count = 16;
 757          dev->thread_count = 128;
 758          dev->urb_size = 256 * 1024;
 759       } else {
 760          dev->eu_count = 6;
 761          dev->thread_count = 36;
 762          dev->urb_size = 128 * 1024;
 763       }
 764    } else if (gen_is_snb(info->devid)) {
 765       /*
 766        * From the Sandy Bridge PRM, volume 1 part 1, page 22:
 767        *
 768        *     "Device             # of EUs        #Threads/EU
 769        *      SNB GT2            12              5
 770        *      SNB GT1            6               4"
 771        *
 772        * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 773        *
 774        *     "[DevSNB]: The GT1 product's URB provides 32KB of storage,
 775        *      arranged as 1024 256-bit rows. The GT2 product's URB provides
 776        *      64KB of storage, arranged as 2048 256-bit rows. A row
 777        *      corresponds in size to an EU GRF register. Read/write access to
 778        *      the URB is generally supported on a row-granular basis."
 779        */
 780       dev->gen_opaque = ILO_GEN(6);
 781       dev->gt = gen_get_snb_gt(info->devid);
 782       if (dev->gt == 2) {
 783          dev->eu_count = 12;
 784          dev->thread_count = 60;
 785          dev->urb_size = 64 * 1024;
 786       } else {
 787          dev->eu_count = 6;
 788          dev->thread_count = 24;
 789          dev->urb_size = 32 * 1024;
 790       }
 791    } else {
 792       ilo_err("unknown GPU generation\n");
 793       return false;
 794    }
 795
 796    return true;
 797 }
 798
 799 struct pipe_screen *
 800 ilo_screen_create(struct intel_winsys *ws)
 801 {
 802    struct ilo_screen *is;
 803    const struct intel_winsys_info *info;
 804
 805    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 806
 807    is = CALLOC_STRUCT(ilo_screen);
 808    if (!is)
 809       return NULL;
 810
 811    is->winsys = ws;
 812
 813    info = intel_winsys_get_info(is->winsys);
 814    if (!init_dev(&is->dev, info)) {
 815       FREE(is);
 816       return NULL;
 817    }
 818
 819    util_format_s3tc_init();
 820
 821    is->base.destroy = ilo_screen_destroy;
 822    is->base.get_name = ilo_get_name;
 823    is->base.get_vendor = ilo_get_vendor;
 824    is->base.get_param = ilo_get_param;
 825    is->base.get_paramf = ilo_get_paramf;
 826    is->base.get_shader_param = ilo_get_shader_param;
 827    is->base.get_video_param = ilo_get_video_param;
 828    is->base.get_compute_param = ilo_get_compute_param;
 829
 830    is->base.get_timestamp = ilo_get_timestamp;
 831
 832    is->base.flush_frontbuffer = NULL;
 833
 834    is->base.fence_reference = ilo_fence_reference;
 835    is->base.fence_signalled = ilo_fence_signalled;
 836    is->base.fence_finish = ilo_fence_finish;
 837
 838    is->base.get_driver_query_info = NULL;
 839
 840    ilo_init_format_functions(is);
 841    ilo_init_context_functions(is);
 842    ilo_init_resource_functions(is);
 843
 844    return &is->base;
 845 }