src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "intel_chipset.h"
  32 #include "intel_reg.h" /* for TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_public.h"
  39 #include "ilo_screen.h"
  40
  41 int ilo_debug;
  42
  43 static const struct debug_named_value ilo_debug_flags[] = {
  44    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  50    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  51    DEBUG_NAMED_VALUE_END
  52 };
  53
  54 static float
  55 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  56 {
  57    switch (param) {
  58    case PIPE_CAPF_MAX_LINE_WIDTH:
  59       /* in U3.7, defined in 3DSTATE_SF */
  60       return 7.0f;
  61    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  62       /* line width minus one, which is reserved for AA region */
  63       return 6.0f;
  64    case PIPE_CAPF_MAX_POINT_WIDTH:
  65       /* in U8.3, defined in 3DSTATE_SF */
  66       return 255.0f;
  67    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  68       /* same as point width, as we ignore rasterizer->point_smooth */
  69       return 255.0f;
  70    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  71       /* [2.0, 16.0], defined in SAMPLER_STATE */
  72       return 16.0f;
  73    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  74       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  75       return 15.0f;
  76    case PIPE_CAPF_GUARD_BAND_LEFT:
  77    case PIPE_CAPF_GUARD_BAND_TOP:
  78    case PIPE_CAPF_GUARD_BAND_RIGHT:
  79    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  80       /* what are these for? */
  81       return 0.0f;
  82
  83    default:
  84       return 0.0f;
  85    }
  86 }
  87
  88 static int
  89 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  90                      enum pipe_shader_cap param)
  91 {
  92    switch (shader) {
  93    case PIPE_SHADER_FRAGMENT:
  94    case PIPE_SHADER_VERTEX:
  95    case PIPE_SHADER_GEOMETRY:
  96       break;
  97    default:
  98       return 0;
  99    }
 100
 101    switch (param) {
 102    /* the limits are copied from the classic driver */
 103    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 104       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 105    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 106       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 107    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 108       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 109    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 110       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 111    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 112       return UINT_MAX;
 113    case PIPE_SHADER_CAP_MAX_INPUTS:
 114       /* this is limited by how many attributes SF can remap */
 115       return 16;
 116    case PIPE_SHADER_CAP_MAX_CONSTS:
 117       return 1024;
 118    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 119       return ILO_MAX_CONST_BUFFERS;
 120    case PIPE_SHADER_CAP_MAX_TEMPS:
 121       return 256;
 122    case PIPE_SHADER_CAP_MAX_ADDRS:
 123       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 124    case PIPE_SHADER_CAP_MAX_PREDS:
 125       return 0;
 126    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 127       return 1;
 128    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 129       return 0;
 130    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 131       return 0;
 132    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 133       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 134    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 135       return 1;
 136    case PIPE_SHADER_CAP_SUBROUTINES:
 137       return 0;
 138    case PIPE_SHADER_CAP_INTEGERS:
 139       return 1;
 140    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 141       return ILO_MAX_SAMPLERS;
 142    case PIPE_SHADER_CAP_PREFERRED_IR:
 143       return PIPE_SHADER_IR_TGSI;
 144    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 145       return 1;
 146
 147    default:
 148       return 0;
 149    }
 150 }
 151
 152 static int
 153 ilo_get_video_param(struct pipe_screen *screen,
 154                     enum pipe_video_profile profile,
 155                     enum pipe_video_cap param)
 156 {
 157    switch (param) {
 158    case PIPE_VIDEO_CAP_SUPPORTED:
 159       return vl_profile_supported(screen, profile);
 160    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 161       return 1;
 162    case PIPE_VIDEO_CAP_MAX_WIDTH:
 163    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 164       return vl_video_buffer_max_size(screen);
 165    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 166       return PIPE_FORMAT_NV12;
 167    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 168       return 1;
 169    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 170       return 1;
 171    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 172       return 0;
 173    case PIPE_VIDEO_CAP_MAX_LEVEL:
 174       return vl_level_supported(screen, profile);
 175    default:
 176       return 0;
 177    }
 178 }
 179
 180 static int
 181 ilo_get_compute_param(struct pipe_screen *screen,
 182                       enum pipe_compute_cap param,
 183                       void *ret)
 184 {
 185    union {
 186       const char *ir_target;
 187       uint64_t grid_dimension;
 188       uint64_t max_grid_size[3];
 189       uint64_t max_block_size[3];
 190       uint64_t max_threads_per_block;
 191       uint64_t max_global_size;
 192       uint64_t max_local_size;
 193       uint64_t max_private_size;
 194       uint64_t max_input_size;
 195       uint64_t max_mem_alloc_size;
 196    } val;
 197    const void *ptr;
 198    int size;
 199
 200    /* XXX some randomly chosen values */
 201    switch (param) {
 202    case PIPE_COMPUTE_CAP_IR_TARGET:
 203       val.ir_target = "ilog";
 204
 205       ptr = val.ir_target;
 206       size = strlen(val.ir_target) + 1;
 207       break;
 208    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 209       val.grid_dimension = Elements(val.max_grid_size);
 210
 211       ptr = &val.grid_dimension;
 212       size = sizeof(val.grid_dimension);
 213       break;
 214    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 215       val.max_grid_size[0] = 65535;
 216       val.max_grid_size[1] = 65535;
 217       val.max_grid_size[2] = 1;
 218
 219       ptr = &val.max_grid_size;
 220       size = sizeof(val.max_grid_size);
 221       break;
 222    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 223       val.max_block_size[0] = 512;
 224       val.max_block_size[1] = 512;
 225       val.max_block_size[2] = 512;
 226
 227       ptr = &val.max_block_size;
 228       size = sizeof(val.max_block_size);
 229       break;
 230
 231    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 232       val.max_threads_per_block = 512;
 233
 234       ptr = &val.max_threads_per_block;
 235       size = sizeof(val.max_threads_per_block);
 236       break;
 237    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 238       val.max_global_size = 4;
 239
 240       ptr = &val.max_global_size;
 241       size = sizeof(val.max_global_size);
 242       break;
 243    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 244       val.max_local_size = 64 * 1024;
 245
 246       ptr = &val.max_local_size;
 247       size = sizeof(val.max_local_size);
 248       break;
 249    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 250       val.max_private_size = 32768;
 251
 252       ptr = &val.max_private_size;
 253       size = sizeof(val.max_private_size);
 254       break;
 255    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 256       val.max_input_size = 256;
 257
 258       ptr = &val.max_input_size;
 259       size = sizeof(val.max_input_size);
 260       break;
 261    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 262       val.max_mem_alloc_size = 128 * 1024 * 1024;
 263
 264       ptr = &val.max_mem_alloc_size;
 265       size = sizeof(val.max_mem_alloc_size);
 266       break;
 267    default:
 268       ptr = NULL;
 269       size = 0;
 270       break;
 271    }
 272
 273    if (ret)
 274       memcpy(ret, ptr, size);
 275
 276    return size;
 277 }
 278
 279 static int
 280 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 281 {
 282    struct ilo_screen *is = ilo_screen(screen);
 283
 284    switch (param) {
 285    case PIPE_CAP_NPOT_TEXTURES:
 286    case PIPE_CAP_TWO_SIDED_STENCIL:
 287       return true;
 288    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 289       return 0; /* TODO */
 290    case PIPE_CAP_ANISOTROPIC_FILTER:
 291    case PIPE_CAP_POINT_SPRITE:
 292       return true;
 293    case PIPE_CAP_MAX_RENDER_TARGETS:
 294       return ILO_MAX_DRAW_BUFFERS;
 295    case PIPE_CAP_OCCLUSION_QUERY:
 296    case PIPE_CAP_QUERY_TIME_ELAPSED:
 297    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 298    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 299       return true;
 300    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 301       /*
 302        * As defined in SURFACE_STATE, we have
 303        *
 304        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 305        *  GEN6           8192x8192x512            2048x2048x2048
 306        *  GEN7         16384x16384x2048           2048x2048x2048
 307        *
 308        * However, when the texutre size is large, things become unstable.  We
 309        * require the maximum texture size to be 2^30 bytes in
 310        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 311        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 312        * than 2^26 pixels.
 313        *
 314        * For 3D textures, we have to set the maximum number of levels to 9,
 315        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 316        * which has at most 2^26 pixels.  And for cube textures, we has to set
 317        * it to 12.
 318        */
 319       return 14;
 320    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 321       return 9;
 322    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 323       return 12;
 324    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 325       return false;
 326    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 327    case PIPE_CAP_SM3:
 328       return true;
 329    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 330       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 331          return 0;
 332       return ILO_MAX_SO_BUFFERS;
 333    case PIPE_CAP_PRIMITIVE_RESTART:
 334       return true;
 335    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 336       return ILO_MAX_SAMPLERS * 2;
 337    case PIPE_CAP_INDEP_BLEND_ENABLE:
 338    case PIPE_CAP_INDEP_BLEND_FUNC:
 339       return true;
 340    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 341       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 342    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 343    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 344    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 345    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 346    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 347       return true;
 348    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 349       return false;
 350    case PIPE_CAP_TGSI_INSTANCEID:
 351    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 352       return true;
 353    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 354       return false;
 355    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 356       return true;
 357    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 358    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 359    case PIPE_CAP_SCALED_RESOLVE:
 360       return true;
 361    case PIPE_CAP_MIN_TEXEL_OFFSET:
 362       return -8;
 363    case PIPE_CAP_MAX_TEXEL_OFFSET:
 364       return 7;
 365    case PIPE_CAP_CONDITIONAL_RENDER:
 366    case PIPE_CAP_TEXTURE_BARRIER:
 367       return true;
 368    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 369       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 370    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 371       return ILO_MAX_SO_BINDINGS;
 372    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 373       if (is->dev.gen >= ILO_GEN(7))
 374          return is->dev.has_gen7_sol_reset;
 375       else
 376          return false; /* TODO */
 377    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 378       return false;
 379    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 380       return true;
 381    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 382       return false;
 383    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 384       return 140;
 385    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 386    case PIPE_CAP_USER_VERTEX_BUFFERS:
 387       return false;
 388    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 389    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 390    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 391       return false;
 392    case PIPE_CAP_COMPUTE:
 393       return false; /* TODO */
 394    case PIPE_CAP_USER_INDEX_BUFFERS:
 395    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 396       return true;
 397    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 398       /* imposed by OWord (Dual) Block Read */
 399       return 16;
 400    case PIPE_CAP_START_INSTANCE:
 401    case PIPE_CAP_QUERY_TIMESTAMP:
 402       return true;
 403    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 404       return false; /* TODO */
 405    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 406       return 0;
 407    case PIPE_CAP_CUBE_MAP_ARRAY:
 408    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 409       return true;
 410    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 411       return 1;
 412    case PIPE_CAP_TGSI_TEXCOORD:
 413       return false;
 414    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 415       return true;
 416    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 417       return false; /* TODO */
 418    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 419       return 0;
 420    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 421       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
 422       return 1 << 27;
 423    case PIPE_CAP_MAX_VIEWPORTS:
 424       return ILO_MAX_VIEWPORTS;
 425    case PIPE_CAP_ENDIANNESS:
 426       return PIPE_ENDIAN_LITTLE;
 427
 428    default:
 429       return 0;
 430    }
 431 }
 432
 433 static const char *
 434 ilo_get_vendor(struct pipe_screen *screen)
 435 {
 436    return "LunarG, Inc.";
 437 }
 438
 439 static const char *
 440 ilo_get_name(struct pipe_screen *screen)
 441 {
 442    struct ilo_screen *is = ilo_screen(screen);
 443    const char *chipset;
 444
 445    /* stolen from classic i965 */
 446    switch (is->dev.devid) {
 447    case PCI_CHIP_SANDYBRIDGE_GT1:
 448    case PCI_CHIP_SANDYBRIDGE_GT2:
 449    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 450       chipset = "Intel(R) Sandybridge Desktop";
 451       break;
 452    case PCI_CHIP_SANDYBRIDGE_M_GT1:
 453    case PCI_CHIP_SANDYBRIDGE_M_GT2:
 454    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 455       chipset = "Intel(R) Sandybridge Mobile";
 456       break;
 457    case PCI_CHIP_SANDYBRIDGE_S:
 458       chipset = "Intel(R) Sandybridge Server";
 459       break;
 460    case PCI_CHIP_IVYBRIDGE_GT1:
 461    case PCI_CHIP_IVYBRIDGE_GT2:
 462       chipset = "Intel(R) Ivybridge Desktop";
 463       break;
 464    case PCI_CHIP_IVYBRIDGE_M_GT1:
 465    case PCI_CHIP_IVYBRIDGE_M_GT2:
 466       chipset = "Intel(R) Ivybridge Mobile";
 467       break;
 468    case PCI_CHIP_IVYBRIDGE_S_GT1:
 469    case PCI_CHIP_IVYBRIDGE_S_GT2:
 470       chipset = "Intel(R) Ivybridge Server";
 471       break;
 472    case PCI_CHIP_BAYTRAIL_M_1:
 473    case PCI_CHIP_BAYTRAIL_M_2:
 474    case PCI_CHIP_BAYTRAIL_M_3:
 475    case PCI_CHIP_BAYTRAIL_M_4:
 476    case PCI_CHIP_BAYTRAIL_D:
 477       chipset = "Intel(R) Bay Trail";
 478       break;
 479    case PCI_CHIP_HASWELL_GT1:
 480    case PCI_CHIP_HASWELL_GT2:
 481    case PCI_CHIP_HASWELL_GT3:
 482    case PCI_CHIP_HASWELL_SDV_GT1:
 483    case PCI_CHIP_HASWELL_SDV_GT2:
 484    case PCI_CHIP_HASWELL_SDV_GT3:
 485    case PCI_CHIP_HASWELL_ULT_GT1:
 486    case PCI_CHIP_HASWELL_ULT_GT2:
 487    case PCI_CHIP_HASWELL_ULT_GT3:
 488    case PCI_CHIP_HASWELL_CRW_GT1:
 489    case PCI_CHIP_HASWELL_CRW_GT2:
 490    case PCI_CHIP_HASWELL_CRW_GT3:
 491       chipset = "Intel(R) Haswell Desktop";
 492       break;
 493    case PCI_CHIP_HASWELL_M_GT1:
 494    case PCI_CHIP_HASWELL_M_GT2:
 495    case PCI_CHIP_HASWELL_M_GT3:
 496    case PCI_CHIP_HASWELL_SDV_M_GT1:
 497    case PCI_CHIP_HASWELL_SDV_M_GT2:
 498    case PCI_CHIP_HASWELL_SDV_M_GT3:
 499    case PCI_CHIP_HASWELL_ULT_M_GT1:
 500    case PCI_CHIP_HASWELL_ULT_M_GT2:
 501    case PCI_CHIP_HASWELL_ULT_M_GT3:
 502    case PCI_CHIP_HASWELL_CRW_M_GT1:
 503    case PCI_CHIP_HASWELL_CRW_M_GT2:
 504    case PCI_CHIP_HASWELL_CRW_M_GT3:
 505       chipset = "Intel(R) Haswell Mobile";
 506       break;
 507    case PCI_CHIP_HASWELL_S_GT1:
 508    case PCI_CHIP_HASWELL_S_GT2:
 509    case PCI_CHIP_HASWELL_S_GT3:
 510    case PCI_CHIP_HASWELL_SDV_S_GT1:
 511    case PCI_CHIP_HASWELL_SDV_S_GT2:
 512    case PCI_CHIP_HASWELL_SDV_S_GT3:
 513    case PCI_CHIP_HASWELL_ULT_S_GT1:
 514    case PCI_CHIP_HASWELL_ULT_S_GT2:
 515    case PCI_CHIP_HASWELL_ULT_S_GT3:
 516    case PCI_CHIP_HASWELL_CRW_S_GT1:
 517    case PCI_CHIP_HASWELL_CRW_S_GT2:
 518    case PCI_CHIP_HASWELL_CRW_S_GT3:
 519       chipset = "Intel(R) Haswell Server";
 520       break;
 521    default:
 522       chipset = "Unknown Intel Chipset";
 523       break;
 524    }
 525
 526    return chipset;
 527 }
 528
 529 static uint64_t
 530 ilo_get_timestamp(struct pipe_screen *screen)
 531 {
 532    struct ilo_screen *is = ilo_screen(screen);
 533    union {
 534       uint64_t val;
 535       uint32_t dw[2];
 536    } timestamp;
 537
 538    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 539
 540    /*
 541     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 542     *
 543     *     "Note: This timestamp register reflects the value of the PCU TSC.
 544     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 545     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 546     *      hours)."
 547     *
 548     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 549     * of the timestamp.  We will have to live with a timestamp that rolls over
 550     * every ~343 seconds.
 551     *
 552     * See also brw_get_timestamp().
 553     */
 554    return (uint64_t) timestamp.dw[1] * 80;
 555 }
 556
 557 static void
 558 ilo_fence_reference(struct pipe_screen *screen,
 559                     struct pipe_fence_handle **p,
 560                     struct pipe_fence_handle *f)
 561 {
 562    struct ilo_fence **ptr = (struct ilo_fence **) p;
 563    struct ilo_fence *fence = ilo_fence(f);
 564
 565    if (!ptr) {
 566       /* still need to reference fence */
 567       if (fence)
 568          pipe_reference(NULL, &fence->reference);
 569       return;
 570    }
 571
 572    /* reference fence and dereference the one pointed to by ptr */
 573    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
 574       struct ilo_fence *old = *ptr;
 575
 576       if (old->bo)
 577          intel_bo_unreference(old->bo);
 578       FREE(old);
 579    }
 580
 581    *ptr = fence;
 582 }
 583
 584 static boolean
 585 ilo_fence_signalled(struct pipe_screen *screen,
 586                     struct pipe_fence_handle *f)
 587 {
 588    struct ilo_fence *fence = ilo_fence(f);
 589
 590    /* mark signalled if the bo is idle */
 591    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 592       intel_bo_unreference(fence->bo);
 593       fence->bo = NULL;
 594    }
 595
 596    return (fence->bo == NULL);
 597 }
 598
 599 static boolean
 600 ilo_fence_finish(struct pipe_screen *screen,
 601                  struct pipe_fence_handle *f,
 602                  uint64_t timeout)
 603 {
 604    struct ilo_fence *fence = ilo_fence(f);
 605    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 606
 607    /* already signalled */
 608    if (!fence->bo)
 609       return true;
 610
 611    /* wait and see if it returns error */
 612    if (intel_bo_wait(fence->bo, wait_timeout))
 613       return false;
 614
 615    /* mark signalled */
 616    intel_bo_unreference(fence->bo);
 617    fence->bo = NULL;
 618
 619    return true;
 620 }
 621
 622 static void
 623 ilo_screen_destroy(struct pipe_screen *screen)
 624 {
 625    struct ilo_screen *is = ilo_screen(screen);
 626
 627    /* as it seems, winsys is owned by the screen */
 628    intel_winsys_destroy(is->winsys);
 629
 630    FREE(is);
 631 }
 632
 633 static bool
 634 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 635 {
 636    dev->devid = info->devid;
 637    dev->has_llc = info->has_llc;
 638    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 639    dev->has_address_swizzling = info->has_address_swizzling;
 640
 641    /*
 642     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 643     *
 644     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 645     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 646     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 647     *      to an EU GRF register. Read/write access to the URB is generally
 648     *      supported on a row-granular basis."
 649     *
 650     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 651     *
 652     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 653     *      128k        4096        2048
 654     *      256k        8096        4096"
 655     */
 656
 657    if (IS_HASWELL(info->devid)) {
 658       dev->gen = ILO_GEN(7.5);
 659
 660       if (IS_HSW_GT3(info->devid)) {
 661          dev->gt = 3;
 662          dev->urb_size = 512 * 1024;
 663       }
 664       else if (IS_HSW_GT2(info->devid)) {
 665          dev->gt = 2;
 666          dev->urb_size = 256 * 1024;
 667       }
 668       else {
 669          dev->gt = 1;
 670          dev->urb_size = 128 * 1024;
 671       }
 672    }
 673    else if (IS_GEN7(info->devid)) {
 674       dev->gen = ILO_GEN(7);
 675
 676       if (IS_IVB_GT2(info->devid)) {
 677          dev->gt = 2;
 678          dev->urb_size = 256 * 1024;
 679       }
 680       else {
 681          dev->gt = 1;
 682          dev->urb_size = 128 * 1024;
 683       }
 684    }
 685    else if (IS_GEN6(info->devid)) {
 686       dev->gen = ILO_GEN(6);
 687
 688       if (IS_SNB_GT2(info->devid)) {
 689          dev->gt = 2;
 690          dev->urb_size = 64 * 1024;
 691       }
 692       else {
 693          dev->gt = 1;
 694          dev->urb_size = 32 * 1024;
 695       }
 696    }
 697    else {
 698       ilo_err("unknown GPU generation\n");
 699       return false;
 700    }
 701
 702    return true;
 703 }
 704
 705 struct pipe_screen *
 706 ilo_screen_create(struct intel_winsys *ws)
 707 {
 708    struct ilo_screen *is;
 709    const struct intel_winsys_info *info;
 710
 711    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 712
 713    is = CALLOC_STRUCT(ilo_screen);
 714    if (!is)
 715       return NULL;
 716
 717    is->winsys = ws;
 718
 719    intel_winsys_enable_reuse(is->winsys);
 720
 721    info = intel_winsys_get_info(is->winsys);
 722    if (!init_dev(&is->dev, info)) {
 723       FREE(is);
 724       return NULL;
 725    }
 726
 727    util_format_s3tc_init();
 728
 729    is->base.destroy = ilo_screen_destroy;
 730    is->base.get_name = ilo_get_name;
 731    is->base.get_vendor = ilo_get_vendor;
 732    is->base.get_param = ilo_get_param;
 733    is->base.get_paramf = ilo_get_paramf;
 734    is->base.get_shader_param = ilo_get_shader_param;
 735    is->base.get_video_param = ilo_get_video_param;
 736    is->base.get_compute_param = ilo_get_compute_param;
 737
 738    is->base.get_timestamp = ilo_get_timestamp;
 739
 740    is->base.flush_frontbuffer = NULL;
 741
 742    is->base.fence_reference = ilo_fence_reference;
 743    is->base.fence_signalled = ilo_fence_signalled;
 744    is->base.fence_finish = ilo_fence_finish;
 745
 746    is->base.get_driver_query_info = NULL;
 747
 748    ilo_init_format_functions(is);
 749    ilo_init_context_functions(is);
 750    ilo_init_resource_functions(is);
 751
 752    return &is->base;
 753 }