src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "intel_chipset.h"
  32 #include "intel_reg.h" /* for TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_public.h"
  39 #include "ilo_screen.h"
  40
  41 int ilo_debug;
  42
  43 static const struct debug_named_value ilo_debug_flags[] = {
  44    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  50    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  51    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  52    DEBUG_NAMED_VALUE_END
  53 };
  54
  55 static float
  56 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  57 {
  58    switch (param) {
  59    case PIPE_CAPF_MAX_LINE_WIDTH:
  60       /* in U3.7, defined in 3DSTATE_SF */
  61       return 7.0f;
  62    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  63       /* line width minus one, which is reserved for AA region */
  64       return 6.0f;
  65    case PIPE_CAPF_MAX_POINT_WIDTH:
  66       /* in U8.3, defined in 3DSTATE_SF */
  67       return 255.0f;
  68    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  69       /* same as point width, as we ignore rasterizer->point_smooth */
  70       return 255.0f;
  71    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  72       /* [2.0, 16.0], defined in SAMPLER_STATE */
  73       return 16.0f;
  74    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  75       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  76       return 15.0f;
  77    case PIPE_CAPF_GUARD_BAND_LEFT:
  78    case PIPE_CAPF_GUARD_BAND_TOP:
  79    case PIPE_CAPF_GUARD_BAND_RIGHT:
  80    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  81       /* what are these for? */
  82       return 0.0f;
  83
  84    default:
  85       return 0.0f;
  86    }
  87 }
  88
  89 static int
  90 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  91                      enum pipe_shader_cap param)
  92 {
  93    switch (shader) {
  94    case PIPE_SHADER_FRAGMENT:
  95    case PIPE_SHADER_VERTEX:
  96    case PIPE_SHADER_GEOMETRY:
  97       break;
  98    default:
  99       return 0;
 100    }
 101
 102    switch (param) {
 103    /* the limits are copied from the classic driver */
 104    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 105       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 106    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 107       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 108    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 109       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 110    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 111       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 112    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 113       return UINT_MAX;
 114    case PIPE_SHADER_CAP_MAX_INPUTS:
 115       /* this is limited by how many attributes SF can remap */
 116       return 16;
 117    case PIPE_SHADER_CAP_MAX_CONSTS:
 118       return 1024;
 119    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 120       return ILO_MAX_CONST_BUFFERS;
 121    case PIPE_SHADER_CAP_MAX_TEMPS:
 122       return 256;
 123    case PIPE_SHADER_CAP_MAX_ADDRS:
 124       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 125    case PIPE_SHADER_CAP_MAX_PREDS:
 126       return 0;
 127    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 128       return 1;
 129    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 130       return 0;
 131    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 132       return 0;
 133    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 134       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 135    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 136       return 1;
 137    case PIPE_SHADER_CAP_SUBROUTINES:
 138       return 0;
 139    case PIPE_SHADER_CAP_INTEGERS:
 140       return 1;
 141    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 142       return ILO_MAX_SAMPLERS;
 143    case PIPE_SHADER_CAP_PREFERRED_IR:
 144       return PIPE_SHADER_IR_TGSI;
 145    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 146       return 1;
 147
 148    default:
 149       return 0;
 150    }
 151 }
 152
 153 static int
 154 ilo_get_video_param(struct pipe_screen *screen,
 155                     enum pipe_video_profile profile,
 156                     enum pipe_video_entrypoint entrypoint,
 157                     enum pipe_video_cap param)
 158 {
 159    switch (param) {
 160    case PIPE_VIDEO_CAP_SUPPORTED:
 161       return vl_profile_supported(screen, profile, entrypoint);
 162    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 163       return 1;
 164    case PIPE_VIDEO_CAP_MAX_WIDTH:
 165    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 166       return vl_video_buffer_max_size(screen);
 167    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 168       return PIPE_FORMAT_NV12;
 169    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 170       return 1;
 171    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 172       return 1;
 173    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 174       return 0;
 175    case PIPE_VIDEO_CAP_MAX_LEVEL:
 176       return vl_level_supported(screen, profile);
 177    default:
 178       return 0;
 179    }
 180 }
 181
 182 static int
 183 ilo_get_compute_param(struct pipe_screen *screen,
 184                       enum pipe_compute_cap param,
 185                       void *ret)
 186 {
 187    union {
 188       const char *ir_target;
 189       uint64_t grid_dimension;
 190       uint64_t max_grid_size[3];
 191       uint64_t max_block_size[3];
 192       uint64_t max_threads_per_block;
 193       uint64_t max_global_size;
 194       uint64_t max_local_size;
 195       uint64_t max_private_size;
 196       uint64_t max_input_size;
 197       uint64_t max_mem_alloc_size;
 198    } val;
 199    const void *ptr;
 200    int size;
 201
 202    /* XXX some randomly chosen values */
 203    switch (param) {
 204    case PIPE_COMPUTE_CAP_IR_TARGET:
 205       val.ir_target = "ilog";
 206
 207       ptr = val.ir_target;
 208       size = strlen(val.ir_target) + 1;
 209       break;
 210    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 211       val.grid_dimension = Elements(val.max_grid_size);
 212
 213       ptr = &val.grid_dimension;
 214       size = sizeof(val.grid_dimension);
 215       break;
 216    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 217       val.max_grid_size[0] = 65535;
 218       val.max_grid_size[1] = 65535;
 219       val.max_grid_size[2] = 1;
 220
 221       ptr = &val.max_grid_size;
 222       size = sizeof(val.max_grid_size);
 223       break;
 224    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 225       val.max_block_size[0] = 512;
 226       val.max_block_size[1] = 512;
 227       val.max_block_size[2] = 512;
 228
 229       ptr = &val.max_block_size;
 230       size = sizeof(val.max_block_size);
 231       break;
 232
 233    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 234       val.max_threads_per_block = 512;
 235
 236       ptr = &val.max_threads_per_block;
 237       size = sizeof(val.max_threads_per_block);
 238       break;
 239    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 240       val.max_global_size = 4;
 241
 242       ptr = &val.max_global_size;
 243       size = sizeof(val.max_global_size);
 244       break;
 245    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 246       val.max_local_size = 64 * 1024;
 247
 248       ptr = &val.max_local_size;
 249       size = sizeof(val.max_local_size);
 250       break;
 251    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 252       val.max_private_size = 32768;
 253
 254       ptr = &val.max_private_size;
 255       size = sizeof(val.max_private_size);
 256       break;
 257    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 258       val.max_input_size = 256;
 259
 260       ptr = &val.max_input_size;
 261       size = sizeof(val.max_input_size);
 262       break;
 263    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 264       val.max_mem_alloc_size = 128 * 1024 * 1024;
 265
 266       ptr = &val.max_mem_alloc_size;
 267       size = sizeof(val.max_mem_alloc_size);
 268       break;
 269    default:
 270       ptr = NULL;
 271       size = 0;
 272       break;
 273    }
 274
 275    if (ret)
 276       memcpy(ret, ptr, size);
 277
 278    return size;
 279 }
 280
 281 static int
 282 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 283 {
 284    struct ilo_screen *is = ilo_screen(screen);
 285
 286    switch (param) {
 287    case PIPE_CAP_NPOT_TEXTURES:
 288    case PIPE_CAP_TWO_SIDED_STENCIL:
 289       return true;
 290    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 291       return 0; /* TODO */
 292    case PIPE_CAP_ANISOTROPIC_FILTER:
 293    case PIPE_CAP_POINT_SPRITE:
 294       return true;
 295    case PIPE_CAP_MAX_RENDER_TARGETS:
 296       return ILO_MAX_DRAW_BUFFERS;
 297    case PIPE_CAP_OCCLUSION_QUERY:
 298    case PIPE_CAP_QUERY_TIME_ELAPSED:
 299    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 300    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 301       return true;
 302    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 303       /*
 304        * As defined in SURFACE_STATE, we have
 305        *
 306        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 307        *  GEN6           8192x8192x512            2048x2048x2048
 308        *  GEN7         16384x16384x2048           2048x2048x2048
 309        *
 310        * However, when the texutre size is large, things become unstable.  We
 311        * require the maximum texture size to be 2^30 bytes in
 312        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 313        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 314        * than 2^26 pixels.
 315        *
 316        * For 3D textures, we have to set the maximum number of levels to 9,
 317        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 318        * which has at most 2^26 pixels.  And for cube textures, we has to set
 319        * it to 12.
 320        */
 321       return 14;
 322    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 323       return 9;
 324    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 325       return 12;
 326    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 327       return false;
 328    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 329    case PIPE_CAP_SM3:
 330       return true;
 331    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 332       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 333          return 0;
 334       return ILO_MAX_SO_BUFFERS;
 335    case PIPE_CAP_PRIMITIVE_RESTART:
 336       return true;
 337    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 338       return ILO_MAX_SAMPLERS * 2;
 339    case PIPE_CAP_INDEP_BLEND_ENABLE:
 340    case PIPE_CAP_INDEP_BLEND_FUNC:
 341       return true;
 342    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 343       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 344    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 345    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 346    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 347    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 348    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 349       return true;
 350    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 351       return false;
 352    case PIPE_CAP_TGSI_INSTANCEID:
 353    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 354       return true;
 355    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 356       return false;
 357    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 358       return true;
 359    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 360    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 361    case PIPE_CAP_SCALED_RESOLVE:
 362       return true;
 363    case PIPE_CAP_MIN_TEXEL_OFFSET:
 364       return -8;
 365    case PIPE_CAP_MAX_TEXEL_OFFSET:
 366       return 7;
 367    case PIPE_CAP_CONDITIONAL_RENDER:
 368    case PIPE_CAP_TEXTURE_BARRIER:
 369       return true;
 370    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 371       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 372    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 373       return ILO_MAX_SO_BINDINGS;
 374    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 375       if (is->dev.gen >= ILO_GEN(7))
 376          return is->dev.has_gen7_sol_reset;
 377       else
 378          return false; /* TODO */
 379    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 380       return false;
 381    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 382       return true;
 383    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 384       return false;
 385    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 386       return 140;
 387    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 388    case PIPE_CAP_USER_VERTEX_BUFFERS:
 389       return false;
 390    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 391    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 392    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 393       return false;
 394    case PIPE_CAP_COMPUTE:
 395       return false; /* TODO */
 396    case PIPE_CAP_USER_INDEX_BUFFERS:
 397    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 398       return true;
 399    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 400       /* imposed by OWord (Dual) Block Read */
 401       return 16;
 402    case PIPE_CAP_START_INSTANCE:
 403    case PIPE_CAP_QUERY_TIMESTAMP:
 404       return true;
 405    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 406       return false; /* TODO */
 407    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 408       return 0;
 409    case PIPE_CAP_CUBE_MAP_ARRAY:
 410    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 411       return true;
 412    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 413       return 1;
 414    case PIPE_CAP_TGSI_TEXCOORD:
 415       return false;
 416    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 417       return true;
 418    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 419       return false; /* TODO */
 420    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 421       return 0;
 422    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 423       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
 424       return 1 << 27;
 425    case PIPE_CAP_MAX_VIEWPORTS:
 426       return ILO_MAX_VIEWPORTS;
 427    case PIPE_CAP_ENDIANNESS:
 428       return PIPE_ENDIAN_LITTLE;
 429
 430    default:
 431       return 0;
 432    }
 433 }
 434
 435 static const char *
 436 ilo_get_vendor(struct pipe_screen *screen)
 437 {
 438    return "LunarG, Inc.";
 439 }
 440
 441 static const char *
 442 ilo_get_name(struct pipe_screen *screen)
 443 {
 444    struct ilo_screen *is = ilo_screen(screen);
 445    const char *chipset;
 446
 447    /* stolen from classic i965 */
 448    switch (is->dev.devid) {
 449    case PCI_CHIP_SANDYBRIDGE_GT1:
 450    case PCI_CHIP_SANDYBRIDGE_GT2:
 451    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 452       chipset = "Intel(R) Sandybridge Desktop";
 453       break;
 454    case PCI_CHIP_SANDYBRIDGE_M_GT1:
 455    case PCI_CHIP_SANDYBRIDGE_M_GT2:
 456    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 457       chipset = "Intel(R) Sandybridge Mobile";
 458       break;
 459    case PCI_CHIP_SANDYBRIDGE_S:
 460       chipset = "Intel(R) Sandybridge Server";
 461       break;
 462    case PCI_CHIP_IVYBRIDGE_GT1:
 463    case PCI_CHIP_IVYBRIDGE_GT2:
 464       chipset = "Intel(R) Ivybridge Desktop";
 465       break;
 466    case PCI_CHIP_IVYBRIDGE_M_GT1:
 467    case PCI_CHIP_IVYBRIDGE_M_GT2:
 468       chipset = "Intel(R) Ivybridge Mobile";
 469       break;
 470    case PCI_CHIP_IVYBRIDGE_S_GT1:
 471    case PCI_CHIP_IVYBRIDGE_S_GT2:
 472       chipset = "Intel(R) Ivybridge Server";
 473       break;
 474    case PCI_CHIP_BAYTRAIL_M_1:
 475    case PCI_CHIP_BAYTRAIL_M_2:
 476    case PCI_CHIP_BAYTRAIL_M_3:
 477    case PCI_CHIP_BAYTRAIL_M_4:
 478    case PCI_CHIP_BAYTRAIL_D:
 479       chipset = "Intel(R) Bay Trail";
 480       break;
 481    case PCI_CHIP_HASWELL_GT1:
 482    case PCI_CHIP_HASWELL_GT2:
 483    case PCI_CHIP_HASWELL_GT3:
 484    case PCI_CHIP_HASWELL_SDV_GT1:
 485    case PCI_CHIP_HASWELL_SDV_GT2:
 486    case PCI_CHIP_HASWELL_SDV_GT3:
 487    case PCI_CHIP_HASWELL_ULT_GT1:
 488    case PCI_CHIP_HASWELL_ULT_GT2:
 489    case PCI_CHIP_HASWELL_ULT_GT3:
 490    case PCI_CHIP_HASWELL_CRW_GT1:
 491    case PCI_CHIP_HASWELL_CRW_GT2:
 492    case PCI_CHIP_HASWELL_CRW_GT3:
 493       chipset = "Intel(R) Haswell Desktop";
 494       break;
 495    case PCI_CHIP_HASWELL_M_GT1:
 496    case PCI_CHIP_HASWELL_M_GT2:
 497    case PCI_CHIP_HASWELL_M_GT3:
 498    case PCI_CHIP_HASWELL_SDV_M_GT1:
 499    case PCI_CHIP_HASWELL_SDV_M_GT2:
 500    case PCI_CHIP_HASWELL_SDV_M_GT3:
 501    case PCI_CHIP_HASWELL_ULT_M_GT1:
 502    case PCI_CHIP_HASWELL_ULT_M_GT2:
 503    case PCI_CHIP_HASWELL_ULT_M_GT3:
 504    case PCI_CHIP_HASWELL_CRW_M_GT1:
 505    case PCI_CHIP_HASWELL_CRW_M_GT2:
 506    case PCI_CHIP_HASWELL_CRW_M_GT3:
 507       chipset = "Intel(R) Haswell Mobile";
 508       break;
 509    case PCI_CHIP_HASWELL_S_GT1:
 510    case PCI_CHIP_HASWELL_S_GT2:
 511    case PCI_CHIP_HASWELL_S_GT3:
 512    case PCI_CHIP_HASWELL_SDV_S_GT1:
 513    case PCI_CHIP_HASWELL_SDV_S_GT2:
 514    case PCI_CHIP_HASWELL_SDV_S_GT3:
 515    case PCI_CHIP_HASWELL_ULT_S_GT1:
 516    case PCI_CHIP_HASWELL_ULT_S_GT2:
 517    case PCI_CHIP_HASWELL_ULT_S_GT3:
 518    case PCI_CHIP_HASWELL_CRW_S_GT1:
 519    case PCI_CHIP_HASWELL_CRW_S_GT2:
 520    case PCI_CHIP_HASWELL_CRW_S_GT3:
 521       chipset = "Intel(R) Haswell Server";
 522       break;
 523    default:
 524       chipset = "Unknown Intel Chipset";
 525       break;
 526    }
 527
 528    return chipset;
 529 }
 530
 531 static uint64_t
 532 ilo_get_timestamp(struct pipe_screen *screen)
 533 {
 534    struct ilo_screen *is = ilo_screen(screen);
 535    union {
 536       uint64_t val;
 537       uint32_t dw[2];
 538    } timestamp;
 539
 540    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 541
 542    /*
 543     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 544     *
 545     *     "Note: This timestamp register reflects the value of the PCU TSC.
 546     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 547     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 548     *      hours)."
 549     *
 550     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 551     * of the timestamp.  We will have to live with a timestamp that rolls over
 552     * every ~343 seconds.
 553     *
 554     * See also brw_get_timestamp().
 555     */
 556    return (uint64_t) timestamp.dw[1] * 80;
 557 }
 558
 559 static void
 560 ilo_fence_reference(struct pipe_screen *screen,
 561                     struct pipe_fence_handle **p,
 562                     struct pipe_fence_handle *f)
 563 {
 564    struct ilo_fence **ptr = (struct ilo_fence **) p;
 565    struct ilo_fence *fence = ilo_fence(f);
 566
 567    if (!ptr) {
 568       /* still need to reference fence */
 569       if (fence)
 570          pipe_reference(NULL, &fence->reference);
 571       return;
 572    }
 573
 574    /* reference fence and dereference the one pointed to by ptr */
 575    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
 576       struct ilo_fence *old = *ptr;
 577
 578       if (old->bo)
 579          intel_bo_unreference(old->bo);
 580       FREE(old);
 581    }
 582
 583    *ptr = fence;
 584 }
 585
 586 static boolean
 587 ilo_fence_signalled(struct pipe_screen *screen,
 588                     struct pipe_fence_handle *f)
 589 {
 590    struct ilo_fence *fence = ilo_fence(f);
 591
 592    /* mark signalled if the bo is idle */
 593    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 594       intel_bo_unreference(fence->bo);
 595       fence->bo = NULL;
 596    }
 597
 598    return (fence->bo == NULL);
 599 }
 600
 601 static boolean
 602 ilo_fence_finish(struct pipe_screen *screen,
 603                  struct pipe_fence_handle *f,
 604                  uint64_t timeout)
 605 {
 606    struct ilo_fence *fence = ilo_fence(f);
 607    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 608
 609    /* already signalled */
 610    if (!fence->bo)
 611       return true;
 612
 613    /* wait and see if it returns error */
 614    if (intel_bo_wait(fence->bo, wait_timeout))
 615       return false;
 616
 617    /* mark signalled */
 618    intel_bo_unreference(fence->bo);
 619    fence->bo = NULL;
 620
 621    return true;
 622 }
 623
 624 static void
 625 ilo_screen_destroy(struct pipe_screen *screen)
 626 {
 627    struct ilo_screen *is = ilo_screen(screen);
 628
 629    /* as it seems, winsys is owned by the screen */
 630    intel_winsys_destroy(is->winsys);
 631
 632    FREE(is);
 633 }
 634
 635 static bool
 636 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 637 {
 638    dev->devid = info->devid;
 639    dev->has_llc = info->has_llc;
 640    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 641    dev->has_address_swizzling = info->has_address_swizzling;
 642
 643    /*
 644     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 645     *
 646     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 647     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 648     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 649     *      to an EU GRF register. Read/write access to the URB is generally
 650     *      supported on a row-granular basis."
 651     *
 652     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 653     *
 654     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 655     *      128k        4096        2048
 656     *      256k        8096        4096"
 657     */
 658
 659    if (IS_HASWELL(info->devid)) {
 660       dev->gen = ILO_GEN(7.5);
 661
 662       if (IS_HSW_GT3(info->devid)) {
 663          dev->gt = 3;
 664          dev->urb_size = 512 * 1024;
 665       }
 666       else if (IS_HSW_GT2(info->devid)) {
 667          dev->gt = 2;
 668          dev->urb_size = 256 * 1024;
 669       }
 670       else {
 671          dev->gt = 1;
 672          dev->urb_size = 128 * 1024;
 673       }
 674    }
 675    else if (IS_GEN7(info->devid)) {
 676       dev->gen = ILO_GEN(7);
 677
 678       if (IS_IVB_GT2(info->devid)) {
 679          dev->gt = 2;
 680          dev->urb_size = 256 * 1024;
 681       }
 682       else {
 683          dev->gt = 1;
 684          dev->urb_size = 128 * 1024;
 685       }
 686    }
 687    else if (IS_GEN6(info->devid)) {
 688       dev->gen = ILO_GEN(6);
 689
 690       if (IS_SNB_GT2(info->devid)) {
 691          dev->gt = 2;
 692          dev->urb_size = 64 * 1024;
 693       }
 694       else {
 695          dev->gt = 1;
 696          dev->urb_size = 32 * 1024;
 697       }
 698    }
 699    else {
 700       ilo_err("unknown GPU generation\n");
 701       return false;
 702    }
 703
 704    return true;
 705 }
 706
 707 struct pipe_screen *
 708 ilo_screen_create(struct intel_winsys *ws)
 709 {
 710    struct ilo_screen *is;
 711    const struct intel_winsys_info *info;
 712
 713    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 714
 715    is = CALLOC_STRUCT(ilo_screen);
 716    if (!is)
 717       return NULL;
 718
 719    is->winsys = ws;
 720
 721    intel_winsys_enable_reuse(is->winsys);
 722
 723    info = intel_winsys_get_info(is->winsys);
 724    if (!init_dev(&is->dev, info)) {
 725       FREE(is);
 726       return NULL;
 727    }
 728
 729    util_format_s3tc_init();
 730
 731    is->base.destroy = ilo_screen_destroy;
 732    is->base.get_name = ilo_get_name;
 733    is->base.get_vendor = ilo_get_vendor;
 734    is->base.get_param = ilo_get_param;
 735    is->base.get_paramf = ilo_get_paramf;
 736    is->base.get_shader_param = ilo_get_shader_param;
 737    is->base.get_video_param = ilo_get_video_param;
 738    is->base.get_compute_param = ilo_get_compute_param;
 739
 740    is->base.get_timestamp = ilo_get_timestamp;
 741
 742    is->base.flush_frontbuffer = NULL;
 743
 744    is->base.fence_reference = ilo_fence_reference;
 745    is->base.fence_signalled = ilo_fence_signalled;
 746    is->base.fence_finish = ilo_fence_finish;
 747
 748    is->base.get_driver_query_info = NULL;
 749
 750    ilo_init_format_functions(is);
 751    ilo_init_context_functions(is);
 752    ilo_init_resource_functions(is);
 753
 754    return &is->base;
 755 }