2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "pipe/p_state.h"
29 #include "os/os_misc.h"
30 #include "util/u_format_s3tc.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
34 #include "intel_winsys.h"
36 #include "ilo_context.h"
37 #include "ilo_format.h"
38 #include "ilo_resource.h"
39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
40 #include "ilo_public.h"
41 #include "ilo_screen.h"
44 struct pipe_reference reference
;
50 static const struct debug_named_value ilo_debug_flags
[] = {
51 { "batch", ILO_DEBUG_BATCH
, "Dump batch/state/surface/instruction buffers" },
52 { "vs", ILO_DEBUG_VS
, "Dump vertex shaders" },
53 { "gs", ILO_DEBUG_GS
, "Dump geometry shaders" },
54 { "fs", ILO_DEBUG_FS
, "Dump fragment shaders" },
55 { "cs", ILO_DEBUG_CS
, "Dump compute shaders" },
56 { "draw", ILO_DEBUG_DRAW
, "Show draw information" },
57 { "submit", ILO_DEBUG_SUBMIT
, "Show batch buffer submissions" },
58 { "nohw", ILO_DEBUG_NOHW
, "Do not send commands to HW" },
59 { "nocache", ILO_DEBUG_NOCACHE
, "Always invalidate HW caches" },
60 { "nohiz", ILO_DEBUG_NOHIZ
, "Disable HiZ" },
65 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
68 case PIPE_CAPF_MAX_LINE_WIDTH
:
69 /* in U3.7, defined in 3DSTATE_SF */
71 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
72 /* line width minus one, which is reserved for AA region */
74 case PIPE_CAPF_MAX_POINT_WIDTH
:
75 /* in U8.3, defined in 3DSTATE_SF */
77 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
78 /* same as point width, as we ignore rasterizer->point_smooth */
80 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
81 /* [2.0, 16.0], defined in SAMPLER_STATE */
83 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
84 /* [-16.0, 16.0), defined in SAMPLER_STATE */
86 case PIPE_CAPF_GUARD_BAND_LEFT
:
87 case PIPE_CAPF_GUARD_BAND_TOP
:
88 case PIPE_CAPF_GUARD_BAND_RIGHT
:
89 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
90 /* what are these for? */
99 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
100 enum pipe_shader_cap param
)
103 case PIPE_SHADER_FRAGMENT
:
104 case PIPE_SHADER_VERTEX
:
105 case PIPE_SHADER_GEOMETRY
:
112 /* the limits are copied from the classic driver */
113 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
114 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
115 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
116 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
117 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
118 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
119 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
120 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
121 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
123 case PIPE_SHADER_CAP_MAX_INPUTS
:
124 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
125 /* this is limited by how many attributes SF can remap */
127 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
128 return 1024 * sizeof(float[4]);
129 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
130 return ILO_MAX_CONST_BUFFERS
;
131 case PIPE_SHADER_CAP_MAX_TEMPS
:
133 case PIPE_SHADER_CAP_MAX_PREDS
:
135 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
137 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
139 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
141 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
142 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
143 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
145 case PIPE_SHADER_CAP_SUBROUTINES
:
147 case PIPE_SHADER_CAP_INTEGERS
:
149 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
150 return ILO_MAX_SAMPLERS
;
151 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
152 return ILO_MAX_SAMPLER_VIEWS
;
153 case PIPE_SHADER_CAP_PREFERRED_IR
:
154 return PIPE_SHADER_IR_TGSI
;
155 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
164 ilo_get_video_param(struct pipe_screen
*screen
,
165 enum pipe_video_profile profile
,
166 enum pipe_video_entrypoint entrypoint
,
167 enum pipe_video_cap param
)
170 case PIPE_VIDEO_CAP_SUPPORTED
:
171 return vl_profile_supported(screen
, profile
, entrypoint
);
172 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
174 case PIPE_VIDEO_CAP_MAX_WIDTH
:
175 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
176 return vl_video_buffer_max_size(screen
);
177 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
178 return PIPE_FORMAT_NV12
;
179 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
181 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
183 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
185 case PIPE_VIDEO_CAP_MAX_LEVEL
:
186 return vl_level_supported(screen
, profile
);
193 ilo_get_compute_param(struct pipe_screen
*screen
,
194 enum pipe_compute_cap param
,
197 struct ilo_screen
*is
= ilo_screen(screen
);
199 const char *ir_target
;
200 uint64_t grid_dimension
;
201 uint64_t max_grid_size
[3];
202 uint64_t max_block_size
[3];
203 uint64_t max_threads_per_block
;
204 uint64_t max_global_size
;
205 uint64_t max_local_size
;
206 uint64_t max_private_size
;
207 uint64_t max_input_size
;
208 uint64_t max_mem_alloc_size
;
209 uint32_t max_clock_frequency
;
210 uint32_t max_compute_units
;
211 uint32_t images_supported
;
217 case PIPE_COMPUTE_CAP_IR_TARGET
:
218 val
.ir_target
= "ilog";
221 size
= strlen(val
.ir_target
) + 1;
223 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
224 val
.grid_dimension
= Elements(val
.max_grid_size
);
226 ptr
= &val
.grid_dimension
;
227 size
= sizeof(val
.grid_dimension
);
229 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
230 val
.max_grid_size
[0] = 0xffffffffu
;
231 val
.max_grid_size
[1] = 0xffffffffu
;
232 val
.max_grid_size
[2] = 0xffffffffu
;
234 ptr
= &val
.max_grid_size
;
235 size
= sizeof(val
.max_grid_size
);
237 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
238 val
.max_block_size
[0] = 1024;
239 val
.max_block_size
[1] = 1024;
240 val
.max_block_size
[2] = 1024;
242 ptr
= &val
.max_block_size
;
243 size
= sizeof(val
.max_block_size
);
246 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
247 val
.max_threads_per_block
= 1024;
249 ptr
= &val
.max_threads_per_block
;
250 size
= sizeof(val
.max_threads_per_block
);
252 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
253 /* \see ilo_max_resource_size */
254 val
.max_global_size
= 1u << 31;
256 ptr
= &val
.max_global_size
;
257 size
= sizeof(val
.max_global_size
);
259 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
260 /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
261 val
.max_local_size
= 64 * 1024;
263 ptr
= &val
.max_local_size
;
264 size
= sizeof(val
.max_local_size
);
266 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
268 val
.max_private_size
= 12 * 1024;
270 ptr
= &val
.max_private_size
;
271 size
= sizeof(val
.max_private_size
);
273 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
274 val
.max_input_size
= 1024;
276 ptr
= &val
.max_input_size
;
277 size
= sizeof(val
.max_input_size
);
279 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
280 val
.max_mem_alloc_size
= 1u << 31;
282 ptr
= &val
.max_mem_alloc_size
;
283 size
= sizeof(val
.max_mem_alloc_size
);
285 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
286 val
.max_clock_frequency
= 1000;
288 ptr
= &val
.max_clock_frequency
;
289 size
= sizeof(val
.max_clock_frequency
);
291 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
292 val
.max_compute_units
= is
->dev
.eu_count
;
294 ptr
= &val
.max_compute_units
;
295 size
= sizeof(val
.max_compute_units
);
297 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
298 val
.images_supported
= 1;
300 ptr
= &val
.images_supported
;
301 size
= sizeof(val
.images_supported
);
310 memcpy(ret
, ptr
, size
);
316 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
318 struct ilo_screen
*is
= ilo_screen(screen
);
321 case PIPE_CAP_NPOT_TEXTURES
:
322 case PIPE_CAP_TWO_SIDED_STENCIL
:
324 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
326 case PIPE_CAP_ANISOTROPIC_FILTER
:
327 case PIPE_CAP_POINT_SPRITE
:
329 case PIPE_CAP_MAX_RENDER_TARGETS
:
330 return ILO_MAX_DRAW_BUFFERS
;
331 case PIPE_CAP_OCCLUSION_QUERY
:
332 case PIPE_CAP_QUERY_TIME_ELAPSED
:
333 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
334 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
336 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
338 * As defined in SURFACE_STATE, we have
340 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
341 * GEN6 8192x8192x512 2048x2048x2048
342 * GEN7 16384x16384x2048 2048x2048x2048
344 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
345 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
347 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
348 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
349 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
351 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
354 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
355 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
357 return ILO_MAX_SO_BUFFERS
;
358 case PIPE_CAP_PRIMITIVE_RESTART
:
360 case PIPE_CAP_INDEP_BLEND_ENABLE
:
361 case PIPE_CAP_INDEP_BLEND_FUNC
:
363 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
364 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 2048 : 512;
365 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
366 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
367 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
368 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
369 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
371 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
373 case PIPE_CAP_TGSI_INSTANCEID
:
374 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
376 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
378 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
380 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
381 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
383 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
384 case PIPE_CAP_MIN_TEXEL_OFFSET
:
386 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
387 case PIPE_CAP_MAX_TEXEL_OFFSET
:
389 case PIPE_CAP_CONDITIONAL_RENDER
:
390 case PIPE_CAP_TEXTURE_BARRIER
:
392 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
393 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
394 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
395 return ILO_MAX_SO_BINDINGS
;
396 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
397 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7))
398 return is
->dev
.has_gen7_sol_reset
;
400 return false; /* TODO */
401 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
403 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
405 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
407 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
409 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
410 case PIPE_CAP_USER_VERTEX_BUFFERS
:
412 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
413 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
414 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
416 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
418 case PIPE_CAP_COMPUTE
:
419 return false; /* TODO */
420 case PIPE_CAP_USER_INDEX_BUFFERS
:
421 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
423 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
424 /* imposed by OWord (Dual) Block Read */
426 case PIPE_CAP_START_INSTANCE
:
428 case PIPE_CAP_QUERY_TIMESTAMP
:
429 return is
->dev
.has_timestamp
;
430 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
431 return false; /* TODO */
432 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
433 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
434 case PIPE_CAP_CUBE_MAP_ARRAY
:
435 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
437 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
439 case PIPE_CAP_TGSI_TEXCOORD
:
441 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
442 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
444 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
446 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
447 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
449 case PIPE_CAP_MAX_VIEWPORTS
:
450 return ILO_MAX_VIEWPORTS
;
451 case PIPE_CAP_ENDIANNESS
:
452 return PIPE_ENDIAN_LITTLE
;
453 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
455 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
456 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
457 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
458 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
459 case PIPE_CAP_TEXTURE_GATHER_SM5
:
461 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
463 case PIPE_CAP_FAKE_SW_MSAA
:
464 case PIPE_CAP_TEXTURE_QUERY_LOD
:
465 case PIPE_CAP_SAMPLE_SHADING
:
466 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
467 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
468 case PIPE_CAP_MAX_VERTEX_STREAMS
:
469 case PIPE_CAP_DRAW_INDIRECT
:
470 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
471 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
472 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
473 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
476 case PIPE_CAP_VENDOR_ID
:
478 case PIPE_CAP_DEVICE_ID
:
479 return is
->dev
.devid
;
480 case PIPE_CAP_ACCELERATED
:
482 case PIPE_CAP_VIDEO_MEMORY
: {
483 /* Once a batch uses more than 75% of the maximum mappable size, we
484 * assume that there's some fragmentation, and we start doing extra
485 * flushing, etc. That's the big cliff apps will care about.
487 const uint64_t gpu_memory
= is
->dev
.aperture_total
* 3 / 4;
488 uint64_t system_memory
;
490 if (!os_get_total_physical_memory(&system_memory
))
493 return (int) (MIN2(gpu_memory
, system_memory
) >> 20);
497 case PIPE_CAP_CLIP_HALFZ
:
499 case PIPE_CAP_VERTEXID_NOBASE
:
501 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
510 ilo_get_vendor(struct pipe_screen
*screen
)
512 return "LunarG, Inc.";
516 ilo_get_name(struct pipe_screen
*screen
)
518 struct ilo_screen
*is
= ilo_screen(screen
);
519 const char *chipset
= NULL
;
521 if (gen_is_chv(is
->dev
.devid
)) {
522 chipset
= "Intel(R) Cherryview";
523 } else if (gen_is_bdw(is
->dev
.devid
)) {
524 /* this is likely wrong */
525 if (gen_is_desktop(is
->dev
.devid
))
526 chipset
= "Intel(R) Broadwell Desktop";
527 else if (gen_is_mobile(is
->dev
.devid
))
528 chipset
= "Intel(R) Broadwell Mobile";
529 else if (gen_is_server(is
->dev
.devid
))
530 chipset
= "Intel(R) Broadwell Server";
531 } else if (gen_is_vlv(is
->dev
.devid
)) {
532 chipset
= "Intel(R) Bay Trail";
533 } else if (gen_is_hsw(is
->dev
.devid
)) {
534 if (gen_is_desktop(is
->dev
.devid
))
535 chipset
= "Intel(R) Haswell Desktop";
536 else if (gen_is_mobile(is
->dev
.devid
))
537 chipset
= "Intel(R) Haswell Mobile";
538 else if (gen_is_server(is
->dev
.devid
))
539 chipset
= "Intel(R) Haswell Server";
540 } else if (gen_is_ivb(is
->dev
.devid
)) {
541 if (gen_is_desktop(is
->dev
.devid
))
542 chipset
= "Intel(R) Ivybridge Desktop";
543 else if (gen_is_mobile(is
->dev
.devid
))
544 chipset
= "Intel(R) Ivybridge Mobile";
545 else if (gen_is_server(is
->dev
.devid
))
546 chipset
= "Intel(R) Ivybridge Server";
547 } else if (gen_is_snb(is
->dev
.devid
)) {
548 if (gen_is_desktop(is
->dev
.devid
))
549 chipset
= "Intel(R) Sandybridge Desktop";
550 else if (gen_is_mobile(is
->dev
.devid
))
551 chipset
= "Intel(R) Sandybridge Mobile";
552 else if (gen_is_server(is
->dev
.devid
))
553 chipset
= "Intel(R) Sandybridge Server";
557 chipset
= "Unknown Intel Chipset";
563 ilo_get_timestamp(struct pipe_screen
*screen
)
565 struct ilo_screen
*is
= ilo_screen(screen
);
571 intel_winsys_read_reg(is
->winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
574 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
576 * "Note: This timestamp register reflects the value of the PCU TSC.
577 * The PCU TSC counts 10ns increments; this timestamp reflects bits
578 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
581 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
582 * of the timestamp. We will have to live with a timestamp that rolls over
583 * every ~343 seconds.
585 * See also brw_get_timestamp().
587 return (uint64_t) timestamp
.dw
[1] * 80;
591 ilo_fence_reference(struct pipe_screen
*screen
,
592 struct pipe_fence_handle
**p
,
593 struct pipe_fence_handle
*f
)
595 struct ilo_fence
*fence
= ilo_fence(f
);
596 struct ilo_fence
*old
;
606 STATIC_ASSERT(&((struct ilo_fence
*) NULL
)->reference
== NULL
);
607 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
609 intel_bo_unreference(old
->bo
);
615 ilo_fence_signalled(struct pipe_screen
*screen
,
616 struct pipe_fence_handle
*f
)
618 struct ilo_fence
*fence
= ilo_fence(f
);
620 /* mark signalled if the bo is idle */
621 if (fence
->bo
&& !intel_bo_is_busy(fence
->bo
)) {
622 intel_bo_unreference(fence
->bo
);
626 return (fence
->bo
== NULL
);
630 ilo_fence_finish(struct pipe_screen
*screen
,
631 struct pipe_fence_handle
*f
,
634 struct ilo_fence
*fence
= ilo_fence(f
);
635 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
637 /* already signalled */
641 /* wait and see if it returns error */
642 if (intel_bo_wait(fence
->bo
, wait_timeout
))
646 intel_bo_unreference(fence
->bo
);
653 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
654 * before waited on or checked.
657 ilo_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
659 struct ilo_fence
*fence
;
661 fence
= CALLOC_STRUCT(ilo_fence
);
665 pipe_reference_init(&fence
->reference
, 1);
668 intel_bo_reference(bo
);
675 ilo_screen_destroy(struct pipe_screen
*screen
)
677 struct ilo_screen
*is
= ilo_screen(screen
);
679 /* as it seems, winsys is owned by the screen */
680 intel_winsys_destroy(is
->winsys
);
686 init_dev(struct ilo_dev_info
*dev
, const struct intel_winsys_info
*info
)
688 dev
->devid
= info
->devid
;
689 dev
->aperture_total
= info
->aperture_total
;
690 dev
->aperture_mappable
= info
->aperture_mappable
;
691 dev
->has_llc
= info
->has_llc
;
692 dev
->has_address_swizzling
= info
->has_address_swizzling
;
693 dev
->has_logical_context
= info
->has_logical_context
;
694 dev
->has_ppgtt
= info
->has_ppgtt
;
695 dev
->has_timestamp
= info
->has_timestamp
;
696 dev
->has_gen7_sol_reset
= info
->has_gen7_sol_reset
;
698 if (!dev
->has_logical_context
) {
699 ilo_err("missing hardware logical context support\n");
704 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
707 * From the Sandy Bridge PRM, volume 1 part 3, page 101:
709 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
710 * code is in a secure environment, independent of address space.
711 * Under this condition, this bit only specifies the address space
712 * (GGTT or PPGTT). All commands are executed "as-is""
714 * We need PPGTT to be enabled on GEN6 too.
716 if (!dev
->has_ppgtt
) {
717 /* experiments show that it does not really matter... */
718 ilo_warn("PPGTT disabled\n");
721 if (gen_is_bdw(info
->devid
) || gen_is_chv(info
->devid
)) {
722 dev
->gen_opaque
= ILO_GEN(8);
723 dev
->gt
= (gen_is_bdw(info
->devid
)) ? gen_get_bdw_gt(info
->devid
) : 1;
724 /* XXX random values */
727 dev
->thread_count
= 336;
728 dev
->urb_size
= 384 * 1024;
729 } else if (dev
->gt
== 2) {
731 dev
->thread_count
= 168;
732 dev
->urb_size
= 384 * 1024;
735 dev
->thread_count
= 84;
736 dev
->urb_size
= 192 * 1024;
738 } else if (gen_is_hsw(info
->devid
)) {
740 * From the Haswell PRM, volume 4, page 8:
742 * "Description GT3 GT2 GT1.5 GT1
744 * EUs (Total) 40 20 12 10
745 * Threads (Total) 280 140 84 70
747 * URB Size (max, within L3$) 512KB 256KB 256KB 128KB
749 dev
->gen_opaque
= ILO_GEN(7.5);
750 dev
->gt
= gen_get_hsw_gt(info
->devid
);
753 dev
->thread_count
= 280;
754 dev
->urb_size
= 512 * 1024;
755 } else if (dev
->gt
== 2) {
757 dev
->thread_count
= 140;
758 dev
->urb_size
= 256 * 1024;
761 dev
->thread_count
= 70;
762 dev
->urb_size
= 128 * 1024;
764 } else if (gen_is_ivb(info
->devid
) || gen_is_vlv(info
->devid
)) {
766 * From the Ivy Bridge PRM, volume 1 part 1, page 18:
768 * "Device # of EUs #Threads/EU
769 * Ivy Bridge (GT2) 16 8
770 * Ivy Bridge (GT1) 6 6"
772 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
774 * "URB Size URB Rows URB Rows when SLM Enabled
778 dev
->gen_opaque
= ILO_GEN(7);
779 dev
->gt
= (gen_is_ivb(info
->devid
)) ? gen_get_ivb_gt(info
->devid
) : 1;
782 dev
->thread_count
= 128;
783 dev
->urb_size
= 256 * 1024;
786 dev
->thread_count
= 36;
787 dev
->urb_size
= 128 * 1024;
789 } else if (gen_is_snb(info
->devid
)) {
791 * From the Sandy Bridge PRM, volume 1 part 1, page 22:
793 * "Device # of EUs #Threads/EU
797 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
799 * "[DevSNB]: The GT1 product's URB provides 32KB of storage,
800 * arranged as 1024 256-bit rows. The GT2 product's URB provides
801 * 64KB of storage, arranged as 2048 256-bit rows. A row
802 * corresponds in size to an EU GRF register. Read/write access to
803 * the URB is generally supported on a row-granular basis."
805 dev
->gen_opaque
= ILO_GEN(6);
806 dev
->gt
= gen_get_snb_gt(info
->devid
);
809 dev
->thread_count
= 60;
810 dev
->urb_size
= 64 * 1024;
813 dev
->thread_count
= 24;
814 dev
->urb_size
= 32 * 1024;
817 ilo_err("unknown GPU generation\n");
825 ilo_screen_create(struct intel_winsys
*ws
)
827 struct ilo_screen
*is
;
828 const struct intel_winsys_info
*info
;
830 ilo_debug
= debug_get_flags_option("ILO_DEBUG", ilo_debug_flags
, 0);
832 is
= CALLOC_STRUCT(ilo_screen
);
838 info
= intel_winsys_get_info(is
->winsys
);
839 if (!init_dev(&is
->dev
, info
)) {
844 util_format_s3tc_init();
846 is
->base
.destroy
= ilo_screen_destroy
;
847 is
->base
.get_name
= ilo_get_name
;
848 is
->base
.get_vendor
= ilo_get_vendor
;
849 is
->base
.get_param
= ilo_get_param
;
850 is
->base
.get_paramf
= ilo_get_paramf
;
851 is
->base
.get_shader_param
= ilo_get_shader_param
;
852 is
->base
.get_video_param
= ilo_get_video_param
;
853 is
->base
.get_compute_param
= ilo_get_compute_param
;
855 is
->base
.get_timestamp
= ilo_get_timestamp
;
857 is
->base
.flush_frontbuffer
= NULL
;
859 is
->base
.fence_reference
= ilo_fence_reference
;
860 is
->base
.fence_signalled
= ilo_fence_signalled
;
861 is
->base
.fence_finish
= ilo_fence_finish
;
863 is
->base
.get_driver_query_info
= NULL
;
865 ilo_init_format_functions(is
);
866 ilo_init_context_functions(is
);
867 ilo_init_resource_functions(is
);