src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "intel_chipset.h"
  32 #include "intel_reg.h" /* for TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_public.h"
  39 #include "ilo_screen.h"
  40
  41 int ilo_debug;
  42
  43 static const struct debug_named_value ilo_debug_flags[] = {
  44    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  50    { "flush",     ILO_DEBUG_FLUSH,    "Show batch buffer flushes" },
  51    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  52    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  53    DEBUG_NAMED_VALUE_END
  54 };
  55
  56 static float
  57 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  58 {
  59    switch (param) {
  60    case PIPE_CAPF_MAX_LINE_WIDTH:
  61       /* in U3.7, defined in 3DSTATE_SF */
  62       return 7.0f;
  63    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  64       /* line width minus one, which is reserved for AA region */
  65       return 6.0f;
  66    case PIPE_CAPF_MAX_POINT_WIDTH:
  67       /* in U8.3, defined in 3DSTATE_SF */
  68       return 255.0f;
  69    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  70       /* same as point width, as we ignore rasterizer->point_smooth */
  71       return 255.0f;
  72    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  73       /* [2.0, 16.0], defined in SAMPLER_STATE */
  74       return 16.0f;
  75    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  76       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  77       return 15.0f;
  78    case PIPE_CAPF_GUARD_BAND_LEFT:
  79    case PIPE_CAPF_GUARD_BAND_TOP:
  80    case PIPE_CAPF_GUARD_BAND_RIGHT:
  81    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  82       /* what are these for? */
  83       return 0.0f;
  84
  85    default:
  86       return 0.0f;
  87    }
  88 }
  89
  90 static int
  91 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  92                      enum pipe_shader_cap param)
  93 {
  94    switch (shader) {
  95    case PIPE_SHADER_FRAGMENT:
  96    case PIPE_SHADER_VERTEX:
  97    case PIPE_SHADER_GEOMETRY:
  98       break;
  99    default:
 100       return 0;
 101    }
 102
 103    switch (param) {
 104    /* the limits are copied from the classic driver */
 105    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 106       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 107    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 108       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 109    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 110       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 111    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 112       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 113    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 114       return UINT_MAX;
 115    case PIPE_SHADER_CAP_MAX_INPUTS:
 116       /* this is limited by how many attributes SF can remap */
 117       return 16;
 118    case PIPE_SHADER_CAP_MAX_CONSTS:
 119       return 1024;
 120    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 121       return ILO_MAX_CONST_BUFFERS;
 122    case PIPE_SHADER_CAP_MAX_TEMPS:
 123       return 256;
 124    case PIPE_SHADER_CAP_MAX_ADDRS:
 125       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 126    case PIPE_SHADER_CAP_MAX_PREDS:
 127       return 0;
 128    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 129       return 1;
 130    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 131       return 0;
 132    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133       return 0;
 134    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 135       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 136    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 137       return 1;
 138    case PIPE_SHADER_CAP_SUBROUTINES:
 139       return 0;
 140    case PIPE_SHADER_CAP_INTEGERS:
 141       return 1;
 142    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 143       return ILO_MAX_SAMPLERS;
 144    case PIPE_SHADER_CAP_PREFERRED_IR:
 145       return PIPE_SHADER_IR_TGSI;
 146    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 147       return 1;
 148
 149    default:
 150       return 0;
 151    }
 152 }
 153
 154 static int
 155 ilo_get_video_param(struct pipe_screen *screen,
 156                     enum pipe_video_profile profile,
 157                     enum pipe_video_entrypoint entrypoint,
 158                     enum pipe_video_cap param)
 159 {
 160    switch (param) {
 161    case PIPE_VIDEO_CAP_SUPPORTED:
 162       return vl_profile_supported(screen, profile, entrypoint);
 163    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 164       return 1;
 165    case PIPE_VIDEO_CAP_MAX_WIDTH:
 166    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 167       return vl_video_buffer_max_size(screen);
 168    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 169       return PIPE_FORMAT_NV12;
 170    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 171       return 1;
 172    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 173       return 1;
 174    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 175       return 0;
 176    case PIPE_VIDEO_CAP_MAX_LEVEL:
 177       return vl_level_supported(screen, profile);
 178    default:
 179       return 0;
 180    }
 181 }
 182
 183 static int
 184 ilo_get_compute_param(struct pipe_screen *screen,
 185                       enum pipe_compute_cap param,
 186                       void *ret)
 187 {
 188    union {
 189       const char *ir_target;
 190       uint64_t grid_dimension;
 191       uint64_t max_grid_size[3];
 192       uint64_t max_block_size[3];
 193       uint64_t max_threads_per_block;
 194       uint64_t max_global_size;
 195       uint64_t max_local_size;
 196       uint64_t max_private_size;
 197       uint64_t max_input_size;
 198       uint64_t max_mem_alloc_size;
 199    } val;
 200    const void *ptr;
 201    int size;
 202
 203    /* XXX some randomly chosen values */
 204    switch (param) {
 205    case PIPE_COMPUTE_CAP_IR_TARGET:
 206       val.ir_target = "ilog";
 207
 208       ptr = val.ir_target;
 209       size = strlen(val.ir_target) + 1;
 210       break;
 211    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 212       val.grid_dimension = Elements(val.max_grid_size);
 213
 214       ptr = &val.grid_dimension;
 215       size = sizeof(val.grid_dimension);
 216       break;
 217    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 218       val.max_grid_size[0] = 65535;
 219       val.max_grid_size[1] = 65535;
 220       val.max_grid_size[2] = 1;
 221
 222       ptr = &val.max_grid_size;
 223       size = sizeof(val.max_grid_size);
 224       break;
 225    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 226       val.max_block_size[0] = 512;
 227       val.max_block_size[1] = 512;
 228       val.max_block_size[2] = 512;
 229
 230       ptr = &val.max_block_size;
 231       size = sizeof(val.max_block_size);
 232       break;
 233
 234    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 235       val.max_threads_per_block = 512;
 236
 237       ptr = &val.max_threads_per_block;
 238       size = sizeof(val.max_threads_per_block);
 239       break;
 240    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 241       val.max_global_size = 4;
 242
 243       ptr = &val.max_global_size;
 244       size = sizeof(val.max_global_size);
 245       break;
 246    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 247       val.max_local_size = 64 * 1024;
 248
 249       ptr = &val.max_local_size;
 250       size = sizeof(val.max_local_size);
 251       break;
 252    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 253       val.max_private_size = 32768;
 254
 255       ptr = &val.max_private_size;
 256       size = sizeof(val.max_private_size);
 257       break;
 258    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 259       val.max_input_size = 256;
 260
 261       ptr = &val.max_input_size;
 262       size = sizeof(val.max_input_size);
 263       break;
 264    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 265       val.max_mem_alloc_size = 128 * 1024 * 1024;
 266
 267       ptr = &val.max_mem_alloc_size;
 268       size = sizeof(val.max_mem_alloc_size);
 269       break;
 270    default:
 271       ptr = NULL;
 272       size = 0;
 273       break;
 274    }
 275
 276    if (ret)
 277       memcpy(ret, ptr, size);
 278
 279    return size;
 280 }
 281
 282 static int
 283 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 284 {
 285    struct ilo_screen *is = ilo_screen(screen);
 286
 287    switch (param) {
 288    case PIPE_CAP_NPOT_TEXTURES:
 289    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 290    case PIPE_CAP_TWO_SIDED_STENCIL:
 291       return true;
 292    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 293       return 0; /* TODO */
 294    case PIPE_CAP_ANISOTROPIC_FILTER:
 295    case PIPE_CAP_POINT_SPRITE:
 296       return true;
 297    case PIPE_CAP_MAX_RENDER_TARGETS:
 298       return ILO_MAX_DRAW_BUFFERS;
 299    case PIPE_CAP_OCCLUSION_QUERY:
 300    case PIPE_CAP_QUERY_TIME_ELAPSED:
 301    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 302    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 303       return true;
 304    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 305       /*
 306        * As defined in SURFACE_STATE, we have
 307        *
 308        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 309        *  GEN6           8192x8192x512            2048x2048x2048
 310        *  GEN7         16384x16384x2048           2048x2048x2048
 311        *
 312        * However, when the texutre size is large, things become unstable.  We
 313        * require the maximum texture size to be 2^30 bytes in
 314        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 315        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 316        * than 2^26 pixels.
 317        *
 318        * For 3D textures, we have to set the maximum number of levels to 9,
 319        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 320        * which has at most 2^26 pixels.  And for cube textures, we has to set
 321        * it to 12.
 322        */
 323       return 14;
 324    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 325       return 9;
 326    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 327       return 12;
 328    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 329       return false;
 330    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 331    case PIPE_CAP_SM3:
 332       return true;
 333    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 334       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 335          return 0;
 336       return ILO_MAX_SO_BUFFERS;
 337    case PIPE_CAP_PRIMITIVE_RESTART:
 338       return true;
 339    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 340       return ILO_MAX_SAMPLERS * 2;
 341    case PIPE_CAP_INDEP_BLEND_ENABLE:
 342    case PIPE_CAP_INDEP_BLEND_FUNC:
 343       return true;
 344    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 345       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 346    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 347    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 348    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 349    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 350    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 351       return true;
 352    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 353       return false;
 354    case PIPE_CAP_TGSI_INSTANCEID:
 355    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 356       return true;
 357    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 358       return false;
 359    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 360       return true;
 361    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 362    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 363    case PIPE_CAP_SCALED_RESOLVE:
 364       return true;
 365    case PIPE_CAP_MIN_TEXEL_OFFSET:
 366       return -8;
 367    case PIPE_CAP_MAX_TEXEL_OFFSET:
 368       return 7;
 369    case PIPE_CAP_CONDITIONAL_RENDER:
 370    case PIPE_CAP_TEXTURE_BARRIER:
 371       return true;
 372    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 373       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 374    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 375       return ILO_MAX_SO_BINDINGS;
 376    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 377       if (is->dev.gen >= ILO_GEN(7))
 378          return is->dev.has_gen7_sol_reset;
 379       else
 380          return false; /* TODO */
 381    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 382       return false;
 383    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 384       return true;
 385    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 386       return false;
 387    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 388       return 140;
 389    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 390    case PIPE_CAP_USER_VERTEX_BUFFERS:
 391       return false;
 392    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 393    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 394    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 395       return false;
 396    case PIPE_CAP_COMPUTE:
 397       return false; /* TODO */
 398    case PIPE_CAP_USER_INDEX_BUFFERS:
 399    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 400       return true;
 401    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 402       /* imposed by OWord (Dual) Block Read */
 403       return 16;
 404    case PIPE_CAP_START_INSTANCE:
 405    case PIPE_CAP_QUERY_TIMESTAMP:
 406       return true;
 407    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 408       return false; /* TODO */
 409    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 410       return 0;
 411    case PIPE_CAP_CUBE_MAP_ARRAY:
 412    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 413       return true;
 414    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 415       return 1;
 416    case PIPE_CAP_TGSI_TEXCOORD:
 417       return false;
 418    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 419       return true;
 420    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 421       return false; /* TODO */
 422    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 423       return 0;
 424    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 425       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
 426       return 1 << 27;
 427    case PIPE_CAP_MAX_VIEWPORTS:
 428       return ILO_MAX_VIEWPORTS;
 429    case PIPE_CAP_ENDIANNESS:
 430       return PIPE_ENDIAN_LITTLE;
 431
 432    default:
 433       return 0;
 434    }
 435 }
 436
 437 static const char *
 438 ilo_get_vendor(struct pipe_screen *screen)
 439 {
 440    return "LunarG, Inc.";
 441 }
 442
 443 static const char *
 444 ilo_get_name(struct pipe_screen *screen)
 445 {
 446    struct ilo_screen *is = ilo_screen(screen);
 447    const char *chipset;
 448
 449    /* stolen from classic i965 */
 450    switch (is->dev.devid) {
 451    case PCI_CHIP_SANDYBRIDGE_GT1:
 452    case PCI_CHIP_SANDYBRIDGE_GT2:
 453    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 454       chipset = "Intel(R) Sandybridge Desktop";
 455       break;
 456    case PCI_CHIP_SANDYBRIDGE_M_GT1:
 457    case PCI_CHIP_SANDYBRIDGE_M_GT2:
 458    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 459       chipset = "Intel(R) Sandybridge Mobile";
 460       break;
 461    case PCI_CHIP_SANDYBRIDGE_S:
 462       chipset = "Intel(R) Sandybridge Server";
 463       break;
 464    case PCI_CHIP_IVYBRIDGE_GT1:
 465    case PCI_CHIP_IVYBRIDGE_GT2:
 466       chipset = "Intel(R) Ivybridge Desktop";
 467       break;
 468    case PCI_CHIP_IVYBRIDGE_M_GT1:
 469    case PCI_CHIP_IVYBRIDGE_M_GT2:
 470       chipset = "Intel(R) Ivybridge Mobile";
 471       break;
 472    case PCI_CHIP_IVYBRIDGE_S_GT1:
 473    case PCI_CHIP_IVYBRIDGE_S_GT2:
 474       chipset = "Intel(R) Ivybridge Server";
 475       break;
 476    case PCI_CHIP_BAYTRAIL_M_1:
 477    case PCI_CHIP_BAYTRAIL_M_2:
 478    case PCI_CHIP_BAYTRAIL_M_3:
 479    case PCI_CHIP_BAYTRAIL_M_4:
 480    case PCI_CHIP_BAYTRAIL_D:
 481       chipset = "Intel(R) Bay Trail";
 482       break;
 483    case PCI_CHIP_HASWELL_GT1:
 484    case PCI_CHIP_HASWELL_GT2:
 485    case PCI_CHIP_HASWELL_GT3:
 486    case PCI_CHIP_HASWELL_SDV_GT1:
 487    case PCI_CHIP_HASWELL_SDV_GT2:
 488    case PCI_CHIP_HASWELL_SDV_GT3:
 489    case PCI_CHIP_HASWELL_ULT_GT1:
 490    case PCI_CHIP_HASWELL_ULT_GT2:
 491    case PCI_CHIP_HASWELL_ULT_GT3:
 492    case PCI_CHIP_HASWELL_CRW_GT1:
 493    case PCI_CHIP_HASWELL_CRW_GT2:
 494    case PCI_CHIP_HASWELL_CRW_GT3:
 495       chipset = "Intel(R) Haswell Desktop";
 496       break;
 497    case PCI_CHIP_HASWELL_M_GT1:
 498    case PCI_CHIP_HASWELL_M_GT2:
 499    case PCI_CHIP_HASWELL_M_GT3:
 500    case PCI_CHIP_HASWELL_SDV_M_GT1:
 501    case PCI_CHIP_HASWELL_SDV_M_GT2:
 502    case PCI_CHIP_HASWELL_SDV_M_GT3:
 503    case PCI_CHIP_HASWELL_ULT_M_GT1:
 504    case PCI_CHIP_HASWELL_ULT_M_GT2:
 505    case PCI_CHIP_HASWELL_ULT_M_GT3:
 506    case PCI_CHIP_HASWELL_CRW_M_GT1:
 507    case PCI_CHIP_HASWELL_CRW_M_GT2:
 508    case PCI_CHIP_HASWELL_CRW_M_GT3:
 509       chipset = "Intel(R) Haswell Mobile";
 510       break;
 511    case PCI_CHIP_HASWELL_S_GT1:
 512    case PCI_CHIP_HASWELL_S_GT2:
 513    case PCI_CHIP_HASWELL_S_GT3:
 514    case PCI_CHIP_HASWELL_SDV_S_GT1:
 515    case PCI_CHIP_HASWELL_SDV_S_GT2:
 516    case PCI_CHIP_HASWELL_SDV_S_GT3:
 517    case PCI_CHIP_HASWELL_ULT_S_GT1:
 518    case PCI_CHIP_HASWELL_ULT_S_GT2:
 519    case PCI_CHIP_HASWELL_ULT_S_GT3:
 520    case PCI_CHIP_HASWELL_CRW_S_GT1:
 521    case PCI_CHIP_HASWELL_CRW_S_GT2:
 522    case PCI_CHIP_HASWELL_CRW_S_GT3:
 523       chipset = "Intel(R) Haswell Server";
 524       break;
 525    default:
 526       chipset = "Unknown Intel Chipset";
 527       break;
 528    }
 529
 530    return chipset;
 531 }
 532
 533 static uint64_t
 534 ilo_get_timestamp(struct pipe_screen *screen)
 535 {
 536    struct ilo_screen *is = ilo_screen(screen);
 537    union {
 538       uint64_t val;
 539       uint32_t dw[2];
 540    } timestamp;
 541
 542    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 543
 544    /*
 545     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 546     *
 547     *     "Note: This timestamp register reflects the value of the PCU TSC.
 548     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 549     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 550     *      hours)."
 551     *
 552     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 553     * of the timestamp.  We will have to live with a timestamp that rolls over
 554     * every ~343 seconds.
 555     *
 556     * See also brw_get_timestamp().
 557     */
 558    return (uint64_t) timestamp.dw[1] * 80;
 559 }
 560
 561 static void
 562 ilo_fence_reference(struct pipe_screen *screen,
 563                     struct pipe_fence_handle **p,
 564                     struct pipe_fence_handle *f)
 565 {
 566    struct ilo_fence **ptr = (struct ilo_fence **) p;
 567    struct ilo_fence *fence = ilo_fence(f);
 568
 569    if (!ptr) {
 570       /* still need to reference fence */
 571       if (fence)
 572          pipe_reference(NULL, &fence->reference);
 573       return;
 574    }
 575
 576    /* reference fence and dereference the one pointed to by ptr */
 577    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
 578       struct ilo_fence *old = *ptr;
 579
 580       if (old->bo)
 581          intel_bo_unreference(old->bo);
 582       FREE(old);
 583    }
 584
 585    *ptr = fence;
 586 }
 587
 588 static boolean
 589 ilo_fence_signalled(struct pipe_screen *screen,
 590                     struct pipe_fence_handle *f)
 591 {
 592    struct ilo_fence *fence = ilo_fence(f);
 593
 594    /* mark signalled if the bo is idle */
 595    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 596       intel_bo_unreference(fence->bo);
 597       fence->bo = NULL;
 598    }
 599
 600    return (fence->bo == NULL);
 601 }
 602
 603 static boolean
 604 ilo_fence_finish(struct pipe_screen *screen,
 605                  struct pipe_fence_handle *f,
 606                  uint64_t timeout)
 607 {
 608    struct ilo_fence *fence = ilo_fence(f);
 609    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 610
 611    /* already signalled */
 612    if (!fence->bo)
 613       return true;
 614
 615    /* wait and see if it returns error */
 616    if (intel_bo_wait(fence->bo, wait_timeout))
 617       return false;
 618
 619    /* mark signalled */
 620    intel_bo_unreference(fence->bo);
 621    fence->bo = NULL;
 622
 623    return true;
 624 }
 625
 626 static void
 627 ilo_screen_destroy(struct pipe_screen *screen)
 628 {
 629    struct ilo_screen *is = ilo_screen(screen);
 630
 631    /* as it seems, winsys is owned by the screen */
 632    intel_winsys_destroy(is->winsys);
 633
 634    FREE(is);
 635 }
 636
 637 static bool
 638 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 639 {
 640    dev->devid = info->devid;
 641    dev->has_llc = info->has_llc;
 642    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 643    dev->has_address_swizzling = info->has_address_swizzling;
 644
 645    /*
 646     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 647     *
 648     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 649     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 650     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 651     *      to an EU GRF register. Read/write access to the URB is generally
 652     *      supported on a row-granular basis."
 653     *
 654     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 655     *
 656     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 657     *      128k        4096        2048
 658     *      256k        8096        4096"
 659     */
 660
 661    if (IS_HASWELL(info->devid)) {
 662       dev->gen = ILO_GEN(7.5);
 663
 664       if (IS_HSW_GT3(info->devid)) {
 665          dev->gt = 3;
 666          dev->urb_size = 512 * 1024;
 667       }
 668       else if (IS_HSW_GT2(info->devid)) {
 669          dev->gt = 2;
 670          dev->urb_size = 256 * 1024;
 671       }
 672       else {
 673          dev->gt = 1;
 674          dev->urb_size = 128 * 1024;
 675       }
 676    }
 677    else if (IS_GEN7(info->devid)) {
 678       dev->gen = ILO_GEN(7);
 679
 680       if (IS_IVB_GT2(info->devid)) {
 681          dev->gt = 2;
 682          dev->urb_size = 256 * 1024;
 683       }
 684       else {
 685          dev->gt = 1;
 686          dev->urb_size = 128 * 1024;
 687       }
 688    }
 689    else if (IS_GEN6(info->devid)) {
 690       dev->gen = ILO_GEN(6);
 691
 692       if (IS_SNB_GT2(info->devid)) {
 693          dev->gt = 2;
 694          dev->urb_size = 64 * 1024;
 695       }
 696       else {
 697          dev->gt = 1;
 698          dev->urb_size = 32 * 1024;
 699       }
 700    }
 701    else {
 702       ilo_err("unknown GPU generation\n");
 703       return false;
 704    }
 705
 706    return true;
 707 }
 708
 709 struct pipe_screen *
 710 ilo_screen_create(struct intel_winsys *ws)
 711 {
 712    struct ilo_screen *is;
 713    const struct intel_winsys_info *info;
 714
 715    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 716
 717    is = CALLOC_STRUCT(ilo_screen);
 718    if (!is)
 719       return NULL;
 720
 721    is->winsys = ws;
 722
 723    intel_winsys_enable_reuse(is->winsys);
 724
 725    info = intel_winsys_get_info(is->winsys);
 726    if (!init_dev(&is->dev, info)) {
 727       FREE(is);
 728       return NULL;
 729    }
 730
 731    util_format_s3tc_init();
 732
 733    is->base.destroy = ilo_screen_destroy;
 734    is->base.get_name = ilo_get_name;
 735    is->base.get_vendor = ilo_get_vendor;
 736    is->base.get_param = ilo_get_param;
 737    is->base.get_paramf = ilo_get_paramf;
 738    is->base.get_shader_param = ilo_get_shader_param;
 739    is->base.get_video_param = ilo_get_video_param;
 740    is->base.get_compute_param = ilo_get_compute_param;
 741
 742    is->base.get_timestamp = ilo_get_timestamp;
 743
 744    is->base.flush_frontbuffer = NULL;
 745
 746    is->base.fence_reference = ilo_fence_reference;
 747    is->base.fence_signalled = ilo_fence_signalled;
 748    is->base.fence_finish = ilo_fence_finish;
 749
 750    is->base.get_driver_query_info = NULL;
 751
 752    ilo_init_format_functions(is);
 753    ilo_init_context_functions(is);
 754    ilo_init_resource_functions(is);
 755
 756    return &is->base;
 757 }