src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "core/intel_winsys.h"
  35
  36 #include "ilo_context.h"
  37 #include "ilo_format.h"
  38 #include "ilo_resource.h"
  39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  40 #include "ilo_public.h"
  41 #include "ilo_screen.h"
  42
  43 struct pipe_fence_handle {
  44    struct pipe_reference reference;
  45    struct intel_bo *seqno_bo;
  46 };
  47
  48 static float
  49 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  50 {
  51    switch (param) {
  52    case PIPE_CAPF_MAX_LINE_WIDTH:
  53       /* in U3.7, defined in 3DSTATE_SF */
  54       return 7.0f;
  55    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  56       /* line width minus one, which is reserved for AA region */
  57       return 6.0f;
  58    case PIPE_CAPF_MAX_POINT_WIDTH:
  59       /* in U8.3, defined in 3DSTATE_SF */
  60       return 255.0f;
  61    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  62       /* same as point width, as we ignore rasterizer->point_smooth */
  63       return 255.0f;
  64    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  65       /* [2.0, 16.0], defined in SAMPLER_STATE */
  66       return 16.0f;
  67    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  68       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  69       return 15.0f;
  70    case PIPE_CAPF_GUARD_BAND_LEFT:
  71    case PIPE_CAPF_GUARD_BAND_TOP:
  72    case PIPE_CAPF_GUARD_BAND_RIGHT:
  73    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  74       /* what are these for? */
  75       return 0.0f;
  76
  77    default:
  78       return 0.0f;
  79    }
  80 }
  81
  82 static int
  83 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  84                      enum pipe_shader_cap param)
  85 {
  86    switch (shader) {
  87    case PIPE_SHADER_FRAGMENT:
  88    case PIPE_SHADER_VERTEX:
  89    case PIPE_SHADER_GEOMETRY:
  90       break;
  91    default:
  92       return 0;
  93    }
  94
  95    switch (param) {
  96    /* the limits are copied from the classic driver */
  97    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  98       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
  99    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 100       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 101    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 102       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 103    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 104       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 105    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 106       return UINT_MAX;
 107    case PIPE_SHADER_CAP_MAX_INPUTS:
 108    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 109       /* this is limited by how many attributes SF can remap */
 110       return 16;
 111    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 112       return 1024 * sizeof(float[4]);
 113    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 114       return ILO_MAX_CONST_BUFFERS;
 115    case PIPE_SHADER_CAP_MAX_TEMPS:
 116       return 256;
 117    case PIPE_SHADER_CAP_MAX_PREDS:
 118       return 0;
 119    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 120       return 1;
 121    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 122       return 0;
 123    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 124       return 0;
 125    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 126       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 127    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 128       return 1;
 129    case PIPE_SHADER_CAP_SUBROUTINES:
 130       return 0;
 131    case PIPE_SHADER_CAP_INTEGERS:
 132       return 1;
 133    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 134       return ILO_MAX_SAMPLERS;
 135    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 136       return ILO_MAX_SAMPLER_VIEWS;
 137    case PIPE_SHADER_CAP_PREFERRED_IR:
 138       return PIPE_SHADER_IR_TGSI;
 139    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 140       return 1;
 141    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 142       return 32;
 143
 144    default:
 145       return 0;
 146    }
 147 }
 148
 149 static int
 150 ilo_get_video_param(struct pipe_screen *screen,
 151                     enum pipe_video_profile profile,
 152                     enum pipe_video_entrypoint entrypoint,
 153                     enum pipe_video_cap param)
 154 {
 155    switch (param) {
 156    case PIPE_VIDEO_CAP_SUPPORTED:
 157       return vl_profile_supported(screen, profile, entrypoint);
 158    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 159       return 1;
 160    case PIPE_VIDEO_CAP_MAX_WIDTH:
 161    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 162       return vl_video_buffer_max_size(screen);
 163    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 164       return PIPE_FORMAT_NV12;
 165    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 166       return 1;
 167    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 168       return 1;
 169    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 170       return 0;
 171    case PIPE_VIDEO_CAP_MAX_LEVEL:
 172       return vl_level_supported(screen, profile);
 173    default:
 174       return 0;
 175    }
 176 }
 177
 178 static int
 179 ilo_get_compute_param(struct pipe_screen *screen,
 180                       enum pipe_compute_cap param,
 181                       void *ret)
 182 {
 183    struct ilo_screen *is = ilo_screen(screen);
 184    union {
 185       const char *ir_target;
 186       uint64_t grid_dimension;
 187       uint64_t max_grid_size[3];
 188       uint64_t max_block_size[3];
 189       uint64_t max_threads_per_block;
 190       uint64_t max_global_size;
 191       uint64_t max_local_size;
 192       uint64_t max_private_size;
 193       uint64_t max_input_size;
 194       uint64_t max_mem_alloc_size;
 195       uint32_t max_clock_frequency;
 196       uint32_t max_compute_units;
 197       uint32_t images_supported;
 198       uint32_t subgroup_size;
 199    } val;
 200    const void *ptr;
 201    int size;
 202
 203    switch (param) {
 204    case PIPE_COMPUTE_CAP_IR_TARGET:
 205       val.ir_target = "ilog";
 206
 207       ptr = val.ir_target;
 208       size = strlen(val.ir_target) + 1;
 209       break;
 210    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 211       val.grid_dimension = Elements(val.max_grid_size);
 212
 213       ptr = &val.grid_dimension;
 214       size = sizeof(val.grid_dimension);
 215       break;
 216    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 217       val.max_grid_size[0] = 0xffffffffu;
 218       val.max_grid_size[1] = 0xffffffffu;
 219       val.max_grid_size[2] = 0xffffffffu;
 220
 221       ptr = &val.max_grid_size;
 222       size = sizeof(val.max_grid_size);
 223       break;
 224    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 225       val.max_block_size[0] = 1024;
 226       val.max_block_size[1] = 1024;
 227       val.max_block_size[2] = 1024;
 228
 229       ptr = &val.max_block_size;
 230       size = sizeof(val.max_block_size);
 231       break;
 232
 233    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 234       val.max_threads_per_block = 1024;
 235
 236       ptr = &val.max_threads_per_block;
 237       size = sizeof(val.max_threads_per_block);
 238       break;
 239    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 240       /* \see ilo_max_resource_size */
 241       val.max_global_size = 1u << 31;
 242
 243       ptr = &val.max_global_size;
 244       size = sizeof(val.max_global_size);
 245       break;
 246    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 247       /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
 248       val.max_local_size = 64 * 1024;
 249
 250       ptr = &val.max_local_size;
 251       size = sizeof(val.max_local_size);
 252       break;
 253    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 254       /* scratch size */
 255       val.max_private_size = 12 * 1024;
 256
 257       ptr = &val.max_private_size;
 258       size = sizeof(val.max_private_size);
 259       break;
 260    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 261       val.max_input_size = 1024;
 262
 263       ptr = &val.max_input_size;
 264       size = sizeof(val.max_input_size);
 265       break;
 266    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 267       val.max_mem_alloc_size = 1u << 31;
 268
 269       ptr = &val.max_mem_alloc_size;
 270       size = sizeof(val.max_mem_alloc_size);
 271       break;
 272    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 273       val.max_clock_frequency = 1000;
 274
 275       ptr = &val.max_clock_frequency;
 276       size = sizeof(val.max_clock_frequency);
 277       break;
 278    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 279       val.max_compute_units = is->dev.eu_count;
 280
 281       ptr = &val.max_compute_units;
 282       size = sizeof(val.max_compute_units);
 283       break;
 284    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 285       val.images_supported = 1;
 286
 287       ptr = &val.images_supported;
 288       size = sizeof(val.images_supported);
 289       break;
 290    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 291       /* best case is actually SIMD32 */
 292       val.subgroup_size = 16;
 293
 294       ptr = &val.subgroup_size;
 295       size = sizeof(val.subgroup_size);
 296       break;
 297    default:
 298       ptr = NULL;
 299       size = 0;
 300       break;
 301    }
 302
 303    if (ret)
 304       memcpy(ret, ptr, size);
 305
 306    return size;
 307 }
 308
 309 static int
 310 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 311 {
 312    struct ilo_screen *is = ilo_screen(screen);
 313
 314    switch (param) {
 315    case PIPE_CAP_NPOT_TEXTURES:
 316    case PIPE_CAP_TWO_SIDED_STENCIL:
 317       return true;
 318    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 319       return 0; /* TODO */
 320    case PIPE_CAP_ANISOTROPIC_FILTER:
 321    case PIPE_CAP_POINT_SPRITE:
 322       return true;
 323    case PIPE_CAP_MAX_RENDER_TARGETS:
 324       return ILO_MAX_DRAW_BUFFERS;
 325    case PIPE_CAP_OCCLUSION_QUERY:
 326    case PIPE_CAP_QUERY_TIME_ELAPSED:
 327    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 328    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 329       return true;
 330    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 331       /*
 332        * As defined in SURFACE_STATE, we have
 333        *
 334        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 335        *  GEN6           8192x8192x512            2048x2048x2048
 336        *  GEN7         16384x16384x2048           2048x2048x2048
 337        */
 338       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 339    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 340       return 12;
 341    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 342       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 343    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 344       return false;
 345    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 346    case PIPE_CAP_SM3:
 347       return true;
 348    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 349       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 350          return 0;
 351       return ILO_MAX_SO_BUFFERS;
 352    case PIPE_CAP_PRIMITIVE_RESTART:
 353       return true;
 354    case PIPE_CAP_INDEP_BLEND_ENABLE:
 355    case PIPE_CAP_INDEP_BLEND_FUNC:
 356       return true;
 357    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 358       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7.5)) ? 2048 : 512;
 359    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 360    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 361    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 362    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 363    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 364       return true;
 365    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 366       return false;
 367    case PIPE_CAP_TGSI_INSTANCEID:
 368    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 369       return true;
 370    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 371       return false;
 372    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 373       return true;
 374    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 375    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 376       return true;
 377    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 378    case PIPE_CAP_MIN_TEXEL_OFFSET:
 379       return -8;
 380    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 381    case PIPE_CAP_MAX_TEXEL_OFFSET:
 382       return 7;
 383    case PIPE_CAP_CONDITIONAL_RENDER:
 384    case PIPE_CAP_TEXTURE_BARRIER:
 385       return true;
 386    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 387       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 388    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 389       return ILO_MAX_SO_BINDINGS;
 390    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 391       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 392          return is->dev.has_gen7_sol_reset;
 393       else
 394          return false; /* TODO */
 395    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 396       return false;
 397    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 398       return true;
 399    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 400       return false;
 401    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 402       return 140;
 403    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 404    case PIPE_CAP_USER_VERTEX_BUFFERS:
 405       return false;
 406    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 407    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 408    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 409       return false;
 410    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 411       return 2048;
 412    case PIPE_CAP_COMPUTE:
 413       return false; /* TODO */
 414    case PIPE_CAP_USER_INDEX_BUFFERS:
 415    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 416       return true;
 417    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 418       /* imposed by OWord (Dual) Block Read */
 419       return 16;
 420    case PIPE_CAP_START_INSTANCE:
 421       return true;
 422    case PIPE_CAP_QUERY_TIMESTAMP:
 423       return is->dev.has_timestamp;
 424    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 425       return false; /* TODO */
 426    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 427       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 428    case PIPE_CAP_CUBE_MAP_ARRAY:
 429    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 430       return true;
 431    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 432       return 1;
 433    case PIPE_CAP_TGSI_TEXCOORD:
 434       return false;
 435    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 436    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 437       return true;
 438    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 439       return 0;
 440    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 441       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 442       return 1 << 27;
 443    case PIPE_CAP_MAX_VIEWPORTS:
 444       return ILO_MAX_VIEWPORTS;
 445    case PIPE_CAP_ENDIANNESS:
 446       return PIPE_ENDIAN_LITTLE;
 447    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 448       return true;
 449    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 450    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 451    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 452    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 453    case PIPE_CAP_TEXTURE_GATHER_SM5:
 454       return 0;
 455    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 456    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 457    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 458       return true;
 459    case PIPE_CAP_FAKE_SW_MSAA:
 460    case PIPE_CAP_TEXTURE_QUERY_LOD:
 461    case PIPE_CAP_SAMPLE_SHADING:
 462    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 463    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 464    case PIPE_CAP_MAX_VERTEX_STREAMS:
 465    case PIPE_CAP_DRAW_INDIRECT:
 466    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 467    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 468    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 469    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 470    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 471    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 472    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 473    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 474    case PIPE_CAP_TGSI_TXQS:
 475    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 476    case PIPE_CAP_SHAREABLE_SHADERS:
 477    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 478    case PIPE_CAP_CLEAR_TEXTURE:
 479       return 0;
 480
 481    case PIPE_CAP_VENDOR_ID:
 482       return 0x8086;
 483    case PIPE_CAP_DEVICE_ID:
 484       return is->dev.devid;
 485    case PIPE_CAP_ACCELERATED:
 486       return true;
 487    case PIPE_CAP_VIDEO_MEMORY: {
 488       /* Once a batch uses more than 75% of the maximum mappable size, we
 489        * assume that there's some fragmentation, and we start doing extra
 490        * flushing, etc.  That's the big cliff apps will care about.
 491        */
 492       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 493       uint64_t system_memory;
 494
 495       if (!os_get_total_physical_memory(&system_memory))
 496          return 0;
 497
 498       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 499    }
 500    case PIPE_CAP_UMA:
 501       return true;
 502    case PIPE_CAP_CLIP_HALFZ:
 503       return true;
 504    case PIPE_CAP_VERTEXID_NOBASE:
 505       return false;
 506    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 507       return true;
 508
 509    default:
 510       return 0;
 511    }
 512 }
 513
 514 static const char *
 515 ilo_get_vendor(struct pipe_screen *screen)
 516 {
 517    return "LunarG, Inc.";
 518 }
 519
 520 static const char *
 521 ilo_get_device_vendor(struct pipe_screen *screen)
 522 {
 523    return "Intel";
 524 }
 525
 526 static const char *
 527 ilo_get_name(struct pipe_screen *screen)
 528 {
 529    struct ilo_screen *is = ilo_screen(screen);
 530    const char *chipset = NULL;
 531
 532    if (gen_is_chv(is->dev.devid)) {
 533       chipset = "Intel(R) Cherryview";
 534    } else if (gen_is_bdw(is->dev.devid)) {
 535       /* this is likely wrong */
 536       if (gen_is_desktop(is->dev.devid))
 537          chipset = "Intel(R) Broadwell Desktop";
 538       else if (gen_is_mobile(is->dev.devid))
 539          chipset = "Intel(R) Broadwell Mobile";
 540       else if (gen_is_server(is->dev.devid))
 541          chipset = "Intel(R) Broadwell Server";
 542    } else if (gen_is_vlv(is->dev.devid)) {
 543       chipset = "Intel(R) Bay Trail";
 544    } else if (gen_is_hsw(is->dev.devid)) {
 545       if (gen_is_desktop(is->dev.devid))
 546          chipset = "Intel(R) Haswell Desktop";
 547       else if (gen_is_mobile(is->dev.devid))
 548          chipset = "Intel(R) Haswell Mobile";
 549       else if (gen_is_server(is->dev.devid))
 550          chipset = "Intel(R) Haswell Server";
 551    } else if (gen_is_ivb(is->dev.devid)) {
 552       if (gen_is_desktop(is->dev.devid))
 553          chipset = "Intel(R) Ivybridge Desktop";
 554       else if (gen_is_mobile(is->dev.devid))
 555          chipset = "Intel(R) Ivybridge Mobile";
 556       else if (gen_is_server(is->dev.devid))
 557          chipset = "Intel(R) Ivybridge Server";
 558    } else if (gen_is_snb(is->dev.devid)) {
 559       if (gen_is_desktop(is->dev.devid))
 560          chipset = "Intel(R) Sandybridge Desktop";
 561       else if (gen_is_mobile(is->dev.devid))
 562          chipset = "Intel(R) Sandybridge Mobile";
 563       else if (gen_is_server(is->dev.devid))
 564          chipset = "Intel(R) Sandybridge Server";
 565    }
 566
 567    if (!chipset)
 568       chipset = "Unknown Intel Chipset";
 569
 570    return chipset;
 571 }
 572
 573 static uint64_t
 574 ilo_get_timestamp(struct pipe_screen *screen)
 575 {
 576    struct ilo_screen *is = ilo_screen(screen);
 577    union {
 578       uint64_t val;
 579       uint32_t dw[2];
 580    } timestamp;
 581
 582    intel_winsys_read_reg(is->dev.winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 583
 584    /*
 585     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 586     *
 587     *     "Note: This timestamp register reflects the value of the PCU TSC.
 588     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 589     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 590     *      hours)."
 591     *
 592     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 593     * of the timestamp.  We will have to live with a timestamp that rolls over
 594     * every ~343 seconds.
 595     *
 596     * See also brw_get_timestamp().
 597     */
 598    return (uint64_t) timestamp.dw[1] * 80;
 599 }
 600
 601 static boolean
 602 ilo_is_format_supported(struct pipe_screen *screen,
 603                         enum pipe_format format,
 604                         enum pipe_texture_target target,
 605                         unsigned sample_count,
 606                         unsigned bindings)
 607 {
 608    struct ilo_screen *is = ilo_screen(screen);
 609    const struct ilo_dev *dev = &is->dev;
 610
 611    if (!util_format_is_supported(format, bindings))
 612       return false;
 613
 614    /* no MSAA support yet */
 615    if (sample_count > 1)
 616       return false;
 617
 618    if ((bindings & PIPE_BIND_DEPTH_STENCIL) &&
 619        !ilo_format_support_zs(dev, format))
 620       return false;
 621
 622    if ((bindings & PIPE_BIND_RENDER_TARGET) &&
 623        !ilo_format_support_rt(dev, format))
 624       return false;
 625
 626    if ((bindings & PIPE_BIND_SAMPLER_VIEW) &&
 627        !ilo_format_support_sampler(dev, format))
 628       return false;
 629
 630    if ((bindings & PIPE_BIND_VERTEX_BUFFER) &&
 631        !ilo_format_support_vb(dev, format))
 632       return false;
 633
 634    return true;
 635 }
 636
 637 static boolean
 638 ilo_is_video_format_supported(struct pipe_screen *screen,
 639                               enum pipe_format format,
 640                               enum pipe_video_profile profile,
 641                               enum pipe_video_entrypoint entrypoint)
 642 {
 643    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 644 }
 645
 646 static void
 647 ilo_screen_fence_reference(struct pipe_screen *screen,
 648                            struct pipe_fence_handle **ptr,
 649                            struct pipe_fence_handle *fence)
 650 {
 651    struct pipe_fence_handle *old;
 652
 653    if (likely(ptr)) {
 654       old = *ptr;
 655       *ptr = fence;
 656    } else {
 657       old = NULL;
 658    }
 659
 660    STATIC_ASSERT(&((struct pipe_fence_handle *) NULL)->reference == NULL);
 661    if (pipe_reference(&old->reference, &fence->reference)) {
 662       intel_bo_unref(old->seqno_bo);
 663       FREE(old);
 664    }
 665 }
 666
 667 static boolean
 668 ilo_screen_fence_finish(struct pipe_screen *screen,
 669                         struct pipe_fence_handle *fence,
 670                         uint64_t timeout)
 671 {
 672    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 673    bool signaled;
 674
 675    signaled = (!fence->seqno_bo ||
 676          intel_bo_wait(fence->seqno_bo, wait_timeout) == 0);
 677
 678    /* XXX not thread safe */
 679    if (signaled && fence->seqno_bo) {
 680       intel_bo_unref(fence->seqno_bo);
 681       fence->seqno_bo = NULL;
 682    }
 683
 684    return signaled;
 685 }
 686
 687 /**
 688  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 689  * before waited on or checked.
 690  */
 691 struct pipe_fence_handle *
 692 ilo_screen_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 693 {
 694    struct pipe_fence_handle *fence;
 695
 696    fence = CALLOC_STRUCT(pipe_fence_handle);
 697    if (!fence)
 698       return NULL;
 699
 700    pipe_reference_init(&fence->reference, 1);
 701
 702    fence->seqno_bo = intel_bo_ref(bo);
 703
 704    return fence;
 705 }
 706
 707 static void
 708 ilo_screen_destroy(struct pipe_screen *screen)
 709 {
 710    struct ilo_screen *is = ilo_screen(screen);
 711
 712    intel_winsys_destroy(is->dev.winsys);
 713
 714    FREE(is);
 715 }
 716
 717 struct pipe_screen *
 718 ilo_screen_create(struct intel_winsys *ws)
 719 {
 720    struct ilo_screen *is;
 721
 722    ilo_debug_init("ILO_DEBUG");
 723
 724    is = CALLOC_STRUCT(ilo_screen);
 725    if (!is)
 726       return NULL;
 727
 728    if (!ilo_dev_init(&is->dev, ws)) {
 729       FREE(is);
 730       return NULL;
 731    }
 732
 733    util_format_s3tc_init();
 734
 735    is->base.destroy = ilo_screen_destroy;
 736    is->base.get_name = ilo_get_name;
 737    is->base.get_vendor = ilo_get_vendor;
 738    is->base.get_device_vendor = ilo_get_device_vendor;
 739    is->base.get_param = ilo_get_param;
 740    is->base.get_paramf = ilo_get_paramf;
 741    is->base.get_shader_param = ilo_get_shader_param;
 742    is->base.get_video_param = ilo_get_video_param;
 743    is->base.get_compute_param = ilo_get_compute_param;
 744
 745    is->base.get_timestamp = ilo_get_timestamp;
 746
 747    is->base.is_format_supported = ilo_is_format_supported;
 748    is->base.is_video_format_supported = ilo_is_video_format_supported;
 749
 750    is->base.flush_frontbuffer = NULL;
 751
 752    is->base.fence_reference = ilo_screen_fence_reference;
 753    is->base.fence_finish = ilo_screen_fence_finish;
 754
 755    is->base.get_driver_query_info = NULL;
 756
 757    ilo_init_context_functions(is);
 758    ilo_init_resource_functions(is);
 759
 760    return &is->base;
 761 }