2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_format_s3tc.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31 #include "intel_chipset.h"
32 #include "intel_reg.h" /* for TIMESTAMP */
33 #include "intel_winsys.h"
35 #include "ilo_context.h"
36 #include "ilo_format.h"
37 #include "ilo_resource.h"
38 #include "ilo_public.h"
39 #include "ilo_screen.h"
43 static const struct debug_named_value ilo_debug_flags
[] = {
44 { "3d", ILO_DEBUG_3D
, "Dump 3D commands and states" },
45 { "vs", ILO_DEBUG_VS
, "Dump vertex shaders" },
46 { "gs", ILO_DEBUG_GS
, "Dump geometry shaders" },
47 { "fs", ILO_DEBUG_FS
, "Dump fragment shaders" },
48 { "cs", ILO_DEBUG_CS
, "Dump compute shaders" },
49 { "draw", ILO_DEBUG_DRAW
, "Show draw information" },
50 { "flush", ILO_DEBUG_FLUSH
, "Show batch buffer flushes" },
51 { "nohw", ILO_DEBUG_NOHW
, "Do not send commands to HW" },
52 { "nocache", ILO_DEBUG_NOCACHE
, "Always invalidate HW caches" },
53 { "nohiz", ILO_DEBUG_NOHIZ
, "Disable HiZ" },
58 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
61 case PIPE_CAPF_MAX_LINE_WIDTH
:
62 /* in U3.7, defined in 3DSTATE_SF */
64 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
65 /* line width minus one, which is reserved for AA region */
67 case PIPE_CAPF_MAX_POINT_WIDTH
:
68 /* in U8.3, defined in 3DSTATE_SF */
70 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
71 /* same as point width, as we ignore rasterizer->point_smooth */
73 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
74 /* [2.0, 16.0], defined in SAMPLER_STATE */
76 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
77 /* [-16.0, 16.0), defined in SAMPLER_STATE */
79 case PIPE_CAPF_GUARD_BAND_LEFT
:
80 case PIPE_CAPF_GUARD_BAND_TOP
:
81 case PIPE_CAPF_GUARD_BAND_RIGHT
:
82 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
83 /* what are these for? */
92 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
93 enum pipe_shader_cap param
)
96 case PIPE_SHADER_FRAGMENT
:
97 case PIPE_SHADER_VERTEX
:
98 case PIPE_SHADER_GEOMETRY
:
105 /* the limits are copied from the classic driver */
106 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
107 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
108 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
109 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
110 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
111 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
112 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
113 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
114 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
116 case PIPE_SHADER_CAP_MAX_INPUTS
:
117 /* this is limited by how many attributes SF can remap */
119 case PIPE_SHADER_CAP_MAX_CONSTS
:
121 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
122 return ILO_MAX_CONST_BUFFERS
;
123 case PIPE_SHADER_CAP_MAX_TEMPS
:
125 case PIPE_SHADER_CAP_MAX_ADDRS
:
126 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
127 case PIPE_SHADER_CAP_MAX_PREDS
:
129 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
131 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
133 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
135 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
136 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
137 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
139 case PIPE_SHADER_CAP_SUBROUTINES
:
141 case PIPE_SHADER_CAP_INTEGERS
:
143 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
144 return ILO_MAX_SAMPLERS
;
145 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
146 return ILO_MAX_SAMPLER_VIEWS
;
147 case PIPE_SHADER_CAP_PREFERRED_IR
:
148 return PIPE_SHADER_IR_TGSI
;
149 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
158 ilo_get_video_param(struct pipe_screen
*screen
,
159 enum pipe_video_profile profile
,
160 enum pipe_video_entrypoint entrypoint
,
161 enum pipe_video_cap param
)
164 case PIPE_VIDEO_CAP_SUPPORTED
:
165 return vl_profile_supported(screen
, profile
, entrypoint
);
166 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
168 case PIPE_VIDEO_CAP_MAX_WIDTH
:
169 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
170 return vl_video_buffer_max_size(screen
);
171 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
172 return PIPE_FORMAT_NV12
;
173 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
175 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
177 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
179 case PIPE_VIDEO_CAP_MAX_LEVEL
:
180 return vl_level_supported(screen
, profile
);
187 ilo_get_compute_param(struct pipe_screen
*screen
,
188 enum pipe_compute_cap param
,
192 const char *ir_target
;
193 uint64_t grid_dimension
;
194 uint64_t max_grid_size
[3];
195 uint64_t max_block_size
[3];
196 uint64_t max_threads_per_block
;
197 uint64_t max_global_size
;
198 uint64_t max_local_size
;
199 uint64_t max_private_size
;
200 uint64_t max_input_size
;
201 uint64_t max_mem_alloc_size
;
206 /* XXX some randomly chosen values */
208 case PIPE_COMPUTE_CAP_IR_TARGET
:
209 val
.ir_target
= "ilog";
212 size
= strlen(val
.ir_target
) + 1;
214 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
215 val
.grid_dimension
= Elements(val
.max_grid_size
);
217 ptr
= &val
.grid_dimension
;
218 size
= sizeof(val
.grid_dimension
);
220 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
221 val
.max_grid_size
[0] = 65535;
222 val
.max_grid_size
[1] = 65535;
223 val
.max_grid_size
[2] = 1;
225 ptr
= &val
.max_grid_size
;
226 size
= sizeof(val
.max_grid_size
);
228 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
229 val
.max_block_size
[0] = 512;
230 val
.max_block_size
[1] = 512;
231 val
.max_block_size
[2] = 512;
233 ptr
= &val
.max_block_size
;
234 size
= sizeof(val
.max_block_size
);
237 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
238 val
.max_threads_per_block
= 512;
240 ptr
= &val
.max_threads_per_block
;
241 size
= sizeof(val
.max_threads_per_block
);
243 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
244 val
.max_global_size
= 4;
246 ptr
= &val
.max_global_size
;
247 size
= sizeof(val
.max_global_size
);
249 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
250 val
.max_local_size
= 64 * 1024;
252 ptr
= &val
.max_local_size
;
253 size
= sizeof(val
.max_local_size
);
255 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
256 val
.max_private_size
= 32768;
258 ptr
= &val
.max_private_size
;
259 size
= sizeof(val
.max_private_size
);
261 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
262 val
.max_input_size
= 256;
264 ptr
= &val
.max_input_size
;
265 size
= sizeof(val
.max_input_size
);
267 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
268 val
.max_mem_alloc_size
= 128 * 1024 * 1024;
270 ptr
= &val
.max_mem_alloc_size
;
271 size
= sizeof(val
.max_mem_alloc_size
);
280 memcpy(ret
, ptr
, size
);
286 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
288 struct ilo_screen
*is
= ilo_screen(screen
);
291 case PIPE_CAP_NPOT_TEXTURES
:
292 case PIPE_CAP_TWO_SIDED_STENCIL
:
294 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
296 case PIPE_CAP_ANISOTROPIC_FILTER
:
297 case PIPE_CAP_POINT_SPRITE
:
299 case PIPE_CAP_MAX_RENDER_TARGETS
:
300 return ILO_MAX_DRAW_BUFFERS
;
301 case PIPE_CAP_OCCLUSION_QUERY
:
302 case PIPE_CAP_QUERY_TIME_ELAPSED
:
303 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
304 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
306 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
308 * As defined in SURFACE_STATE, we have
310 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
311 * GEN6 8192x8192x512 2048x2048x2048
312 * GEN7 16384x16384x2048 2048x2048x2048
314 * However, when the texutre size is large, things become unstable. We
315 * require the maximum texture size to be 2^30 bytes in
316 * screen->can_create_resource(). Since the maximum pixel size is 2^4
317 * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
320 * For 3D textures, we have to set the maximum number of levels to 9,
321 * which has at most 2^24 pixels. For 2D textures, we set it to 14,
322 * which has at most 2^26 pixels. And for cube textures, we has to set
326 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
328 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
330 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
332 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
335 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
336 if (is
->dev
.gen
>= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
338 return ILO_MAX_SO_BUFFERS
;
339 case PIPE_CAP_PRIMITIVE_RESTART
:
341 case PIPE_CAP_INDEP_BLEND_ENABLE
:
342 case PIPE_CAP_INDEP_BLEND_FUNC
:
344 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
345 return (is
->dev
.gen
>= ILO_GEN(7)) ? 2048 : 512;
346 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
347 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
348 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
349 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
350 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
352 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
354 case PIPE_CAP_TGSI_INSTANCEID
:
355 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
357 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
359 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
361 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
362 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
364 case PIPE_CAP_MIN_TEXEL_OFFSET
:
366 case PIPE_CAP_MAX_TEXEL_OFFSET
:
368 case PIPE_CAP_CONDITIONAL_RENDER
:
369 case PIPE_CAP_TEXTURE_BARRIER
:
371 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
372 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
373 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
374 return ILO_MAX_SO_BINDINGS
;
375 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
376 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
378 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
379 if (is
->dev
.gen
>= ILO_GEN(7))
380 return is
->dev
.has_gen7_sol_reset
;
382 return false; /* TODO */
383 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
385 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
387 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
389 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
391 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
392 case PIPE_CAP_USER_VERTEX_BUFFERS
:
394 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
395 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
396 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
398 case PIPE_CAP_COMPUTE
:
399 return false; /* TODO */
400 case PIPE_CAP_USER_INDEX_BUFFERS
:
401 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
403 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
404 /* imposed by OWord (Dual) Block Read */
406 case PIPE_CAP_START_INSTANCE
:
408 case PIPE_CAP_QUERY_TIMESTAMP
:
409 return is
->dev
.has_timestamp
;
410 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
411 return false; /* TODO */
412 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
414 case PIPE_CAP_CUBE_MAP_ARRAY
:
415 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
417 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
419 case PIPE_CAP_TGSI_TEXCOORD
:
421 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
423 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
424 return false; /* TODO */
425 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
427 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
428 /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
430 case PIPE_CAP_MAX_VIEWPORTS
:
431 return ILO_MAX_VIEWPORTS
;
432 case PIPE_CAP_ENDIANNESS
:
433 return PIPE_ENDIAN_LITTLE
;
434 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
436 case PIPE_CAP_TGSI_VS_LAYER
:
437 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
438 case PIPE_CAP_TEXTURE_GATHER_SM5
:
439 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
448 ilo_get_vendor(struct pipe_screen
*screen
)
450 return "LunarG, Inc.";
454 ilo_get_name(struct pipe_screen
*screen
)
456 struct ilo_screen
*is
= ilo_screen(screen
);
459 /* stolen from classic i965 */
460 switch (is
->dev
.devid
) {
461 case PCI_CHIP_SANDYBRIDGE_GT1
:
462 case PCI_CHIP_SANDYBRIDGE_GT2
:
463 case PCI_CHIP_SANDYBRIDGE_GT2_PLUS
:
464 chipset
= "Intel(R) Sandybridge Desktop";
466 case PCI_CHIP_SANDYBRIDGE_M_GT1
:
467 case PCI_CHIP_SANDYBRIDGE_M_GT2
:
468 case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS
:
469 chipset
= "Intel(R) Sandybridge Mobile";
471 case PCI_CHIP_SANDYBRIDGE_S
:
472 chipset
= "Intel(R) Sandybridge Server";
474 case PCI_CHIP_IVYBRIDGE_GT1
:
475 case PCI_CHIP_IVYBRIDGE_GT2
:
476 chipset
= "Intel(R) Ivybridge Desktop";
478 case PCI_CHIP_IVYBRIDGE_M_GT1
:
479 case PCI_CHIP_IVYBRIDGE_M_GT2
:
480 chipset
= "Intel(R) Ivybridge Mobile";
482 case PCI_CHIP_IVYBRIDGE_S_GT1
:
483 case PCI_CHIP_IVYBRIDGE_S_GT2
:
484 chipset
= "Intel(R) Ivybridge Server";
486 case PCI_CHIP_BAYTRAIL_M_1
:
487 case PCI_CHIP_BAYTRAIL_M_2
:
488 case PCI_CHIP_BAYTRAIL_M_3
:
489 case PCI_CHIP_BAYTRAIL_M_4
:
490 case PCI_CHIP_BAYTRAIL_D
:
491 chipset
= "Intel(R) Bay Trail";
493 case PCI_CHIP_HASWELL_GT1
:
494 case PCI_CHIP_HASWELL_GT2
:
495 case PCI_CHIP_HASWELL_GT3
:
496 case PCI_CHIP_HASWELL_SDV_GT1
:
497 case PCI_CHIP_HASWELL_SDV_GT2
:
498 case PCI_CHIP_HASWELL_SDV_GT3
:
499 case PCI_CHIP_HASWELL_ULT_GT1
:
500 case PCI_CHIP_HASWELL_ULT_GT2
:
501 case PCI_CHIP_HASWELL_ULT_GT3
:
502 case PCI_CHIP_HASWELL_CRW_GT1
:
503 case PCI_CHIP_HASWELL_CRW_GT2
:
504 case PCI_CHIP_HASWELL_CRW_GT3
:
505 chipset
= "Intel(R) Haswell Desktop";
507 case PCI_CHIP_HASWELL_M_GT1
:
508 case PCI_CHIP_HASWELL_M_GT2
:
509 case PCI_CHIP_HASWELL_M_GT3
:
510 case PCI_CHIP_HASWELL_SDV_M_GT1
:
511 case PCI_CHIP_HASWELL_SDV_M_GT2
:
512 case PCI_CHIP_HASWELL_SDV_M_GT3
:
513 case PCI_CHIP_HASWELL_ULT_M_GT1
:
514 case PCI_CHIP_HASWELL_ULT_M_GT2
:
515 case PCI_CHIP_HASWELL_ULT_M_GT3
:
516 case PCI_CHIP_HASWELL_CRW_M_GT1
:
517 case PCI_CHIP_HASWELL_CRW_M_GT2
:
518 case PCI_CHIP_HASWELL_CRW_M_GT3
:
519 chipset
= "Intel(R) Haswell Mobile";
521 case PCI_CHIP_HASWELL_S_GT1
:
522 case PCI_CHIP_HASWELL_S_GT2
:
523 case PCI_CHIP_HASWELL_S_GT3
:
524 case PCI_CHIP_HASWELL_SDV_S_GT1
:
525 case PCI_CHIP_HASWELL_SDV_S_GT2
:
526 case PCI_CHIP_HASWELL_SDV_S_GT3
:
527 case PCI_CHIP_HASWELL_ULT_S_GT1
:
528 case PCI_CHIP_HASWELL_ULT_S_GT2
:
529 case PCI_CHIP_HASWELL_ULT_S_GT3
:
530 case PCI_CHIP_HASWELL_CRW_S_GT1
:
531 case PCI_CHIP_HASWELL_CRW_S_GT2
:
532 case PCI_CHIP_HASWELL_CRW_S_GT3
:
533 chipset
= "Intel(R) Haswell Server";
536 chipset
= "Unknown Intel Chipset";
544 ilo_get_timestamp(struct pipe_screen
*screen
)
546 struct ilo_screen
*is
= ilo_screen(screen
);
552 intel_winsys_read_reg(is
->winsys
, TIMESTAMP
, ×tamp
.val
);
555 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
557 * "Note: This timestamp register reflects the value of the PCU TSC.
558 * The PCU TSC counts 10ns increments; this timestamp reflects bits
559 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
562 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
563 * of the timestamp. We will have to live with a timestamp that rolls over
564 * every ~343 seconds.
566 * See also brw_get_timestamp().
568 return (uint64_t) timestamp
.dw
[1] * 80;
572 ilo_fence_reference(struct pipe_screen
*screen
,
573 struct pipe_fence_handle
**p
,
574 struct pipe_fence_handle
*f
)
576 struct ilo_fence
**ptr
= (struct ilo_fence
**) p
;
577 struct ilo_fence
*fence
= ilo_fence(f
);
580 /* still need to reference fence */
582 pipe_reference(NULL
, &fence
->reference
);
586 /* reference fence and dereference the one pointed to by ptr */
587 if (*ptr
&& pipe_reference(&(*ptr
)->reference
, &fence
->reference
)) {
588 struct ilo_fence
*old
= *ptr
;
591 intel_bo_unreference(old
->bo
);
599 ilo_fence_signalled(struct pipe_screen
*screen
,
600 struct pipe_fence_handle
*f
)
602 struct ilo_fence
*fence
= ilo_fence(f
);
604 /* mark signalled if the bo is idle */
605 if (fence
->bo
&& !intel_bo_is_busy(fence
->bo
)) {
606 intel_bo_unreference(fence
->bo
);
610 return (fence
->bo
== NULL
);
614 ilo_fence_finish(struct pipe_screen
*screen
,
615 struct pipe_fence_handle
*f
,
618 struct ilo_fence
*fence
= ilo_fence(f
);
619 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
621 /* already signalled */
625 /* wait and see if it returns error */
626 if (intel_bo_wait(fence
->bo
, wait_timeout
))
630 intel_bo_unreference(fence
->bo
);
637 ilo_screen_destroy(struct pipe_screen
*screen
)
639 struct ilo_screen
*is
= ilo_screen(screen
);
641 /* as it seems, winsys is owned by the screen */
642 intel_winsys_destroy(is
->winsys
);
648 init_dev(struct ilo_dev_info
*dev
, const struct intel_winsys_info
*info
)
650 dev
->devid
= info
->devid
;
651 dev
->max_batch_size
= info
->max_batch_size
;
652 dev
->has_llc
= info
->has_llc
;
653 dev
->has_address_swizzling
= info
->has_address_swizzling
;
654 dev
->has_logical_context
= info
->has_logical_context
;
655 dev
->has_ppgtt
= info
->has_ppgtt
;
656 dev
->has_timestamp
= info
->has_timestamp
;
657 dev
->has_gen7_sol_reset
= info
->has_gen7_sol_reset
;
659 if (!dev
->has_logical_context
) {
660 ilo_err("missing hardware logical context support\n");
665 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
668 * From the Sandy Bridge PRM, volume 1 part 3, page 101:
670 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
671 * code is in a secure environment, independent of address space.
672 * Under this condition, this bit only specifies the address space
673 * (GGTT or PPGTT). All commands are executed "as-is""
675 * We need PPGTT to be enabled on GEN6 too.
677 if (!dev
->has_ppgtt
) {
678 /* experiments show that it does not really matter... */
679 ilo_warn("PPGTT disabled\n");
683 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
685 * "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
686 * as 1024 256-bit rows. The GT2 product's URB provides 64KB of
687 * storage, arranged as 2048 256-bit rows. A row corresponds in size
688 * to an EU GRF register. Read/write access to the URB is generally
689 * supported on a row-granular basis."
691 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
693 * "URB Size URB Rows URB Rows when SLM Enabled
698 if (IS_HASWELL(info
->devid
)) {
699 dev
->gen
= ILO_GEN(7.5);
701 if (IS_HSW_GT3(info
->devid
)) {
703 dev
->urb_size
= 512 * 1024;
705 else if (IS_HSW_GT2(info
->devid
)) {
707 dev
->urb_size
= 256 * 1024;
711 dev
->urb_size
= 128 * 1024;
714 else if (IS_GEN7(info
->devid
)) {
715 dev
->gen
= ILO_GEN(7);
717 if (IS_IVB_GT2(info
->devid
)) {
719 dev
->urb_size
= 256 * 1024;
723 dev
->urb_size
= 128 * 1024;
726 else if (IS_GEN6(info
->devid
)) {
727 dev
->gen
= ILO_GEN(6);
729 if (IS_SNB_GT2(info
->devid
)) {
731 dev
->urb_size
= 64 * 1024;
735 dev
->urb_size
= 32 * 1024;
739 ilo_err("unknown GPU generation\n");
747 ilo_screen_create(struct intel_winsys
*ws
)
749 struct ilo_screen
*is
;
750 const struct intel_winsys_info
*info
;
752 ilo_debug
= debug_get_flags_option("ILO_DEBUG", ilo_debug_flags
, 0);
754 is
= CALLOC_STRUCT(ilo_screen
);
760 info
= intel_winsys_get_info(is
->winsys
);
761 if (!init_dev(&is
->dev
, info
)) {
766 util_format_s3tc_init();
768 is
->base
.destroy
= ilo_screen_destroy
;
769 is
->base
.get_name
= ilo_get_name
;
770 is
->base
.get_vendor
= ilo_get_vendor
;
771 is
->base
.get_param
= ilo_get_param
;
772 is
->base
.get_paramf
= ilo_get_paramf
;
773 is
->base
.get_shader_param
= ilo_get_shader_param
;
774 is
->base
.get_video_param
= ilo_get_video_param
;
775 is
->base
.get_compute_param
= ilo_get_compute_param
;
777 is
->base
.get_timestamp
= ilo_get_timestamp
;
779 is
->base
.flush_frontbuffer
= NULL
;
781 is
->base
.fence_reference
= ilo_fence_reference
;
782 is
->base
.fence_signalled
= ilo_fence_signalled
;
783 is
->base
.fence_finish
= ilo_fence_finish
;
785 is
->base
.get_driver_query_info
= NULL
;
787 ilo_init_format_functions(is
);
788 ilo_init_context_functions(is
);
789 ilo_init_resource_functions(is
);