src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "intel_winsys.h"
  35
  36 #include "ilo_context.h"
  37 #include "ilo_format.h"
  38 #include "ilo_resource.h"
  39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  40 #include "ilo_public.h"
  41 #include "ilo_screen.h"
  42
  43 struct ilo_fence {
  44    struct pipe_reference reference;
  45    struct intel_bo *bo;
  46 };
  47
  48 int ilo_debug;
  49
  50 static const struct debug_named_value ilo_debug_flags[] = {
  51    { "batch",     ILO_DEBUG_BATCH,    "Dump batch/state/surface/instruction buffers" },
  52    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  53    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  54    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  55    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  56    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  57    { "submit",    ILO_DEBUG_SUBMIT,   "Show batch buffer submissions" },
  58    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  59    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  60    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  61    DEBUG_NAMED_VALUE_END
  62 };
  63
  64 static float
  65 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  66 {
  67    switch (param) {
  68    case PIPE_CAPF_MAX_LINE_WIDTH:
  69       /* in U3.7, defined in 3DSTATE_SF */
  70       return 7.0f;
  71    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  72       /* line width minus one, which is reserved for AA region */
  73       return 6.0f;
  74    case PIPE_CAPF_MAX_POINT_WIDTH:
  75       /* in U8.3, defined in 3DSTATE_SF */
  76       return 255.0f;
  77    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  78       /* same as point width, as we ignore rasterizer->point_smooth */
  79       return 255.0f;
  80    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  81       /* [2.0, 16.0], defined in SAMPLER_STATE */
  82       return 16.0f;
  83    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  84       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  85       return 15.0f;
  86    case PIPE_CAPF_GUARD_BAND_LEFT:
  87    case PIPE_CAPF_GUARD_BAND_TOP:
  88    case PIPE_CAPF_GUARD_BAND_RIGHT:
  89    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  90       /* what are these for? */
  91       return 0.0f;
  92
  93    default:
  94       return 0.0f;
  95    }
  96 }
  97
  98 static int
  99 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
 100                      enum pipe_shader_cap param)
 101 {
 102    switch (shader) {
 103    case PIPE_SHADER_FRAGMENT:
 104    case PIPE_SHADER_VERTEX:
 105    case PIPE_SHADER_GEOMETRY:
 106       break;
 107    default:
 108       return 0;
 109    }
 110
 111    switch (param) {
 112    /* the limits are copied from the classic driver */
 113    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 114       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 115    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 116       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 117    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 118       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 119    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 120       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 121    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 122       return UINT_MAX;
 123    case PIPE_SHADER_CAP_MAX_INPUTS:
 124       /* this is limited by how many attributes SF can remap */
 125       return 16;
 126    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 127       return 1024 * sizeof(float[4]);
 128    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 129       return ILO_MAX_CONST_BUFFERS;
 130    case PIPE_SHADER_CAP_MAX_TEMPS:
 131       return 256;
 132    case PIPE_SHADER_CAP_MAX_PREDS:
 133       return 0;
 134    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 135       return 1;
 136    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 137       return 0;
 138    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 139       return 0;
 140    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 141       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 142    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 143       return 1;
 144    case PIPE_SHADER_CAP_SUBROUTINES:
 145       return 0;
 146    case PIPE_SHADER_CAP_INTEGERS:
 147       return 1;
 148    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 149       return ILO_MAX_SAMPLERS;
 150    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 151       return ILO_MAX_SAMPLER_VIEWS;
 152    case PIPE_SHADER_CAP_PREFERRED_IR:
 153       return PIPE_SHADER_IR_TGSI;
 154    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 155       return 1;
 156
 157    default:
 158       return 0;
 159    }
 160 }
 161
 162 static int
 163 ilo_get_video_param(struct pipe_screen *screen,
 164                     enum pipe_video_profile profile,
 165                     enum pipe_video_entrypoint entrypoint,
 166                     enum pipe_video_cap param)
 167 {
 168    switch (param) {
 169    case PIPE_VIDEO_CAP_SUPPORTED:
 170       return vl_profile_supported(screen, profile, entrypoint);
 171    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 172       return 1;
 173    case PIPE_VIDEO_CAP_MAX_WIDTH:
 174    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 175       return vl_video_buffer_max_size(screen);
 176    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 177       return PIPE_FORMAT_NV12;
 178    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 179       return 1;
 180    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 181       return 1;
 182    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 183       return 0;
 184    case PIPE_VIDEO_CAP_MAX_LEVEL:
 185       return vl_level_supported(screen, profile);
 186    default:
 187       return 0;
 188    }
 189 }
 190
 191 static int
 192 ilo_get_compute_param(struct pipe_screen *screen,
 193                       enum pipe_compute_cap param,
 194                       void *ret)
 195 {
 196    union {
 197       const char *ir_target;
 198       uint64_t grid_dimension;
 199       uint64_t max_grid_size[3];
 200       uint64_t max_block_size[3];
 201       uint64_t max_threads_per_block;
 202       uint64_t max_global_size;
 203       uint64_t max_local_size;
 204       uint64_t max_private_size;
 205       uint64_t max_input_size;
 206       uint64_t max_mem_alloc_size;
 207    } val;
 208    const void *ptr;
 209    int size;
 210
 211    /* XXX some randomly chosen values */
 212    switch (param) {
 213    case PIPE_COMPUTE_CAP_IR_TARGET:
 214       val.ir_target = "ilog";
 215
 216       ptr = val.ir_target;
 217       size = strlen(val.ir_target) + 1;
 218       break;
 219    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 220       val.grid_dimension = Elements(val.max_grid_size);
 221
 222       ptr = &val.grid_dimension;
 223       size = sizeof(val.grid_dimension);
 224       break;
 225    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 226       val.max_grid_size[0] = 65535;
 227       val.max_grid_size[1] = 65535;
 228       val.max_grid_size[2] = 1;
 229
 230       ptr = &val.max_grid_size;
 231       size = sizeof(val.max_grid_size);
 232       break;
 233    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 234       val.max_block_size[0] = 512;
 235       val.max_block_size[1] = 512;
 236       val.max_block_size[2] = 512;
 237
 238       ptr = &val.max_block_size;
 239       size = sizeof(val.max_block_size);
 240       break;
 241
 242    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 243       val.max_threads_per_block = 512;
 244
 245       ptr = &val.max_threads_per_block;
 246       size = sizeof(val.max_threads_per_block);
 247       break;
 248    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 249       val.max_global_size = 4;
 250
 251       ptr = &val.max_global_size;
 252       size = sizeof(val.max_global_size);
 253       break;
 254    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 255       val.max_local_size = 64 * 1024;
 256
 257       ptr = &val.max_local_size;
 258       size = sizeof(val.max_local_size);
 259       break;
 260    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 261       val.max_private_size = 32768;
 262
 263       ptr = &val.max_private_size;
 264       size = sizeof(val.max_private_size);
 265       break;
 266    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 267       val.max_input_size = 256;
 268
 269       ptr = &val.max_input_size;
 270       size = sizeof(val.max_input_size);
 271       break;
 272    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 273       val.max_mem_alloc_size = 128 * 1024 * 1024;
 274
 275       ptr = &val.max_mem_alloc_size;
 276       size = sizeof(val.max_mem_alloc_size);
 277       break;
 278    default:
 279       ptr = NULL;
 280       size = 0;
 281       break;
 282    }
 283
 284    if (ret)
 285       memcpy(ret, ptr, size);
 286
 287    return size;
 288 }
 289
 290 static int
 291 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 292 {
 293    struct ilo_screen *is = ilo_screen(screen);
 294
 295    switch (param) {
 296    case PIPE_CAP_NPOT_TEXTURES:
 297    case PIPE_CAP_TWO_SIDED_STENCIL:
 298       return true;
 299    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 300       return 0; /* TODO */
 301    case PIPE_CAP_ANISOTROPIC_FILTER:
 302    case PIPE_CAP_POINT_SPRITE:
 303       return true;
 304    case PIPE_CAP_MAX_RENDER_TARGETS:
 305       return ILO_MAX_DRAW_BUFFERS;
 306    case PIPE_CAP_OCCLUSION_QUERY:
 307    case PIPE_CAP_QUERY_TIME_ELAPSED:
 308    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 309    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 310       return true;
 311    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 312       /*
 313        * As defined in SURFACE_STATE, we have
 314        *
 315        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 316        *  GEN6           8192x8192x512            2048x2048x2048
 317        *  GEN7         16384x16384x2048           2048x2048x2048
 318        */
 319       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 320    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 321       return 12;
 322    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 323       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 324    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 325       return false;
 326    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 327    case PIPE_CAP_SM3:
 328       return true;
 329    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 330       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 331          return 0;
 332       return ILO_MAX_SO_BUFFERS;
 333    case PIPE_CAP_PRIMITIVE_RESTART:
 334       return true;
 335    case PIPE_CAP_INDEP_BLEND_ENABLE:
 336    case PIPE_CAP_INDEP_BLEND_FUNC:
 337       return true;
 338    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 339       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
 340    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 341    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 342    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 343    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 344    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 345       return true;
 346    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 347       return false;
 348    case PIPE_CAP_TGSI_INSTANCEID:
 349    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 350       return true;
 351    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 352       return false;
 353    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 354       return true;
 355    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 356    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 357       return true;
 358    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 359    case PIPE_CAP_MIN_TEXEL_OFFSET:
 360       return -8;
 361    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 362    case PIPE_CAP_MAX_TEXEL_OFFSET:
 363       return 7;
 364    case PIPE_CAP_CONDITIONAL_RENDER:
 365    case PIPE_CAP_TEXTURE_BARRIER:
 366       return true;
 367    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 368       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 369    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 370       return ILO_MAX_SO_BINDINGS;
 371    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 372       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 373          return is->dev.has_gen7_sol_reset;
 374       else
 375          return false; /* TODO */
 376    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 377       return false;
 378    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 379       return true;
 380    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 381       return false;
 382    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 383       return 140;
 384    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 385    case PIPE_CAP_USER_VERTEX_BUFFERS:
 386       return false;
 387    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 388    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 389    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 390       return false;
 391    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 392       return 2048;
 393    case PIPE_CAP_COMPUTE:
 394       return false; /* TODO */
 395    case PIPE_CAP_USER_INDEX_BUFFERS:
 396    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 397       return true;
 398    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 399       /* imposed by OWord (Dual) Block Read */
 400       return 16;
 401    case PIPE_CAP_START_INSTANCE:
 402       return true;
 403    case PIPE_CAP_QUERY_TIMESTAMP:
 404       return is->dev.has_timestamp;
 405    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 406       return false; /* TODO */
 407    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 408       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 409    case PIPE_CAP_CUBE_MAP_ARRAY:
 410    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 411       return true;
 412    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 413       return 1;
 414    case PIPE_CAP_TGSI_TEXCOORD:
 415       return false;
 416    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 417    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 418       return true;
 419    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 420       return 0;
 421    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 422       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 423       return 1 << 27;
 424    case PIPE_CAP_MAX_VIEWPORTS:
 425       return ILO_MAX_VIEWPORTS;
 426    case PIPE_CAP_ENDIANNESS:
 427       return PIPE_ENDIAN_LITTLE;
 428    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 429       return true;
 430    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 431    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 432    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 433    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 434    case PIPE_CAP_TEXTURE_GATHER_SM5:
 435       return 0;
 436    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 437       return true;
 438    case PIPE_CAP_FAKE_SW_MSAA:
 439    case PIPE_CAP_TEXTURE_QUERY_LOD:
 440    case PIPE_CAP_SAMPLE_SHADING:
 441    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 442    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 443    case PIPE_CAP_MAX_VERTEX_STREAMS:
 444    case PIPE_CAP_DRAW_INDIRECT:
 445    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 446    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 447    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 448       return 0;
 449
 450    case PIPE_CAP_VENDOR_ID:
 451       return 0x8086;
 452    case PIPE_CAP_DEVICE_ID:
 453       return is->dev.devid;
 454    case PIPE_CAP_ACCELERATED:
 455       return true;
 456    case PIPE_CAP_VIDEO_MEMORY: {
 457       /* Once a batch uses more than 75% of the maximum mappable size, we
 458        * assume that there's some fragmentation, and we start doing extra
 459        * flushing, etc.  That's the big cliff apps will care about.
 460        */
 461       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 462       uint64_t system_memory;
 463
 464       if (!os_get_total_physical_memory(&system_memory))
 465          return 0;
 466
 467       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 468    }
 469    case PIPE_CAP_UMA:
 470       return true;
 471
 472    default:
 473       return 0;
 474    }
 475 }
 476
 477 static const char *
 478 ilo_get_vendor(struct pipe_screen *screen)
 479 {
 480    return "LunarG, Inc.";
 481 }
 482
 483 static const char *
 484 ilo_get_name(struct pipe_screen *screen)
 485 {
 486    struct ilo_screen *is = ilo_screen(screen);
 487    const char *chipset = NULL;
 488
 489    if (gen_is_vlv(is->dev.devid)) {
 490       chipset = "Intel(R) Bay Trail";
 491    }
 492    else if (gen_is_hsw(is->dev.devid)) {
 493       if (gen_is_desktop(is->dev.devid))
 494          chipset = "Intel(R) Haswell Desktop";
 495       else if (gen_is_mobile(is->dev.devid))
 496          chipset = "Intel(R) Haswell Mobile";
 497       else if (gen_is_server(is->dev.devid))
 498          chipset = "Intel(R) Haswell Server";
 499    }
 500    else if (gen_is_ivb(is->dev.devid)) {
 501       if (gen_is_desktop(is->dev.devid))
 502          chipset = "Intel(R) Ivybridge Desktop";
 503       else if (gen_is_mobile(is->dev.devid))
 504          chipset = "Intel(R) Ivybridge Mobile";
 505       else if (gen_is_server(is->dev.devid))
 506          chipset = "Intel(R) Ivybridge Server";
 507    }
 508    else if (gen_is_snb(is->dev.devid)) {
 509       if (gen_is_desktop(is->dev.devid))
 510          chipset = "Intel(R) Sandybridge Desktop";
 511       else if (gen_is_mobile(is->dev.devid))
 512          chipset = "Intel(R) Sandybridge Mobile";
 513       else if (gen_is_server(is->dev.devid))
 514          chipset = "Intel(R) Sandybridge Server";
 515    }
 516
 517    if (!chipset)
 518       chipset = "Unknown Intel Chipset";
 519
 520    return chipset;
 521 }
 522
 523 static uint64_t
 524 ilo_get_timestamp(struct pipe_screen *screen)
 525 {
 526    struct ilo_screen *is = ilo_screen(screen);
 527    union {
 528       uint64_t val;
 529       uint32_t dw[2];
 530    } timestamp;
 531
 532    intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 533
 534    /*
 535     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 536     *
 537     *     "Note: This timestamp register reflects the value of the PCU TSC.
 538     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 539     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 540     *      hours)."
 541     *
 542     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 543     * of the timestamp.  We will have to live with a timestamp that rolls over
 544     * every ~343 seconds.
 545     *
 546     * See also brw_get_timestamp().
 547     */
 548    return (uint64_t) timestamp.dw[1] * 80;
 549 }
 550
 551 static void
 552 ilo_fence_reference(struct pipe_screen *screen,
 553                     struct pipe_fence_handle **p,
 554                     struct pipe_fence_handle *f)
 555 {
 556    struct ilo_fence *fence = ilo_fence(f);
 557    struct ilo_fence *old;
 558
 559    if (likely(p)) {
 560       old = ilo_fence(*p);
 561       *p = f;
 562    }
 563    else {
 564       old = NULL;
 565    }
 566
 567    STATIC_ASSERT(&((struct ilo_fence *) NULL)->reference == NULL);
 568    if (pipe_reference(&old->reference, &fence->reference)) {
 569       if (old->bo)
 570          intel_bo_unreference(old->bo);
 571       FREE(old);
 572    }
 573 }
 574
 575 static boolean
 576 ilo_fence_signalled(struct pipe_screen *screen,
 577                     struct pipe_fence_handle *f)
 578 {
 579    struct ilo_fence *fence = ilo_fence(f);
 580
 581    /* mark signalled if the bo is idle */
 582    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 583       intel_bo_unreference(fence->bo);
 584       fence->bo = NULL;
 585    }
 586
 587    return (fence->bo == NULL);
 588 }
 589
 590 static boolean
 591 ilo_fence_finish(struct pipe_screen *screen,
 592                  struct pipe_fence_handle *f,
 593                  uint64_t timeout)
 594 {
 595    struct ilo_fence *fence = ilo_fence(f);
 596    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 597
 598    /* already signalled */
 599    if (!fence->bo)
 600       return true;
 601
 602    /* wait and see if it returns error */
 603    if (intel_bo_wait(fence->bo, wait_timeout))
 604       return false;
 605
 606    /* mark signalled */
 607    intel_bo_unreference(fence->bo);
 608    fence->bo = NULL;
 609
 610    return true;
 611 }
 612
 613 /**
 614  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 615  * before waited on or checked.
 616  */
 617 struct ilo_fence *
 618 ilo_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 619 {
 620    struct ilo_fence *fence;
 621
 622    fence = CALLOC_STRUCT(ilo_fence);
 623    if (!fence)
 624       return NULL;
 625
 626    pipe_reference_init(&fence->reference, 1);
 627
 628    if (bo)
 629       intel_bo_reference(bo);
 630    fence->bo = bo;
 631
 632    return fence;
 633 }
 634
 635 static void
 636 ilo_screen_destroy(struct pipe_screen *screen)
 637 {
 638    struct ilo_screen *is = ilo_screen(screen);
 639
 640    /* as it seems, winsys is owned by the screen */
 641    intel_winsys_destroy(is->winsys);
 642
 643    FREE(is);
 644 }
 645
 646 static bool
 647 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 648 {
 649    dev->devid = info->devid;
 650    dev->aperture_total = info->aperture_total;
 651    dev->aperture_mappable = info->aperture_mappable;
 652    dev->has_llc = info->has_llc;
 653    dev->has_address_swizzling = info->has_address_swizzling;
 654    dev->has_logical_context = info->has_logical_context;
 655    dev->has_ppgtt = info->has_ppgtt;
 656    dev->has_timestamp = info->has_timestamp;
 657    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 658
 659    if (!dev->has_logical_context) {
 660       ilo_err("missing hardware logical context support\n");
 661       return false;
 662    }
 663
 664    /*
 665     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 666     * writes on GEN6.
 667     *
 668     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 669     *
 670     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 671     *      code is in a secure environment, independent of address space.
 672     *      Under this condition, this bit only specifies the address space
 673     *      (GGTT or PPGTT). All commands are executed "as-is""
 674     *
 675     * We need PPGTT to be enabled on GEN6 too.
 676     */
 677    if (!dev->has_ppgtt) {
 678       /* experiments show that it does not really matter... */
 679       ilo_warn("PPGTT disabled\n");
 680    }
 681
 682    /*
 683     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 684     *
 685     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 686     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 687     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 688     *      to an EU GRF register. Read/write access to the URB is generally
 689     *      supported on a row-granular basis."
 690     *
 691     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 692     *
 693     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 694     *      128k        4096        2048
 695     *      256k        8096        4096"
 696     */
 697
 698    if (gen_is_hsw(info->devid)) {
 699       dev->gen_opaque = ILO_GEN(7.5);
 700       dev->gt = gen_get_hsw_gt(info->devid);
 701       dev->urb_size = ((dev->gt == 3) ? 512 :
 702                        (dev->gt == 2) ? 256 : 128) * 1024;
 703    }
 704    else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 705       dev->gen_opaque = ILO_GEN(7);
 706       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 707       dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
 708    }
 709    else if (gen_is_snb(info->devid)) {
 710       dev->gen_opaque = ILO_GEN(6);
 711       dev->gt = gen_get_snb_gt(info->devid);
 712       dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
 713    }
 714    else {
 715       ilo_err("unknown GPU generation\n");
 716       return false;
 717    }
 718
 719    return true;
 720 }
 721
 722 struct pipe_screen *
 723 ilo_screen_create(struct intel_winsys *ws)
 724 {
 725    struct ilo_screen *is;
 726    const struct intel_winsys_info *info;
 727
 728    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 729
 730    is = CALLOC_STRUCT(ilo_screen);
 731    if (!is)
 732       return NULL;
 733
 734    is->winsys = ws;
 735
 736    info = intel_winsys_get_info(is->winsys);
 737    if (!init_dev(&is->dev, info)) {
 738       FREE(is);
 739       return NULL;
 740    }
 741
 742    util_format_s3tc_init();
 743
 744    is->base.destroy = ilo_screen_destroy;
 745    is->base.get_name = ilo_get_name;
 746    is->base.get_vendor = ilo_get_vendor;
 747    is->base.get_param = ilo_get_param;
 748    is->base.get_paramf = ilo_get_paramf;
 749    is->base.get_shader_param = ilo_get_shader_param;
 750    is->base.get_video_param = ilo_get_video_param;
 751    is->base.get_compute_param = ilo_get_compute_param;
 752
 753    is->base.get_timestamp = ilo_get_timestamp;
 754
 755    is->base.flush_frontbuffer = NULL;
 756
 757    is->base.fence_reference = ilo_fence_reference;
 758    is->base.fence_signalled = ilo_fence_signalled;
 759    is->base.fence_finish = ilo_fence_finish;
 760
 761    is->base.get_driver_query_info = NULL;
 762
 763    ilo_init_format_functions(is);
 764    ilo_init_context_functions(is);
 765    ilo_init_resource_functions(is);
 766
 767    return &is->base;
 768 }