src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "core/intel_winsys.h"
  35
  36 #include "ilo_context.h"
  37 #include "ilo_format.h"
  38 #include "ilo_resource.h"
  39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  40 #include "ilo_public.h"
  41 #include "ilo_screen.h"
  42
  43 struct pipe_fence_handle {
  44    struct pipe_reference reference;
  45    struct intel_bo *seqno_bo;
  46 };
  47
  48 static float
  49 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  50 {
  51    switch (param) {
  52    case PIPE_CAPF_MAX_LINE_WIDTH:
  53       /* in U3.7, defined in 3DSTATE_SF */
  54       return 7.0f;
  55    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  56       /* line width minus one, which is reserved for AA region */
  57       return 6.0f;
  58    case PIPE_CAPF_MAX_POINT_WIDTH:
  59       /* in U8.3, defined in 3DSTATE_SF */
  60       return 255.0f;
  61    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  62       /* same as point width, as we ignore rasterizer->point_smooth */
  63       return 255.0f;
  64    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  65       /* [2.0, 16.0], defined in SAMPLER_STATE */
  66       return 16.0f;
  67    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  68       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  69       return 15.0f;
  70    case PIPE_CAPF_GUARD_BAND_LEFT:
  71    case PIPE_CAPF_GUARD_BAND_TOP:
  72    case PIPE_CAPF_GUARD_BAND_RIGHT:
  73    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  74       /* what are these for? */
  75       return 0.0f;
  76
  77    default:
  78       return 0.0f;
  79    }
  80 }
  81
  82 static int
  83 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  84                      enum pipe_shader_cap param)
  85 {
  86    switch (shader) {
  87    case PIPE_SHADER_FRAGMENT:
  88    case PIPE_SHADER_VERTEX:
  89    case PIPE_SHADER_GEOMETRY:
  90       break;
  91    default:
  92       return 0;
  93    }
  94
  95    switch (param) {
  96    /* the limits are copied from the classic driver */
  97    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  98       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
  99    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 100       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 101    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 102       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 103    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 104       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 105    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 106       return UINT_MAX;
 107    case PIPE_SHADER_CAP_MAX_INPUTS:
 108    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 109       /* this is limited by how many attributes SF can remap */
 110       return 16;
 111    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 112       return 1024 * sizeof(float[4]);
 113    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 114       return ILO_MAX_CONST_BUFFERS;
 115    case PIPE_SHADER_CAP_MAX_TEMPS:
 116       return 256;
 117    case PIPE_SHADER_CAP_MAX_PREDS:
 118       return 0;
 119    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 120       return 1;
 121    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 122       return 0;
 123    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 124       return 0;
 125    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 126       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 127    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 128       return 1;
 129    case PIPE_SHADER_CAP_SUBROUTINES:
 130       return 0;
 131    case PIPE_SHADER_CAP_INTEGERS:
 132       return 1;
 133    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 134       return ILO_MAX_SAMPLERS;
 135    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 136       return ILO_MAX_SAMPLER_VIEWS;
 137    case PIPE_SHADER_CAP_PREFERRED_IR:
 138       return PIPE_SHADER_IR_TGSI;
 139    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 140       return 1;
 141
 142    default:
 143       return 0;
 144    }
 145 }
 146
 147 static int
 148 ilo_get_video_param(struct pipe_screen *screen,
 149                     enum pipe_video_profile profile,
 150                     enum pipe_video_entrypoint entrypoint,
 151                     enum pipe_video_cap param)
 152 {
 153    switch (param) {
 154    case PIPE_VIDEO_CAP_SUPPORTED:
 155       return vl_profile_supported(screen, profile, entrypoint);
 156    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 157       return 1;
 158    case PIPE_VIDEO_CAP_MAX_WIDTH:
 159    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 160       return vl_video_buffer_max_size(screen);
 161    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 162       return PIPE_FORMAT_NV12;
 163    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 164       return 1;
 165    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 166       return 1;
 167    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 168       return 0;
 169    case PIPE_VIDEO_CAP_MAX_LEVEL:
 170       return vl_level_supported(screen, profile);
 171    default:
 172       return 0;
 173    }
 174 }
 175
 176 static int
 177 ilo_get_compute_param(struct pipe_screen *screen,
 178                       enum pipe_compute_cap param,
 179                       void *ret)
 180 {
 181    struct ilo_screen *is = ilo_screen(screen);
 182    union {
 183       const char *ir_target;
 184       uint64_t grid_dimension;
 185       uint64_t max_grid_size[3];
 186       uint64_t max_block_size[3];
 187       uint64_t max_threads_per_block;
 188       uint64_t max_global_size;
 189       uint64_t max_local_size;
 190       uint64_t max_private_size;
 191       uint64_t max_input_size;
 192       uint64_t max_mem_alloc_size;
 193       uint32_t max_clock_frequency;
 194       uint32_t max_compute_units;
 195       uint32_t images_supported;
 196       uint32_t subgroup_size;
 197    } val;
 198    const void *ptr;
 199    int size;
 200
 201    switch (param) {
 202    case PIPE_COMPUTE_CAP_IR_TARGET:
 203       val.ir_target = "ilog";
 204
 205       ptr = val.ir_target;
 206       size = strlen(val.ir_target) + 1;
 207       break;
 208    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 209       val.grid_dimension = Elements(val.max_grid_size);
 210
 211       ptr = &val.grid_dimension;
 212       size = sizeof(val.grid_dimension);
 213       break;
 214    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 215       val.max_grid_size[0] = 0xffffffffu;
 216       val.max_grid_size[1] = 0xffffffffu;
 217       val.max_grid_size[2] = 0xffffffffu;
 218
 219       ptr = &val.max_grid_size;
 220       size = sizeof(val.max_grid_size);
 221       break;
 222    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 223       val.max_block_size[0] = 1024;
 224       val.max_block_size[1] = 1024;
 225       val.max_block_size[2] = 1024;
 226
 227       ptr = &val.max_block_size;
 228       size = sizeof(val.max_block_size);
 229       break;
 230
 231    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 232       val.max_threads_per_block = 1024;
 233
 234       ptr = &val.max_threads_per_block;
 235       size = sizeof(val.max_threads_per_block);
 236       break;
 237    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 238       /* \see ilo_max_resource_size */
 239       val.max_global_size = 1u << 31;
 240
 241       ptr = &val.max_global_size;
 242       size = sizeof(val.max_global_size);
 243       break;
 244    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 245       /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
 246       val.max_local_size = 64 * 1024;
 247
 248       ptr = &val.max_local_size;
 249       size = sizeof(val.max_local_size);
 250       break;
 251    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 252       /* scratch size */
 253       val.max_private_size = 12 * 1024;
 254
 255       ptr = &val.max_private_size;
 256       size = sizeof(val.max_private_size);
 257       break;
 258    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 259       val.max_input_size = 1024;
 260
 261       ptr = &val.max_input_size;
 262       size = sizeof(val.max_input_size);
 263       break;
 264    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 265       val.max_mem_alloc_size = 1u << 31;
 266
 267       ptr = &val.max_mem_alloc_size;
 268       size = sizeof(val.max_mem_alloc_size);
 269       break;
 270    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 271       val.max_clock_frequency = 1000;
 272
 273       ptr = &val.max_clock_frequency;
 274       size = sizeof(val.max_clock_frequency);
 275       break;
 276    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 277       val.max_compute_units = is->dev.eu_count;
 278
 279       ptr = &val.max_compute_units;
 280       size = sizeof(val.max_compute_units);
 281       break;
 282    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 283       val.images_supported = 1;
 284
 285       ptr = &val.images_supported;
 286       size = sizeof(val.images_supported);
 287       break;
 288    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 289       /* best case is actually SIMD32 */
 290       val.subgroup_size = 16;
 291
 292       ptr = &val.subgroup_size;
 293       size = sizeof(val.subgroup_size);
 294       break;
 295    default:
 296       ptr = NULL;
 297       size = 0;
 298       break;
 299    }
 300
 301    if (ret)
 302       memcpy(ret, ptr, size);
 303
 304    return size;
 305 }
 306
 307 static int
 308 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 309 {
 310    struct ilo_screen *is = ilo_screen(screen);
 311
 312    switch (param) {
 313    case PIPE_CAP_NPOT_TEXTURES:
 314    case PIPE_CAP_TWO_SIDED_STENCIL:
 315       return true;
 316    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 317       return 0; /* TODO */
 318    case PIPE_CAP_ANISOTROPIC_FILTER:
 319    case PIPE_CAP_POINT_SPRITE:
 320       return true;
 321    case PIPE_CAP_MAX_RENDER_TARGETS:
 322       return ILO_MAX_DRAW_BUFFERS;
 323    case PIPE_CAP_OCCLUSION_QUERY:
 324    case PIPE_CAP_QUERY_TIME_ELAPSED:
 325    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 326    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 327       return true;
 328    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 329       /*
 330        * As defined in SURFACE_STATE, we have
 331        *
 332        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 333        *  GEN6           8192x8192x512            2048x2048x2048
 334        *  GEN7         16384x16384x2048           2048x2048x2048
 335        */
 336       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 337    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 338       return 12;
 339    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 340       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 341    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 342       return false;
 343    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 344    case PIPE_CAP_SM3:
 345       return true;
 346    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 347       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 348          return 0;
 349       return ILO_MAX_SO_BUFFERS;
 350    case PIPE_CAP_PRIMITIVE_RESTART:
 351       return true;
 352    case PIPE_CAP_INDEP_BLEND_ENABLE:
 353    case PIPE_CAP_INDEP_BLEND_FUNC:
 354       return true;
 355    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 356       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7.5)) ? 2048 : 512;
 357    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 358    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 359    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 360    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 361    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 362       return true;
 363    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 364       return false;
 365    case PIPE_CAP_TGSI_INSTANCEID:
 366    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 367       return true;
 368    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 369       return false;
 370    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 371       return true;
 372    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 373    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 374       return true;
 375    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 376    case PIPE_CAP_MIN_TEXEL_OFFSET:
 377       return -8;
 378    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 379    case PIPE_CAP_MAX_TEXEL_OFFSET:
 380       return 7;
 381    case PIPE_CAP_CONDITIONAL_RENDER:
 382    case PIPE_CAP_TEXTURE_BARRIER:
 383       return true;
 384    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 385       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 386    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 387       return ILO_MAX_SO_BINDINGS;
 388    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 389       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 390          return is->dev.has_gen7_sol_reset;
 391       else
 392          return false; /* TODO */
 393    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 394       return false;
 395    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 396       return true;
 397    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 398       return false;
 399    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 400       return 140;
 401    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 402    case PIPE_CAP_USER_VERTEX_BUFFERS:
 403       return false;
 404    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 405    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 406    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 407       return false;
 408    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 409       return 2048;
 410    case PIPE_CAP_COMPUTE:
 411       return false; /* TODO */
 412    case PIPE_CAP_USER_INDEX_BUFFERS:
 413    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 414       return true;
 415    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 416       /* imposed by OWord (Dual) Block Read */
 417       return 16;
 418    case PIPE_CAP_START_INSTANCE:
 419       return true;
 420    case PIPE_CAP_QUERY_TIMESTAMP:
 421       return is->dev.has_timestamp;
 422    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 423       return false; /* TODO */
 424    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 425       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 426    case PIPE_CAP_CUBE_MAP_ARRAY:
 427    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 428       return true;
 429    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 430       return 1;
 431    case PIPE_CAP_TGSI_TEXCOORD:
 432       return false;
 433    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 434    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 435       return true;
 436    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 437       return 0;
 438    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 439       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 440       return 1 << 27;
 441    case PIPE_CAP_MAX_VIEWPORTS:
 442       return ILO_MAX_VIEWPORTS;
 443    case PIPE_CAP_ENDIANNESS:
 444       return PIPE_ENDIAN_LITTLE;
 445    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 446       return true;
 447    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 448    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 449    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 450    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 451    case PIPE_CAP_TEXTURE_GATHER_SM5:
 452       return 0;
 453    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 454    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 455    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 456       return true;
 457    case PIPE_CAP_FAKE_SW_MSAA:
 458    case PIPE_CAP_TEXTURE_QUERY_LOD:
 459    case PIPE_CAP_SAMPLE_SHADING:
 460    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 461    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 462    case PIPE_CAP_MAX_VERTEX_STREAMS:
 463    case PIPE_CAP_DRAW_INDIRECT:
 464    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 465    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 466    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 467    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 468    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 469    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 470    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 471       return 0;
 472
 473    case PIPE_CAP_VENDOR_ID:
 474       return 0x8086;
 475    case PIPE_CAP_DEVICE_ID:
 476       return is->dev.devid;
 477    case PIPE_CAP_ACCELERATED:
 478       return true;
 479    case PIPE_CAP_VIDEO_MEMORY: {
 480       /* Once a batch uses more than 75% of the maximum mappable size, we
 481        * assume that there's some fragmentation, and we start doing extra
 482        * flushing, etc.  That's the big cliff apps will care about.
 483        */
 484       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 485       uint64_t system_memory;
 486
 487       if (!os_get_total_physical_memory(&system_memory))
 488          return 0;
 489
 490       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 491    }
 492    case PIPE_CAP_UMA:
 493       return true;
 494    case PIPE_CAP_CLIP_HALFZ:
 495       return true;
 496    case PIPE_CAP_VERTEXID_NOBASE:
 497       return false;
 498    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 499       return true;
 500
 501    default:
 502       return 0;
 503    }
 504 }
 505
 506 static const char *
 507 ilo_get_vendor(struct pipe_screen *screen)
 508 {
 509    return "LunarG, Inc.";
 510 }
 511
 512 static const char *
 513 ilo_get_device_vendor(struct pipe_screen *screen)
 514 {
 515    return "Intel";
 516 }
 517
 518 static const char *
 519 ilo_get_name(struct pipe_screen *screen)
 520 {
 521    struct ilo_screen *is = ilo_screen(screen);
 522    const char *chipset = NULL;
 523
 524    if (gen_is_chv(is->dev.devid)) {
 525       chipset = "Intel(R) Cherryview";
 526    } else if (gen_is_bdw(is->dev.devid)) {
 527       /* this is likely wrong */
 528       if (gen_is_desktop(is->dev.devid))
 529          chipset = "Intel(R) Broadwell Desktop";
 530       else if (gen_is_mobile(is->dev.devid))
 531          chipset = "Intel(R) Broadwell Mobile";
 532       else if (gen_is_server(is->dev.devid))
 533          chipset = "Intel(R) Broadwell Server";
 534    } else if (gen_is_vlv(is->dev.devid)) {
 535       chipset = "Intel(R) Bay Trail";
 536    } else if (gen_is_hsw(is->dev.devid)) {
 537       if (gen_is_desktop(is->dev.devid))
 538          chipset = "Intel(R) Haswell Desktop";
 539       else if (gen_is_mobile(is->dev.devid))
 540          chipset = "Intel(R) Haswell Mobile";
 541       else if (gen_is_server(is->dev.devid))
 542          chipset = "Intel(R) Haswell Server";
 543    } else if (gen_is_ivb(is->dev.devid)) {
 544       if (gen_is_desktop(is->dev.devid))
 545          chipset = "Intel(R) Ivybridge Desktop";
 546       else if (gen_is_mobile(is->dev.devid))
 547          chipset = "Intel(R) Ivybridge Mobile";
 548       else if (gen_is_server(is->dev.devid))
 549          chipset = "Intel(R) Ivybridge Server";
 550    } else if (gen_is_snb(is->dev.devid)) {
 551       if (gen_is_desktop(is->dev.devid))
 552          chipset = "Intel(R) Sandybridge Desktop";
 553       else if (gen_is_mobile(is->dev.devid))
 554          chipset = "Intel(R) Sandybridge Mobile";
 555       else if (gen_is_server(is->dev.devid))
 556          chipset = "Intel(R) Sandybridge Server";
 557    }
 558
 559    if (!chipset)
 560       chipset = "Unknown Intel Chipset";
 561
 562    return chipset;
 563 }
 564
 565 static uint64_t
 566 ilo_get_timestamp(struct pipe_screen *screen)
 567 {
 568    struct ilo_screen *is = ilo_screen(screen);
 569    union {
 570       uint64_t val;
 571       uint32_t dw[2];
 572    } timestamp;
 573
 574    intel_winsys_read_reg(is->dev.winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 575
 576    /*
 577     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 578     *
 579     *     "Note: This timestamp register reflects the value of the PCU TSC.
 580     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 581     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 582     *      hours)."
 583     *
 584     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 585     * of the timestamp.  We will have to live with a timestamp that rolls over
 586     * every ~343 seconds.
 587     *
 588     * See also brw_get_timestamp().
 589     */
 590    return (uint64_t) timestamp.dw[1] * 80;
 591 }
 592
 593 static boolean
 594 ilo_is_format_supported(struct pipe_screen *screen,
 595                         enum pipe_format format,
 596                         enum pipe_texture_target target,
 597                         unsigned sample_count,
 598                         unsigned bindings)
 599 {
 600    struct ilo_screen *is = ilo_screen(screen);
 601    const struct ilo_dev *dev = &is->dev;
 602
 603    if (!util_format_is_supported(format, bindings))
 604       return false;
 605
 606    /* no MSAA support yet */
 607    if (sample_count > 1)
 608       return false;
 609
 610    if ((bindings & PIPE_BIND_DEPTH_STENCIL) &&
 611        !ilo_format_support_zs(dev, format))
 612       return false;
 613
 614    if ((bindings & PIPE_BIND_RENDER_TARGET) &&
 615        !ilo_format_support_rt(dev, format))
 616       return false;
 617
 618    if ((bindings & PIPE_BIND_SAMPLER_VIEW) &&
 619        !ilo_format_support_sampler(dev, format))
 620       return false;
 621
 622    if ((bindings & PIPE_BIND_VERTEX_BUFFER) &&
 623        !ilo_format_support_vb(dev, format))
 624       return false;
 625
 626    return true;
 627 }
 628
 629 static boolean
 630 ilo_is_video_format_supported(struct pipe_screen *screen,
 631                               enum pipe_format format,
 632                               enum pipe_video_profile profile,
 633                               enum pipe_video_entrypoint entrypoint)
 634 {
 635    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 636 }
 637
 638 static void
 639 ilo_screen_fence_reference(struct pipe_screen *screen,
 640                            struct pipe_fence_handle **ptr,
 641                            struct pipe_fence_handle *fence)
 642 {
 643    struct pipe_fence_handle *old;
 644
 645    if (likely(ptr)) {
 646       old = *ptr;
 647       *ptr = fence;
 648    } else {
 649       old = NULL;
 650    }
 651
 652    STATIC_ASSERT(&((struct pipe_fence_handle *) NULL)->reference == NULL);
 653    if (pipe_reference(&old->reference, &fence->reference)) {
 654       intel_bo_unref(old->seqno_bo);
 655       FREE(old);
 656    }
 657 }
 658
 659 static boolean
 660 ilo_screen_fence_finish(struct pipe_screen *screen,
 661                         struct pipe_fence_handle *fence,
 662                         uint64_t timeout)
 663 {
 664    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 665    bool signaled;
 666
 667    signaled = (!fence->seqno_bo ||
 668          intel_bo_wait(fence->seqno_bo, wait_timeout) == 0);
 669
 670    /* XXX not thread safe */
 671    if (signaled && fence->seqno_bo) {
 672       intel_bo_unref(fence->seqno_bo);
 673       fence->seqno_bo = NULL;
 674    }
 675
 676    return signaled;
 677 }
 678
 679 /**
 680  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 681  * before waited on or checked.
 682  */
 683 struct pipe_fence_handle *
 684 ilo_screen_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 685 {
 686    struct pipe_fence_handle *fence;
 687
 688    fence = CALLOC_STRUCT(pipe_fence_handle);
 689    if (!fence)
 690       return NULL;
 691
 692    pipe_reference_init(&fence->reference, 1);
 693
 694    fence->seqno_bo = intel_bo_ref(bo);
 695
 696    return fence;
 697 }
 698
 699 static void
 700 ilo_screen_destroy(struct pipe_screen *screen)
 701 {
 702    struct ilo_screen *is = ilo_screen(screen);
 703
 704    intel_winsys_destroy(is->dev.winsys);
 705
 706    FREE(is);
 707 }
 708
 709 struct pipe_screen *
 710 ilo_screen_create(struct intel_winsys *ws)
 711 {
 712    struct ilo_screen *is;
 713
 714    ilo_debug_init("ILO_DEBUG");
 715
 716    is = CALLOC_STRUCT(ilo_screen);
 717    if (!is)
 718       return NULL;
 719
 720    if (!ilo_dev_init(&is->dev, ws)) {
 721       FREE(is);
 722       return NULL;
 723    }
 724
 725    util_format_s3tc_init();
 726
 727    is->base.destroy = ilo_screen_destroy;
 728    is->base.get_name = ilo_get_name;
 729    is->base.get_vendor = ilo_get_vendor;
 730    is->base.get_device_vendor = ilo_get_device_vendor;
 731    is->base.get_param = ilo_get_param;
 732    is->base.get_paramf = ilo_get_paramf;
 733    is->base.get_shader_param = ilo_get_shader_param;
 734    is->base.get_video_param = ilo_get_video_param;
 735    is->base.get_compute_param = ilo_get_compute_param;
 736
 737    is->base.get_timestamp = ilo_get_timestamp;
 738
 739    is->base.is_format_supported = ilo_is_format_supported;
 740    is->base.is_video_format_supported = ilo_is_video_format_supported;
 741
 742    is->base.flush_frontbuffer = NULL;
 743
 744    is->base.fence_reference = ilo_screen_fence_reference;
 745    is->base.fence_finish = ilo_screen_fence_finish;
 746
 747    is->base.get_driver_query_info = NULL;
 748
 749    ilo_init_context_functions(is);
 750    ilo_init_resource_functions(is);
 751
 752    return &is->base;
 753 }