src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "intel_winsys.h"
  35
  36 #include "ilo_context.h"
  37 #include "ilo_format.h"
  38 #include "ilo_resource.h"
  39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  40 #include "ilo_public.h"
  41 #include "ilo_screen.h"
  42
  43 struct ilo_fence {
  44    struct pipe_reference reference;
  45    struct intel_bo *bo;
  46 };
  47
  48 int ilo_debug;
  49
  50 static const struct debug_named_value ilo_debug_flags[] = {
  51    { "batch",     ILO_DEBUG_BATCH,    "Dump batch/state/surface/instruction buffers" },
  52    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  53    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  54    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  55    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  56    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  57    { "submit",    ILO_DEBUG_SUBMIT,   "Show batch buffer submissions" },
  58    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  59    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  60    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  61    DEBUG_NAMED_VALUE_END
  62 };
  63
  64 static float
  65 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  66 {
  67    switch (param) {
  68    case PIPE_CAPF_MAX_LINE_WIDTH:
  69       /* in U3.7, defined in 3DSTATE_SF */
  70       return 7.0f;
  71    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  72       /* line width minus one, which is reserved for AA region */
  73       return 6.0f;
  74    case PIPE_CAPF_MAX_POINT_WIDTH:
  75       /* in U8.3, defined in 3DSTATE_SF */
  76       return 255.0f;
  77    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  78       /* same as point width, as we ignore rasterizer->point_smooth */
  79       return 255.0f;
  80    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  81       /* [2.0, 16.0], defined in SAMPLER_STATE */
  82       return 16.0f;
  83    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  84       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  85       return 15.0f;
  86    case PIPE_CAPF_GUARD_BAND_LEFT:
  87    case PIPE_CAPF_GUARD_BAND_TOP:
  88    case PIPE_CAPF_GUARD_BAND_RIGHT:
  89    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  90       /* what are these for? */
  91       return 0.0f;
  92
  93    default:
  94       return 0.0f;
  95    }
  96 }
  97
  98 static int
  99 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
 100                      enum pipe_shader_cap param)
 101 {
 102    switch (shader) {
 103    case PIPE_SHADER_FRAGMENT:
 104    case PIPE_SHADER_VERTEX:
 105    case PIPE_SHADER_GEOMETRY:
 106       break;
 107    default:
 108       return 0;
 109    }
 110
 111    switch (param) {
 112    /* the limits are copied from the classic driver */
 113    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 114       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 115    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 116       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 117    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 118       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 119    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 120       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 121    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 122       return UINT_MAX;
 123    case PIPE_SHADER_CAP_MAX_INPUTS:
 124    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 125       /* this is limited by how many attributes SF can remap */
 126       return 16;
 127    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 128       return 1024 * sizeof(float[4]);
 129    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 130       return ILO_MAX_CONST_BUFFERS;
 131    case PIPE_SHADER_CAP_MAX_TEMPS:
 132       return 256;
 133    case PIPE_SHADER_CAP_MAX_PREDS:
 134       return 0;
 135    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 136       return 1;
 137    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 138       return 0;
 139    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 140       return 0;
 141    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 142       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 143    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 144       return 1;
 145    case PIPE_SHADER_CAP_SUBROUTINES:
 146       return 0;
 147    case PIPE_SHADER_CAP_INTEGERS:
 148       return 1;
 149    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 150       return ILO_MAX_SAMPLERS;
 151    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 152       return ILO_MAX_SAMPLER_VIEWS;
 153    case PIPE_SHADER_CAP_PREFERRED_IR:
 154       return PIPE_SHADER_IR_TGSI;
 155    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 156       return 1;
 157
 158    default:
 159       return 0;
 160    }
 161 }
 162
 163 static int
 164 ilo_get_video_param(struct pipe_screen *screen,
 165                     enum pipe_video_profile profile,
 166                     enum pipe_video_entrypoint entrypoint,
 167                     enum pipe_video_cap param)
 168 {
 169    switch (param) {
 170    case PIPE_VIDEO_CAP_SUPPORTED:
 171       return vl_profile_supported(screen, profile, entrypoint);
 172    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 173       return 1;
 174    case PIPE_VIDEO_CAP_MAX_WIDTH:
 175    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 176       return vl_video_buffer_max_size(screen);
 177    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 178       return PIPE_FORMAT_NV12;
 179    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 180       return 1;
 181    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 182       return 1;
 183    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 184       return 0;
 185    case PIPE_VIDEO_CAP_MAX_LEVEL:
 186       return vl_level_supported(screen, profile);
 187    default:
 188       return 0;
 189    }
 190 }
 191
 192 static int
 193 ilo_get_compute_param(struct pipe_screen *screen,
 194                       enum pipe_compute_cap param,
 195                       void *ret)
 196 {
 197    union {
 198       const char *ir_target;
 199       uint64_t grid_dimension;
 200       uint64_t max_grid_size[3];
 201       uint64_t max_block_size[3];
 202       uint64_t max_threads_per_block;
 203       uint64_t max_global_size;
 204       uint64_t max_local_size;
 205       uint64_t max_private_size;
 206       uint64_t max_input_size;
 207       uint64_t max_mem_alloc_size;
 208    } val;
 209    const void *ptr;
 210    int size;
 211
 212    /* XXX some randomly chosen values */
 213    switch (param) {
 214    case PIPE_COMPUTE_CAP_IR_TARGET:
 215       val.ir_target = "ilog";
 216
 217       ptr = val.ir_target;
 218       size = strlen(val.ir_target) + 1;
 219       break;
 220    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 221       val.grid_dimension = Elements(val.max_grid_size);
 222
 223       ptr = &val.grid_dimension;
 224       size = sizeof(val.grid_dimension);
 225       break;
 226    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 227       val.max_grid_size[0] = 65535;
 228       val.max_grid_size[1] = 65535;
 229       val.max_grid_size[2] = 1;
 230
 231       ptr = &val.max_grid_size;
 232       size = sizeof(val.max_grid_size);
 233       break;
 234    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 235       val.max_block_size[0] = 512;
 236       val.max_block_size[1] = 512;
 237       val.max_block_size[2] = 512;
 238
 239       ptr = &val.max_block_size;
 240       size = sizeof(val.max_block_size);
 241       break;
 242
 243    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 244       val.max_threads_per_block = 512;
 245
 246       ptr = &val.max_threads_per_block;
 247       size = sizeof(val.max_threads_per_block);
 248       break;
 249    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 250       val.max_global_size = 4;
 251
 252       ptr = &val.max_global_size;
 253       size = sizeof(val.max_global_size);
 254       break;
 255    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 256       val.max_local_size = 64 * 1024;
 257
 258       ptr = &val.max_local_size;
 259       size = sizeof(val.max_local_size);
 260       break;
 261    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 262       val.max_private_size = 32768;
 263
 264       ptr = &val.max_private_size;
 265       size = sizeof(val.max_private_size);
 266       break;
 267    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 268       val.max_input_size = 256;
 269
 270       ptr = &val.max_input_size;
 271       size = sizeof(val.max_input_size);
 272       break;
 273    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 274       val.max_mem_alloc_size = 128 * 1024 * 1024;
 275
 276       ptr = &val.max_mem_alloc_size;
 277       size = sizeof(val.max_mem_alloc_size);
 278       break;
 279    default:
 280       ptr = NULL;
 281       size = 0;
 282       break;
 283    }
 284
 285    if (ret)
 286       memcpy(ret, ptr, size);
 287
 288    return size;
 289 }
 290
 291 static int
 292 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 293 {
 294    struct ilo_screen *is = ilo_screen(screen);
 295
 296    switch (param) {
 297    case PIPE_CAP_NPOT_TEXTURES:
 298    case PIPE_CAP_TWO_SIDED_STENCIL:
 299       return true;
 300    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 301       return 0; /* TODO */
 302    case PIPE_CAP_ANISOTROPIC_FILTER:
 303    case PIPE_CAP_POINT_SPRITE:
 304       return true;
 305    case PIPE_CAP_MAX_RENDER_TARGETS:
 306       return ILO_MAX_DRAW_BUFFERS;
 307    case PIPE_CAP_OCCLUSION_QUERY:
 308    case PIPE_CAP_QUERY_TIME_ELAPSED:
 309    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 310    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 311       return true;
 312    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 313       /*
 314        * As defined in SURFACE_STATE, we have
 315        *
 316        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 317        *  GEN6           8192x8192x512            2048x2048x2048
 318        *  GEN7         16384x16384x2048           2048x2048x2048
 319        */
 320       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 321    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 322       return 12;
 323    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 324       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 325    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 326       return false;
 327    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 328    case PIPE_CAP_SM3:
 329       return true;
 330    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 331       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 332          return 0;
 333       return ILO_MAX_SO_BUFFERS;
 334    case PIPE_CAP_PRIMITIVE_RESTART:
 335       return true;
 336    case PIPE_CAP_INDEP_BLEND_ENABLE:
 337    case PIPE_CAP_INDEP_BLEND_FUNC:
 338       return true;
 339    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 340       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
 341    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 342    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 343    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 344    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 345    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 346       return true;
 347    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 348       return false;
 349    case PIPE_CAP_TGSI_INSTANCEID:
 350    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 351       return true;
 352    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 353       return false;
 354    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 355       return true;
 356    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 357    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 358       return true;
 359    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 360    case PIPE_CAP_MIN_TEXEL_OFFSET:
 361       return -8;
 362    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 363    case PIPE_CAP_MAX_TEXEL_OFFSET:
 364       return 7;
 365    case PIPE_CAP_CONDITIONAL_RENDER:
 366    case PIPE_CAP_TEXTURE_BARRIER:
 367       return true;
 368    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 369       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 370    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 371       return ILO_MAX_SO_BINDINGS;
 372    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 373       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 374          return is->dev.has_gen7_sol_reset;
 375       else
 376          return false; /* TODO */
 377    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 378       return false;
 379    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 380       return true;
 381    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 382       return false;
 383    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 384       return 140;
 385    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 386    case PIPE_CAP_USER_VERTEX_BUFFERS:
 387       return false;
 388    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 389    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 390    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 391       return false;
 392    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 393       return 2048;
 394    case PIPE_CAP_COMPUTE:
 395       return false; /* TODO */
 396    case PIPE_CAP_USER_INDEX_BUFFERS:
 397    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 398       return true;
 399    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 400       /* imposed by OWord (Dual) Block Read */
 401       return 16;
 402    case PIPE_CAP_START_INSTANCE:
 403       return true;
 404    case PIPE_CAP_QUERY_TIMESTAMP:
 405       return is->dev.has_timestamp;
 406    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 407       return false; /* TODO */
 408    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 409       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 410    case PIPE_CAP_CUBE_MAP_ARRAY:
 411    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 412       return true;
 413    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 414       return 1;
 415    case PIPE_CAP_TGSI_TEXCOORD:
 416       return false;
 417    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 418    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 419       return true;
 420    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 421       return 0;
 422    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 423       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 424       return 1 << 27;
 425    case PIPE_CAP_MAX_VIEWPORTS:
 426       return ILO_MAX_VIEWPORTS;
 427    case PIPE_CAP_ENDIANNESS:
 428       return PIPE_ENDIAN_LITTLE;
 429    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 430       return true;
 431    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 432    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 433    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 434    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 435    case PIPE_CAP_TEXTURE_GATHER_SM5:
 436       return 0;
 437    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 438       return true;
 439    case PIPE_CAP_FAKE_SW_MSAA:
 440    case PIPE_CAP_TEXTURE_QUERY_LOD:
 441    case PIPE_CAP_SAMPLE_SHADING:
 442    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 443    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 444    case PIPE_CAP_MAX_VERTEX_STREAMS:
 445    case PIPE_CAP_DRAW_INDIRECT:
 446    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 447    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 448    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 449       return 0;
 450
 451    case PIPE_CAP_VENDOR_ID:
 452       return 0x8086;
 453    case PIPE_CAP_DEVICE_ID:
 454       return is->dev.devid;
 455    case PIPE_CAP_ACCELERATED:
 456       return true;
 457    case PIPE_CAP_VIDEO_MEMORY: {
 458       /* Once a batch uses more than 75% of the maximum mappable size, we
 459        * assume that there's some fragmentation, and we start doing extra
 460        * flushing, etc.  That's the big cliff apps will care about.
 461        */
 462       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 463       uint64_t system_memory;
 464
 465       if (!os_get_total_physical_memory(&system_memory))
 466          return 0;
 467
 468       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 469    }
 470    case PIPE_CAP_UMA:
 471       return true;
 472    case PIPE_CAP_CLIP_HALFZ:
 473       return true;
 474
 475    default:
 476       return 0;
 477    }
 478 }
 479
 480 static const char *
 481 ilo_get_vendor(struct pipe_screen *screen)
 482 {
 483    return "LunarG, Inc.";
 484 }
 485
 486 static const char *
 487 ilo_get_name(struct pipe_screen *screen)
 488 {
 489    struct ilo_screen *is = ilo_screen(screen);
 490    const char *chipset = NULL;
 491
 492    if (gen_is_vlv(is->dev.devid)) {
 493       chipset = "Intel(R) Bay Trail";
 494    }
 495    else if (gen_is_hsw(is->dev.devid)) {
 496       if (gen_is_desktop(is->dev.devid))
 497          chipset = "Intel(R) Haswell Desktop";
 498       else if (gen_is_mobile(is->dev.devid))
 499          chipset = "Intel(R) Haswell Mobile";
 500       else if (gen_is_server(is->dev.devid))
 501          chipset = "Intel(R) Haswell Server";
 502    }
 503    else if (gen_is_ivb(is->dev.devid)) {
 504       if (gen_is_desktop(is->dev.devid))
 505          chipset = "Intel(R) Ivybridge Desktop";
 506       else if (gen_is_mobile(is->dev.devid))
 507          chipset = "Intel(R) Ivybridge Mobile";
 508       else if (gen_is_server(is->dev.devid))
 509          chipset = "Intel(R) Ivybridge Server";
 510    }
 511    else if (gen_is_snb(is->dev.devid)) {
 512       if (gen_is_desktop(is->dev.devid))
 513          chipset = "Intel(R) Sandybridge Desktop";
 514       else if (gen_is_mobile(is->dev.devid))
 515          chipset = "Intel(R) Sandybridge Mobile";
 516       else if (gen_is_server(is->dev.devid))
 517          chipset = "Intel(R) Sandybridge Server";
 518    }
 519
 520    if (!chipset)
 521       chipset = "Unknown Intel Chipset";
 522
 523    return chipset;
 524 }
 525
 526 static uint64_t
 527 ilo_get_timestamp(struct pipe_screen *screen)
 528 {
 529    struct ilo_screen *is = ilo_screen(screen);
 530    union {
 531       uint64_t val;
 532       uint32_t dw[2];
 533    } timestamp;
 534
 535    intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 536
 537    /*
 538     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 539     *
 540     *     "Note: This timestamp register reflects the value of the PCU TSC.
 541     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 542     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 543     *      hours)."
 544     *
 545     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 546     * of the timestamp.  We will have to live with a timestamp that rolls over
 547     * every ~343 seconds.
 548     *
 549     * See also brw_get_timestamp().
 550     */
 551    return (uint64_t) timestamp.dw[1] * 80;
 552 }
 553
 554 static void
 555 ilo_fence_reference(struct pipe_screen *screen,
 556                     struct pipe_fence_handle **p,
 557                     struct pipe_fence_handle *f)
 558 {
 559    struct ilo_fence *fence = ilo_fence(f);
 560    struct ilo_fence *old;
 561
 562    if (likely(p)) {
 563       old = ilo_fence(*p);
 564       *p = f;
 565    }
 566    else {
 567       old = NULL;
 568    }
 569
 570    STATIC_ASSERT(&((struct ilo_fence *) NULL)->reference == NULL);
 571    if (pipe_reference(&old->reference, &fence->reference)) {
 572       if (old->bo)
 573          intel_bo_unreference(old->bo);
 574       FREE(old);
 575    }
 576 }
 577
 578 static boolean
 579 ilo_fence_signalled(struct pipe_screen *screen,
 580                     struct pipe_fence_handle *f)
 581 {
 582    struct ilo_fence *fence = ilo_fence(f);
 583
 584    /* mark signalled if the bo is idle */
 585    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 586       intel_bo_unreference(fence->bo);
 587       fence->bo = NULL;
 588    }
 589
 590    return (fence->bo == NULL);
 591 }
 592
 593 static boolean
 594 ilo_fence_finish(struct pipe_screen *screen,
 595                  struct pipe_fence_handle *f,
 596                  uint64_t timeout)
 597 {
 598    struct ilo_fence *fence = ilo_fence(f);
 599    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 600
 601    /* already signalled */
 602    if (!fence->bo)
 603       return true;
 604
 605    /* wait and see if it returns error */
 606    if (intel_bo_wait(fence->bo, wait_timeout))
 607       return false;
 608
 609    /* mark signalled */
 610    intel_bo_unreference(fence->bo);
 611    fence->bo = NULL;
 612
 613    return true;
 614 }
 615
 616 /**
 617  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 618  * before waited on or checked.
 619  */
 620 struct ilo_fence *
 621 ilo_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 622 {
 623    struct ilo_fence *fence;
 624
 625    fence = CALLOC_STRUCT(ilo_fence);
 626    if (!fence)
 627       return NULL;
 628
 629    pipe_reference_init(&fence->reference, 1);
 630
 631    if (bo)
 632       intel_bo_reference(bo);
 633    fence->bo = bo;
 634
 635    return fence;
 636 }
 637
 638 static void
 639 ilo_screen_destroy(struct pipe_screen *screen)
 640 {
 641    struct ilo_screen *is = ilo_screen(screen);
 642
 643    /* as it seems, winsys is owned by the screen */
 644    intel_winsys_destroy(is->winsys);
 645
 646    FREE(is);
 647 }
 648
 649 static bool
 650 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 651 {
 652    dev->devid = info->devid;
 653    dev->aperture_total = info->aperture_total;
 654    dev->aperture_mappable = info->aperture_mappable;
 655    dev->has_llc = info->has_llc;
 656    dev->has_address_swizzling = info->has_address_swizzling;
 657    dev->has_logical_context = info->has_logical_context;
 658    dev->has_ppgtt = info->has_ppgtt;
 659    dev->has_timestamp = info->has_timestamp;
 660    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 661
 662    if (!dev->has_logical_context) {
 663       ilo_err("missing hardware logical context support\n");
 664       return false;
 665    }
 666
 667    /*
 668     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 669     * writes on GEN6.
 670     *
 671     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 672     *
 673     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 674     *      code is in a secure environment, independent of address space.
 675     *      Under this condition, this bit only specifies the address space
 676     *      (GGTT or PPGTT). All commands are executed "as-is""
 677     *
 678     * We need PPGTT to be enabled on GEN6 too.
 679     */
 680    if (!dev->has_ppgtt) {
 681       /* experiments show that it does not really matter... */
 682       ilo_warn("PPGTT disabled\n");
 683    }
 684
 685    /*
 686     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 687     *
 688     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 689     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 690     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 691     *      to an EU GRF register. Read/write access to the URB is generally
 692     *      supported on a row-granular basis."
 693     *
 694     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 695     *
 696     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 697     *      128k        4096        2048
 698     *      256k        8096        4096"
 699     */
 700
 701    if (gen_is_hsw(info->devid)) {
 702       dev->gen_opaque = ILO_GEN(7.5);
 703       dev->gt = gen_get_hsw_gt(info->devid);
 704       dev->urb_size = ((dev->gt == 3) ? 512 :
 705                        (dev->gt == 2) ? 256 : 128) * 1024;
 706    }
 707    else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 708       dev->gen_opaque = ILO_GEN(7);
 709       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 710       dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
 711    }
 712    else if (gen_is_snb(info->devid)) {
 713       dev->gen_opaque = ILO_GEN(6);
 714       dev->gt = gen_get_snb_gt(info->devid);
 715       dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
 716    }
 717    else {
 718       ilo_err("unknown GPU generation\n");
 719       return false;
 720    }
 721
 722    return true;
 723 }
 724
 725 struct pipe_screen *
 726 ilo_screen_create(struct intel_winsys *ws)
 727 {
 728    struct ilo_screen *is;
 729    const struct intel_winsys_info *info;
 730
 731    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 732
 733    is = CALLOC_STRUCT(ilo_screen);
 734    if (!is)
 735       return NULL;
 736
 737    is->winsys = ws;
 738
 739    info = intel_winsys_get_info(is->winsys);
 740    if (!init_dev(&is->dev, info)) {
 741       FREE(is);
 742       return NULL;
 743    }
 744
 745    util_format_s3tc_init();
 746
 747    is->base.destroy = ilo_screen_destroy;
 748    is->base.get_name = ilo_get_name;
 749    is->base.get_vendor = ilo_get_vendor;
 750    is->base.get_param = ilo_get_param;
 751    is->base.get_paramf = ilo_get_paramf;
 752    is->base.get_shader_param = ilo_get_shader_param;
 753    is->base.get_video_param = ilo_get_video_param;
 754    is->base.get_compute_param = ilo_get_compute_param;
 755
 756    is->base.get_timestamp = ilo_get_timestamp;
 757
 758    is->base.flush_frontbuffer = NULL;
 759
 760    is->base.fence_reference = ilo_fence_reference;
 761    is->base.fence_signalled = ilo_fence_signalled;
 762    is->base.fence_finish = ilo_fence_finish;
 763
 764    is->base.get_driver_query_info = NULL;
 765
 766    ilo_init_format_functions(is);
 767    ilo_init_context_functions(is);
 768    ilo_init_resource_functions(is);
 769
 770    return &is->base;
 771 }