2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "pipe/p_state.h"
29 #include "os/os_misc.h"
30 #include "util/u_format_s3tc.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
34 #include "core/intel_winsys.h"
36 #include "ilo_context.h"
37 #include "ilo_format.h"
38 #include "ilo_resource.h"
39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
40 #include "ilo_public.h"
41 #include "ilo_screen.h"
43 struct pipe_fence_handle
{
44 struct pipe_reference reference
;
45 struct intel_bo
*seqno_bo
;
49 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
52 case PIPE_CAPF_MAX_LINE_WIDTH
:
53 /* in U3.7, defined in 3DSTATE_SF */
55 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
56 /* line width minus one, which is reserved for AA region */
58 case PIPE_CAPF_MAX_POINT_WIDTH
:
59 /* in U8.3, defined in 3DSTATE_SF */
61 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
62 /* same as point width, as we ignore rasterizer->point_smooth */
64 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
65 /* [2.0, 16.0], defined in SAMPLER_STATE */
67 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
68 /* [-16.0, 16.0), defined in SAMPLER_STATE */
70 case PIPE_CAPF_GUARD_BAND_LEFT
:
71 case PIPE_CAPF_GUARD_BAND_TOP
:
72 case PIPE_CAPF_GUARD_BAND_RIGHT
:
73 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
74 /* what are these for? */
83 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
84 enum pipe_shader_cap param
)
87 case PIPE_SHADER_FRAGMENT
:
88 case PIPE_SHADER_VERTEX
:
89 case PIPE_SHADER_GEOMETRY
:
96 /* the limits are copied from the classic driver */
97 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
98 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
99 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
100 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
101 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
102 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
103 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
104 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
105 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
107 case PIPE_SHADER_CAP_MAX_INPUTS
:
108 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
109 /* this is limited by how many attributes SF can remap */
111 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
112 return 1024 * sizeof(float[4]);
113 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
114 return ILO_MAX_CONST_BUFFERS
;
115 case PIPE_SHADER_CAP_MAX_TEMPS
:
117 case PIPE_SHADER_CAP_MAX_PREDS
:
119 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
121 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
123 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
125 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
126 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
127 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
129 case PIPE_SHADER_CAP_SUBROUTINES
:
131 case PIPE_SHADER_CAP_INTEGERS
:
133 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
134 return ILO_MAX_SAMPLERS
;
135 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
136 return ILO_MAX_SAMPLER_VIEWS
;
137 case PIPE_SHADER_CAP_PREFERRED_IR
:
138 return PIPE_SHADER_IR_TGSI
;
139 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
148 ilo_get_video_param(struct pipe_screen
*screen
,
149 enum pipe_video_profile profile
,
150 enum pipe_video_entrypoint entrypoint
,
151 enum pipe_video_cap param
)
154 case PIPE_VIDEO_CAP_SUPPORTED
:
155 return vl_profile_supported(screen
, profile
, entrypoint
);
156 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
158 case PIPE_VIDEO_CAP_MAX_WIDTH
:
159 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
160 return vl_video_buffer_max_size(screen
);
161 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
162 return PIPE_FORMAT_NV12
;
163 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
165 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
167 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
169 case PIPE_VIDEO_CAP_MAX_LEVEL
:
170 return vl_level_supported(screen
, profile
);
177 ilo_get_compute_param(struct pipe_screen
*screen
,
178 enum pipe_compute_cap param
,
181 struct ilo_screen
*is
= ilo_screen(screen
);
183 const char *ir_target
;
184 uint64_t grid_dimension
;
185 uint64_t max_grid_size
[3];
186 uint64_t max_block_size
[3];
187 uint64_t max_threads_per_block
;
188 uint64_t max_global_size
;
189 uint64_t max_local_size
;
190 uint64_t max_private_size
;
191 uint64_t max_input_size
;
192 uint64_t max_mem_alloc_size
;
193 uint32_t max_clock_frequency
;
194 uint32_t max_compute_units
;
195 uint32_t images_supported
;
196 uint32_t subgroup_size
;
202 case PIPE_COMPUTE_CAP_IR_TARGET
:
203 val
.ir_target
= "ilog";
206 size
= strlen(val
.ir_target
) + 1;
208 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
209 val
.grid_dimension
= Elements(val
.max_grid_size
);
211 ptr
= &val
.grid_dimension
;
212 size
= sizeof(val
.grid_dimension
);
214 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
215 val
.max_grid_size
[0] = 0xffffffffu
;
216 val
.max_grid_size
[1] = 0xffffffffu
;
217 val
.max_grid_size
[2] = 0xffffffffu
;
219 ptr
= &val
.max_grid_size
;
220 size
= sizeof(val
.max_grid_size
);
222 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
223 val
.max_block_size
[0] = 1024;
224 val
.max_block_size
[1] = 1024;
225 val
.max_block_size
[2] = 1024;
227 ptr
= &val
.max_block_size
;
228 size
= sizeof(val
.max_block_size
);
231 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
232 val
.max_threads_per_block
= 1024;
234 ptr
= &val
.max_threads_per_block
;
235 size
= sizeof(val
.max_threads_per_block
);
237 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
238 /* \see ilo_max_resource_size */
239 val
.max_global_size
= 1u << 31;
241 ptr
= &val
.max_global_size
;
242 size
= sizeof(val
.max_global_size
);
244 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
245 /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
246 val
.max_local_size
= 64 * 1024;
248 ptr
= &val
.max_local_size
;
249 size
= sizeof(val
.max_local_size
);
251 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
253 val
.max_private_size
= 12 * 1024;
255 ptr
= &val
.max_private_size
;
256 size
= sizeof(val
.max_private_size
);
258 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
259 val
.max_input_size
= 1024;
261 ptr
= &val
.max_input_size
;
262 size
= sizeof(val
.max_input_size
);
264 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
265 val
.max_mem_alloc_size
= 1u << 31;
267 ptr
= &val
.max_mem_alloc_size
;
268 size
= sizeof(val
.max_mem_alloc_size
);
270 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
271 val
.max_clock_frequency
= 1000;
273 ptr
= &val
.max_clock_frequency
;
274 size
= sizeof(val
.max_clock_frequency
);
276 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
277 val
.max_compute_units
= is
->dev
.eu_count
;
279 ptr
= &val
.max_compute_units
;
280 size
= sizeof(val
.max_compute_units
);
282 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
283 val
.images_supported
= 1;
285 ptr
= &val
.images_supported
;
286 size
= sizeof(val
.images_supported
);
288 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
289 /* best case is actually SIMD32 */
290 val
.subgroup_size
= 16;
292 ptr
= &val
.subgroup_size
;
293 size
= sizeof(val
.subgroup_size
);
302 memcpy(ret
, ptr
, size
);
308 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
310 struct ilo_screen
*is
= ilo_screen(screen
);
313 case PIPE_CAP_NPOT_TEXTURES
:
314 case PIPE_CAP_TWO_SIDED_STENCIL
:
316 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
318 case PIPE_CAP_ANISOTROPIC_FILTER
:
319 case PIPE_CAP_POINT_SPRITE
:
321 case PIPE_CAP_MAX_RENDER_TARGETS
:
322 return ILO_MAX_DRAW_BUFFERS
;
323 case PIPE_CAP_OCCLUSION_QUERY
:
324 case PIPE_CAP_QUERY_TIME_ELAPSED
:
325 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
326 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
328 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
330 * As defined in SURFACE_STATE, we have
332 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
333 * GEN6 8192x8192x512 2048x2048x2048
334 * GEN7 16384x16384x2048 2048x2048x2048
336 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
337 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
339 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
340 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
341 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
343 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
346 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
347 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
349 return ILO_MAX_SO_BUFFERS
;
350 case PIPE_CAP_PRIMITIVE_RESTART
:
352 case PIPE_CAP_INDEP_BLEND_ENABLE
:
353 case PIPE_CAP_INDEP_BLEND_FUNC
:
355 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
356 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7.5)) ? 2048 : 512;
357 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
358 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
359 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
360 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
361 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
363 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
365 case PIPE_CAP_TGSI_INSTANCEID
:
366 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
368 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
370 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
372 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
373 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
375 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
376 case PIPE_CAP_MIN_TEXEL_OFFSET
:
378 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
379 case PIPE_CAP_MAX_TEXEL_OFFSET
:
381 case PIPE_CAP_CONDITIONAL_RENDER
:
382 case PIPE_CAP_TEXTURE_BARRIER
:
384 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
385 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
386 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
387 return ILO_MAX_SO_BINDINGS
;
388 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
389 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7))
390 return is
->dev
.has_gen7_sol_reset
;
392 return false; /* TODO */
393 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
395 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
397 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
399 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
401 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
402 case PIPE_CAP_USER_VERTEX_BUFFERS
:
404 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
405 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
406 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
408 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
410 case PIPE_CAP_COMPUTE
:
411 return false; /* TODO */
412 case PIPE_CAP_USER_INDEX_BUFFERS
:
413 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
415 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
416 /* imposed by OWord (Dual) Block Read */
418 case PIPE_CAP_START_INSTANCE
:
420 case PIPE_CAP_QUERY_TIMESTAMP
:
421 return is
->dev
.has_timestamp
;
422 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
423 return false; /* TODO */
424 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
425 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
426 case PIPE_CAP_CUBE_MAP_ARRAY
:
427 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
429 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
431 case PIPE_CAP_TGSI_TEXCOORD
:
433 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
434 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
436 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
438 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
439 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
441 case PIPE_CAP_MAX_VIEWPORTS
:
442 return ILO_MAX_VIEWPORTS
;
443 case PIPE_CAP_ENDIANNESS
:
444 return PIPE_ENDIAN_LITTLE
;
445 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
447 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
448 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
449 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
450 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
451 case PIPE_CAP_TEXTURE_GATHER_SM5
:
453 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
455 case PIPE_CAP_FAKE_SW_MSAA
:
456 case PIPE_CAP_TEXTURE_QUERY_LOD
:
457 case PIPE_CAP_SAMPLE_SHADING
:
458 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
459 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
460 case PIPE_CAP_MAX_VERTEX_STREAMS
:
461 case PIPE_CAP_DRAW_INDIRECT
:
462 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
463 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
464 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
465 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
466 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
467 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
470 case PIPE_CAP_VENDOR_ID
:
472 case PIPE_CAP_DEVICE_ID
:
473 return is
->dev
.devid
;
474 case PIPE_CAP_ACCELERATED
:
476 case PIPE_CAP_VIDEO_MEMORY
: {
477 /* Once a batch uses more than 75% of the maximum mappable size, we
478 * assume that there's some fragmentation, and we start doing extra
479 * flushing, etc. That's the big cliff apps will care about.
481 const uint64_t gpu_memory
= is
->dev
.aperture_total
* 3 / 4;
482 uint64_t system_memory
;
484 if (!os_get_total_physical_memory(&system_memory
))
487 return (int) (MIN2(gpu_memory
, system_memory
) >> 20);
491 case PIPE_CAP_CLIP_HALFZ
:
493 case PIPE_CAP_VERTEXID_NOBASE
:
495 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
504 ilo_get_vendor(struct pipe_screen
*screen
)
506 return "LunarG, Inc.";
510 ilo_get_device_vendor(struct pipe_screen
*screen
)
516 ilo_get_name(struct pipe_screen
*screen
)
518 struct ilo_screen
*is
= ilo_screen(screen
);
519 const char *chipset
= NULL
;
521 if (gen_is_chv(is
->dev
.devid
)) {
522 chipset
= "Intel(R) Cherryview";
523 } else if (gen_is_bdw(is
->dev
.devid
)) {
524 /* this is likely wrong */
525 if (gen_is_desktop(is
->dev
.devid
))
526 chipset
= "Intel(R) Broadwell Desktop";
527 else if (gen_is_mobile(is
->dev
.devid
))
528 chipset
= "Intel(R) Broadwell Mobile";
529 else if (gen_is_server(is
->dev
.devid
))
530 chipset
= "Intel(R) Broadwell Server";
531 } else if (gen_is_vlv(is
->dev
.devid
)) {
532 chipset
= "Intel(R) Bay Trail";
533 } else if (gen_is_hsw(is
->dev
.devid
)) {
534 if (gen_is_desktop(is
->dev
.devid
))
535 chipset
= "Intel(R) Haswell Desktop";
536 else if (gen_is_mobile(is
->dev
.devid
))
537 chipset
= "Intel(R) Haswell Mobile";
538 else if (gen_is_server(is
->dev
.devid
))
539 chipset
= "Intel(R) Haswell Server";
540 } else if (gen_is_ivb(is
->dev
.devid
)) {
541 if (gen_is_desktop(is
->dev
.devid
))
542 chipset
= "Intel(R) Ivybridge Desktop";
543 else if (gen_is_mobile(is
->dev
.devid
))
544 chipset
= "Intel(R) Ivybridge Mobile";
545 else if (gen_is_server(is
->dev
.devid
))
546 chipset
= "Intel(R) Ivybridge Server";
547 } else if (gen_is_snb(is
->dev
.devid
)) {
548 if (gen_is_desktop(is
->dev
.devid
))
549 chipset
= "Intel(R) Sandybridge Desktop";
550 else if (gen_is_mobile(is
->dev
.devid
))
551 chipset
= "Intel(R) Sandybridge Mobile";
552 else if (gen_is_server(is
->dev
.devid
))
553 chipset
= "Intel(R) Sandybridge Server";
557 chipset
= "Unknown Intel Chipset";
563 ilo_get_timestamp(struct pipe_screen
*screen
)
565 struct ilo_screen
*is
= ilo_screen(screen
);
571 intel_winsys_read_reg(is
->dev
.winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
574 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
576 * "Note: This timestamp register reflects the value of the PCU TSC.
577 * The PCU TSC counts 10ns increments; this timestamp reflects bits
578 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
581 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
582 * of the timestamp. We will have to live with a timestamp that rolls over
583 * every ~343 seconds.
585 * See also brw_get_timestamp().
587 return (uint64_t) timestamp
.dw
[1] * 80;
591 ilo_is_format_supported(struct pipe_screen
*screen
,
592 enum pipe_format format
,
593 enum pipe_texture_target target
,
594 unsigned sample_count
,
597 struct ilo_screen
*is
= ilo_screen(screen
);
598 const struct ilo_dev
*dev
= &is
->dev
;
600 if (!util_format_is_supported(format
, bindings
))
603 /* no MSAA support yet */
604 if (sample_count
> 1)
607 if ((bindings
& PIPE_BIND_DEPTH_STENCIL
) &&
608 !ilo_format_support_zs(dev
, format
))
611 if ((bindings
& PIPE_BIND_RENDER_TARGET
) &&
612 !ilo_format_support_rt(dev
, format
))
615 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) &&
616 !ilo_format_support_sampler(dev
, format
))
619 if ((bindings
& PIPE_BIND_VERTEX_BUFFER
) &&
620 !ilo_format_support_vb(dev
, format
))
627 ilo_is_video_format_supported(struct pipe_screen
*screen
,
628 enum pipe_format format
,
629 enum pipe_video_profile profile
,
630 enum pipe_video_entrypoint entrypoint
)
632 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
636 ilo_screen_fence_reference(struct pipe_screen
*screen
,
637 struct pipe_fence_handle
**ptr
,
638 struct pipe_fence_handle
*fence
)
640 struct pipe_fence_handle
*old
;
649 STATIC_ASSERT(&((struct pipe_fence_handle
*) NULL
)->reference
== NULL
);
650 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
651 intel_bo_unref(old
->seqno_bo
);
657 ilo_screen_fence_finish(struct pipe_screen
*screen
,
658 struct pipe_fence_handle
*fence
,
661 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
664 signaled
= (!fence
->seqno_bo
||
665 intel_bo_wait(fence
->seqno_bo
, wait_timeout
) == 0);
667 /* XXX not thread safe */
668 if (signaled
&& fence
->seqno_bo
) {
669 intel_bo_unref(fence
->seqno_bo
);
670 fence
->seqno_bo
= NULL
;
677 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
678 * before waited on or checked.
680 struct pipe_fence_handle
*
681 ilo_screen_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
683 struct pipe_fence_handle
*fence
;
685 fence
= CALLOC_STRUCT(pipe_fence_handle
);
689 pipe_reference_init(&fence
->reference
, 1);
691 fence
->seqno_bo
= intel_bo_ref(bo
);
697 ilo_screen_destroy(struct pipe_screen
*screen
)
699 struct ilo_screen
*is
= ilo_screen(screen
);
701 intel_winsys_destroy(is
->dev
.winsys
);
707 ilo_screen_create(struct intel_winsys
*ws
)
709 struct ilo_screen
*is
;
711 ilo_debug_init("ILO_DEBUG");
713 is
= CALLOC_STRUCT(ilo_screen
);
717 if (!ilo_dev_init(&is
->dev
, ws
)) {
722 util_format_s3tc_init();
724 is
->base
.destroy
= ilo_screen_destroy
;
725 is
->base
.get_name
= ilo_get_name
;
726 is
->base
.get_vendor
= ilo_get_vendor
;
727 is
->base
.get_device_vendor
= ilo_get_device_vendor
;
728 is
->base
.get_param
= ilo_get_param
;
729 is
->base
.get_paramf
= ilo_get_paramf
;
730 is
->base
.get_shader_param
= ilo_get_shader_param
;
731 is
->base
.get_video_param
= ilo_get_video_param
;
732 is
->base
.get_compute_param
= ilo_get_compute_param
;
734 is
->base
.get_timestamp
= ilo_get_timestamp
;
736 is
->base
.is_format_supported
= ilo_is_format_supported
;
737 is
->base
.is_video_format_supported
= ilo_is_video_format_supported
;
739 is
->base
.flush_frontbuffer
= NULL
;
741 is
->base
.fence_reference
= ilo_screen_fence_reference
;
742 is
->base
.fence_finish
= ilo_screen_fence_finish
;
744 is
->base
.get_driver_query_info
= NULL
;
746 ilo_init_context_functions(is
);
747 ilo_init_resource_functions(is
);