2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "pipe/p_state.h"
29 #include "os/os_misc.h"
30 #include "util/u_format_s3tc.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
34 #include "intel_winsys.h"
36 #include "ilo_context.h"
37 #include "ilo_format.h"
38 #include "ilo_resource.h"
39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
40 #include "ilo_public.h"
41 #include "ilo_screen.h"
44 struct pipe_reference reference
;
50 static const struct debug_named_value ilo_debug_flags
[] = {
51 { "batch", ILO_DEBUG_BATCH
, "Dump batch/dynamic/surface/instruction buffers" },
52 { "vs", ILO_DEBUG_VS
, "Dump vertex shaders" },
53 { "gs", ILO_DEBUG_GS
, "Dump geometry shaders" },
54 { "fs", ILO_DEBUG_FS
, "Dump fragment shaders" },
55 { "cs", ILO_DEBUG_CS
, "Dump compute shaders" },
56 { "draw", ILO_DEBUG_DRAW
, "Show draw information" },
57 { "submit", ILO_DEBUG_SUBMIT
, "Show batch buffer submissions" },
58 { "hang", ILO_DEBUG_HANG
, "Detect GPU hangs" },
59 { "nohw", ILO_DEBUG_NOHW
, "Do not send commands to HW" },
60 { "nocache", ILO_DEBUG_NOCACHE
, "Always invalidate HW caches" },
61 { "nohiz", ILO_DEBUG_NOHIZ
, "Disable HiZ" },
66 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
69 case PIPE_CAPF_MAX_LINE_WIDTH
:
70 /* in U3.7, defined in 3DSTATE_SF */
72 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
73 /* line width minus one, which is reserved for AA region */
75 case PIPE_CAPF_MAX_POINT_WIDTH
:
76 /* in U8.3, defined in 3DSTATE_SF */
78 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
79 /* same as point width, as we ignore rasterizer->point_smooth */
81 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
82 /* [2.0, 16.0], defined in SAMPLER_STATE */
84 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
85 /* [-16.0, 16.0), defined in SAMPLER_STATE */
87 case PIPE_CAPF_GUARD_BAND_LEFT
:
88 case PIPE_CAPF_GUARD_BAND_TOP
:
89 case PIPE_CAPF_GUARD_BAND_RIGHT
:
90 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
91 /* what are these for? */
100 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
101 enum pipe_shader_cap param
)
104 case PIPE_SHADER_FRAGMENT
:
105 case PIPE_SHADER_VERTEX
:
106 case PIPE_SHADER_GEOMETRY
:
113 /* the limits are copied from the classic driver */
114 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
115 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
116 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
117 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
118 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
119 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
120 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
121 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
122 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
124 case PIPE_SHADER_CAP_MAX_INPUTS
:
125 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
126 /* this is limited by how many attributes SF can remap */
128 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
129 return 1024 * sizeof(float[4]);
130 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
131 return ILO_MAX_CONST_BUFFERS
;
132 case PIPE_SHADER_CAP_MAX_TEMPS
:
134 case PIPE_SHADER_CAP_MAX_PREDS
:
136 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
138 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
140 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
142 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
143 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
144 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
146 case PIPE_SHADER_CAP_SUBROUTINES
:
148 case PIPE_SHADER_CAP_INTEGERS
:
150 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
151 return ILO_MAX_SAMPLERS
;
152 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
153 return ILO_MAX_SAMPLER_VIEWS
;
154 case PIPE_SHADER_CAP_PREFERRED_IR
:
155 return PIPE_SHADER_IR_TGSI
;
156 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
165 ilo_get_video_param(struct pipe_screen
*screen
,
166 enum pipe_video_profile profile
,
167 enum pipe_video_entrypoint entrypoint
,
168 enum pipe_video_cap param
)
171 case PIPE_VIDEO_CAP_SUPPORTED
:
172 return vl_profile_supported(screen
, profile
, entrypoint
);
173 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
175 case PIPE_VIDEO_CAP_MAX_WIDTH
:
176 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
177 return vl_video_buffer_max_size(screen
);
178 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
179 return PIPE_FORMAT_NV12
;
180 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
182 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
184 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
186 case PIPE_VIDEO_CAP_MAX_LEVEL
:
187 return vl_level_supported(screen
, profile
);
194 ilo_get_compute_param(struct pipe_screen
*screen
,
195 enum pipe_compute_cap param
,
198 struct ilo_screen
*is
= ilo_screen(screen
);
200 const char *ir_target
;
201 uint64_t grid_dimension
;
202 uint64_t max_grid_size
[3];
203 uint64_t max_block_size
[3];
204 uint64_t max_threads_per_block
;
205 uint64_t max_global_size
;
206 uint64_t max_local_size
;
207 uint64_t max_private_size
;
208 uint64_t max_input_size
;
209 uint64_t max_mem_alloc_size
;
210 uint32_t max_clock_frequency
;
211 uint32_t max_compute_units
;
212 uint32_t images_supported
;
218 case PIPE_COMPUTE_CAP_IR_TARGET
:
219 val
.ir_target
= "ilog";
222 size
= strlen(val
.ir_target
) + 1;
224 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
225 val
.grid_dimension
= Elements(val
.max_grid_size
);
227 ptr
= &val
.grid_dimension
;
228 size
= sizeof(val
.grid_dimension
);
230 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
231 val
.max_grid_size
[0] = 0xffffffffu
;
232 val
.max_grid_size
[1] = 0xffffffffu
;
233 val
.max_grid_size
[2] = 0xffffffffu
;
235 ptr
= &val
.max_grid_size
;
236 size
= sizeof(val
.max_grid_size
);
238 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
239 val
.max_block_size
[0] = 1024;
240 val
.max_block_size
[1] = 1024;
241 val
.max_block_size
[2] = 1024;
243 ptr
= &val
.max_block_size
;
244 size
= sizeof(val
.max_block_size
);
247 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
248 val
.max_threads_per_block
= 1024;
250 ptr
= &val
.max_threads_per_block
;
251 size
= sizeof(val
.max_threads_per_block
);
253 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
254 /* \see ilo_max_resource_size */
255 val
.max_global_size
= 1u << 31;
257 ptr
= &val
.max_global_size
;
258 size
= sizeof(val
.max_global_size
);
260 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
261 /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
262 val
.max_local_size
= 64 * 1024;
264 ptr
= &val
.max_local_size
;
265 size
= sizeof(val
.max_local_size
);
267 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
269 val
.max_private_size
= 12 * 1024;
271 ptr
= &val
.max_private_size
;
272 size
= sizeof(val
.max_private_size
);
274 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
275 val
.max_input_size
= 1024;
277 ptr
= &val
.max_input_size
;
278 size
= sizeof(val
.max_input_size
);
280 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
281 val
.max_mem_alloc_size
= 1u << 31;
283 ptr
= &val
.max_mem_alloc_size
;
284 size
= sizeof(val
.max_mem_alloc_size
);
286 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
287 val
.max_clock_frequency
= 1000;
289 ptr
= &val
.max_clock_frequency
;
290 size
= sizeof(val
.max_clock_frequency
);
292 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
293 val
.max_compute_units
= is
->dev
.eu_count
;
295 ptr
= &val
.max_compute_units
;
296 size
= sizeof(val
.max_compute_units
);
298 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
299 val
.images_supported
= 1;
301 ptr
= &val
.images_supported
;
302 size
= sizeof(val
.images_supported
);
311 memcpy(ret
, ptr
, size
);
317 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
319 struct ilo_screen
*is
= ilo_screen(screen
);
322 case PIPE_CAP_NPOT_TEXTURES
:
323 case PIPE_CAP_TWO_SIDED_STENCIL
:
325 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
327 case PIPE_CAP_ANISOTROPIC_FILTER
:
328 case PIPE_CAP_POINT_SPRITE
:
330 case PIPE_CAP_MAX_RENDER_TARGETS
:
331 return ILO_MAX_DRAW_BUFFERS
;
332 case PIPE_CAP_OCCLUSION_QUERY
:
333 case PIPE_CAP_QUERY_TIME_ELAPSED
:
334 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
335 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
337 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
339 * As defined in SURFACE_STATE, we have
341 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
342 * GEN6 8192x8192x512 2048x2048x2048
343 * GEN7 16384x16384x2048 2048x2048x2048
345 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
346 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
348 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
349 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
350 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
352 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
355 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
356 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
358 return ILO_MAX_SO_BUFFERS
;
359 case PIPE_CAP_PRIMITIVE_RESTART
:
361 case PIPE_CAP_INDEP_BLEND_ENABLE
:
362 case PIPE_CAP_INDEP_BLEND_FUNC
:
364 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
365 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 2048 : 512;
366 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
367 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
368 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
369 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
370 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
372 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
374 case PIPE_CAP_TGSI_INSTANCEID
:
375 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
377 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
379 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
381 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
382 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
384 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
385 case PIPE_CAP_MIN_TEXEL_OFFSET
:
387 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
388 case PIPE_CAP_MAX_TEXEL_OFFSET
:
390 case PIPE_CAP_CONDITIONAL_RENDER
:
391 case PIPE_CAP_TEXTURE_BARRIER
:
393 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
394 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
395 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
396 return ILO_MAX_SO_BINDINGS
;
397 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
398 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7))
399 return is
->dev
.has_gen7_sol_reset
;
401 return false; /* TODO */
402 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
404 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
406 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
408 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
410 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
411 case PIPE_CAP_USER_VERTEX_BUFFERS
:
413 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
414 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
415 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
417 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
419 case PIPE_CAP_COMPUTE
:
420 return false; /* TODO */
421 case PIPE_CAP_USER_INDEX_BUFFERS
:
422 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
424 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
425 /* imposed by OWord (Dual) Block Read */
427 case PIPE_CAP_START_INSTANCE
:
429 case PIPE_CAP_QUERY_TIMESTAMP
:
430 return is
->dev
.has_timestamp
;
431 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
432 return false; /* TODO */
433 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
434 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
435 case PIPE_CAP_CUBE_MAP_ARRAY
:
436 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
438 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
440 case PIPE_CAP_TGSI_TEXCOORD
:
442 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
443 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
445 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
447 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
448 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
450 case PIPE_CAP_MAX_VIEWPORTS
:
451 return ILO_MAX_VIEWPORTS
;
452 case PIPE_CAP_ENDIANNESS
:
453 return PIPE_ENDIAN_LITTLE
;
454 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
456 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
457 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
458 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
459 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
460 case PIPE_CAP_TEXTURE_GATHER_SM5
:
462 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
464 case PIPE_CAP_FAKE_SW_MSAA
:
465 case PIPE_CAP_TEXTURE_QUERY_LOD
:
466 case PIPE_CAP_SAMPLE_SHADING
:
467 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
468 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
469 case PIPE_CAP_MAX_VERTEX_STREAMS
:
470 case PIPE_CAP_DRAW_INDIRECT
:
471 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
472 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
473 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
474 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
475 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
478 case PIPE_CAP_VENDOR_ID
:
480 case PIPE_CAP_DEVICE_ID
:
481 return is
->dev
.devid
;
482 case PIPE_CAP_ACCELERATED
:
484 case PIPE_CAP_VIDEO_MEMORY
: {
485 /* Once a batch uses more than 75% of the maximum mappable size, we
486 * assume that there's some fragmentation, and we start doing extra
487 * flushing, etc. That's the big cliff apps will care about.
489 const uint64_t gpu_memory
= is
->dev
.aperture_total
* 3 / 4;
490 uint64_t system_memory
;
492 if (!os_get_total_physical_memory(&system_memory
))
495 return (int) (MIN2(gpu_memory
, system_memory
) >> 20);
499 case PIPE_CAP_CLIP_HALFZ
:
501 case PIPE_CAP_VERTEXID_NOBASE
:
503 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
512 ilo_get_vendor(struct pipe_screen
*screen
)
514 return "LunarG, Inc.";
518 ilo_get_device_vendor(struct pipe_screen
*screen
)
524 ilo_get_name(struct pipe_screen
*screen
)
526 struct ilo_screen
*is
= ilo_screen(screen
);
527 const char *chipset
= NULL
;
529 if (gen_is_chv(is
->dev
.devid
)) {
530 chipset
= "Intel(R) Cherryview";
531 } else if (gen_is_bdw(is
->dev
.devid
)) {
532 /* this is likely wrong */
533 if (gen_is_desktop(is
->dev
.devid
))
534 chipset
= "Intel(R) Broadwell Desktop";
535 else if (gen_is_mobile(is
->dev
.devid
))
536 chipset
= "Intel(R) Broadwell Mobile";
537 else if (gen_is_server(is
->dev
.devid
))
538 chipset
= "Intel(R) Broadwell Server";
539 } else if (gen_is_vlv(is
->dev
.devid
)) {
540 chipset
= "Intel(R) Bay Trail";
541 } else if (gen_is_hsw(is
->dev
.devid
)) {
542 if (gen_is_desktop(is
->dev
.devid
))
543 chipset
= "Intel(R) Haswell Desktop";
544 else if (gen_is_mobile(is
->dev
.devid
))
545 chipset
= "Intel(R) Haswell Mobile";
546 else if (gen_is_server(is
->dev
.devid
))
547 chipset
= "Intel(R) Haswell Server";
548 } else if (gen_is_ivb(is
->dev
.devid
)) {
549 if (gen_is_desktop(is
->dev
.devid
))
550 chipset
= "Intel(R) Ivybridge Desktop";
551 else if (gen_is_mobile(is
->dev
.devid
))
552 chipset
= "Intel(R) Ivybridge Mobile";
553 else if (gen_is_server(is
->dev
.devid
))
554 chipset
= "Intel(R) Ivybridge Server";
555 } else if (gen_is_snb(is
->dev
.devid
)) {
556 if (gen_is_desktop(is
->dev
.devid
))
557 chipset
= "Intel(R) Sandybridge Desktop";
558 else if (gen_is_mobile(is
->dev
.devid
))
559 chipset
= "Intel(R) Sandybridge Mobile";
560 else if (gen_is_server(is
->dev
.devid
))
561 chipset
= "Intel(R) Sandybridge Server";
565 chipset
= "Unknown Intel Chipset";
571 ilo_get_timestamp(struct pipe_screen
*screen
)
573 struct ilo_screen
*is
= ilo_screen(screen
);
579 intel_winsys_read_reg(is
->winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
582 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
584 * "Note: This timestamp register reflects the value of the PCU TSC.
585 * The PCU TSC counts 10ns increments; this timestamp reflects bits
586 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
589 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
590 * of the timestamp. We will have to live with a timestamp that rolls over
591 * every ~343 seconds.
593 * See also brw_get_timestamp().
595 return (uint64_t) timestamp
.dw
[1] * 80;
599 ilo_fence_reference(struct pipe_screen
*screen
,
600 struct pipe_fence_handle
**p
,
601 struct pipe_fence_handle
*f
)
603 struct ilo_fence
*fence
= ilo_fence(f
);
604 struct ilo_fence
*old
;
613 STATIC_ASSERT(&((struct ilo_fence
*) NULL
)->reference
== NULL
);
614 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
615 intel_bo_unref(old
->bo
);
621 ilo_fence_signalled(struct pipe_screen
*screen
,
622 struct pipe_fence_handle
*f
)
624 struct ilo_fence
*fence
= ilo_fence(f
);
626 /* mark signalled if the bo is idle */
627 if (fence
->bo
&& !intel_bo_is_busy(fence
->bo
)) {
628 intel_bo_unref(fence
->bo
);
632 return (fence
->bo
== NULL
);
636 ilo_fence_finish(struct pipe_screen
*screen
,
637 struct pipe_fence_handle
*f
,
640 struct ilo_fence
*fence
= ilo_fence(f
);
641 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
643 /* already signalled */
647 /* wait and see if it returns error */
648 if (intel_bo_wait(fence
->bo
, wait_timeout
))
652 intel_bo_unref(fence
->bo
);
659 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
660 * before waited on or checked.
663 ilo_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
665 struct ilo_fence
*fence
;
667 fence
= CALLOC_STRUCT(ilo_fence
);
671 pipe_reference_init(&fence
->reference
, 1);
673 fence
->bo
= intel_bo_ref(bo
);
679 ilo_screen_destroy(struct pipe_screen
*screen
)
681 struct ilo_screen
*is
= ilo_screen(screen
);
683 /* as it seems, winsys is owned by the screen */
684 intel_winsys_destroy(is
->winsys
);
690 init_dev(struct ilo_dev_info
*dev
, const struct intel_winsys_info
*info
)
692 dev
->devid
= info
->devid
;
693 dev
->aperture_total
= info
->aperture_total
;
694 dev
->aperture_mappable
= info
->aperture_mappable
;
695 dev
->has_llc
= info
->has_llc
;
696 dev
->has_address_swizzling
= info
->has_address_swizzling
;
697 dev
->has_logical_context
= info
->has_logical_context
;
698 dev
->has_ppgtt
= info
->has_ppgtt
;
699 dev
->has_timestamp
= info
->has_timestamp
;
700 dev
->has_gen7_sol_reset
= info
->has_gen7_sol_reset
;
702 if (!dev
->has_logical_context
) {
703 ilo_err("missing hardware logical context support\n");
708 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
711 * From the Sandy Bridge PRM, volume 1 part 3, page 101:
713 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
714 * code is in a secure environment, independent of address space.
715 * Under this condition, this bit only specifies the address space
716 * (GGTT or PPGTT). All commands are executed "as-is""
718 * We need PPGTT to be enabled on GEN6 too.
720 if (!dev
->has_ppgtt
) {
721 /* experiments show that it does not really matter... */
722 ilo_warn("PPGTT disabled\n");
725 if (gen_is_bdw(info
->devid
) || gen_is_chv(info
->devid
)) {
726 dev
->gen_opaque
= ILO_GEN(8);
727 dev
->gt
= (gen_is_bdw(info
->devid
)) ? gen_get_bdw_gt(info
->devid
) : 1;
728 /* XXX random values */
731 dev
->thread_count
= 336;
732 dev
->urb_size
= 384 * 1024;
733 } else if (dev
->gt
== 2) {
735 dev
->thread_count
= 168;
736 dev
->urb_size
= 384 * 1024;
739 dev
->thread_count
= 84;
740 dev
->urb_size
= 192 * 1024;
742 } else if (gen_is_hsw(info
->devid
)) {
744 * From the Haswell PRM, volume 4, page 8:
746 * "Description GT3 GT2 GT1.5 GT1
748 * EUs (Total) 40 20 12 10
749 * Threads (Total) 280 140 84 70
751 * URB Size (max, within L3$) 512KB 256KB 256KB 128KB
753 dev
->gen_opaque
= ILO_GEN(7.5);
754 dev
->gt
= gen_get_hsw_gt(info
->devid
);
757 dev
->thread_count
= 280;
758 dev
->urb_size
= 512 * 1024;
759 } else if (dev
->gt
== 2) {
761 dev
->thread_count
= 140;
762 dev
->urb_size
= 256 * 1024;
765 dev
->thread_count
= 70;
766 dev
->urb_size
= 128 * 1024;
768 } else if (gen_is_ivb(info
->devid
) || gen_is_vlv(info
->devid
)) {
770 * From the Ivy Bridge PRM, volume 1 part 1, page 18:
772 * "Device # of EUs #Threads/EU
773 * Ivy Bridge (GT2) 16 8
774 * Ivy Bridge (GT1) 6 6"
776 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
778 * "URB Size URB Rows URB Rows when SLM Enabled
782 dev
->gen_opaque
= ILO_GEN(7);
783 dev
->gt
= (gen_is_ivb(info
->devid
)) ? gen_get_ivb_gt(info
->devid
) : 1;
786 dev
->thread_count
= 128;
787 dev
->urb_size
= 256 * 1024;
790 dev
->thread_count
= 36;
791 dev
->urb_size
= 128 * 1024;
793 } else if (gen_is_snb(info
->devid
)) {
795 * From the Sandy Bridge PRM, volume 1 part 1, page 22:
797 * "Device # of EUs #Threads/EU
801 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
803 * "[DevSNB]: The GT1 product's URB provides 32KB of storage,
804 * arranged as 1024 256-bit rows. The GT2 product's URB provides
805 * 64KB of storage, arranged as 2048 256-bit rows. A row
806 * corresponds in size to an EU GRF register. Read/write access to
807 * the URB is generally supported on a row-granular basis."
809 dev
->gen_opaque
= ILO_GEN(6);
810 dev
->gt
= gen_get_snb_gt(info
->devid
);
813 dev
->thread_count
= 60;
814 dev
->urb_size
= 64 * 1024;
817 dev
->thread_count
= 24;
818 dev
->urb_size
= 32 * 1024;
821 ilo_err("unknown GPU generation\n");
829 ilo_screen_create(struct intel_winsys
*ws
)
831 struct ilo_screen
*is
;
832 const struct intel_winsys_info
*info
;
834 ilo_debug
= debug_get_flags_option("ILO_DEBUG", ilo_debug_flags
, 0);
836 is
= CALLOC_STRUCT(ilo_screen
);
842 info
= intel_winsys_get_info(is
->winsys
);
843 if (!init_dev(&is
->dev
, info
)) {
848 util_format_s3tc_init();
850 is
->base
.destroy
= ilo_screen_destroy
;
851 is
->base
.get_name
= ilo_get_name
;
852 is
->base
.get_vendor
= ilo_get_vendor
;
853 is
->base
.get_device_vendor
= ilo_get_device_vendor
;
854 is
->base
.get_param
= ilo_get_param
;
855 is
->base
.get_paramf
= ilo_get_paramf
;
856 is
->base
.get_shader_param
= ilo_get_shader_param
;
857 is
->base
.get_video_param
= ilo_get_video_param
;
858 is
->base
.get_compute_param
= ilo_get_compute_param
;
860 is
->base
.get_timestamp
= ilo_get_timestamp
;
862 is
->base
.flush_frontbuffer
= NULL
;
864 is
->base
.fence_reference
= ilo_fence_reference
;
865 is
->base
.fence_signalled
= ilo_fence_signalled
;
866 is
->base
.fence_finish
= ilo_fence_finish
;
868 is
->base
.get_driver_query_info
= NULL
;
870 ilo_init_format_functions(is
);
871 ilo_init_context_functions(is
);
872 ilo_init_resource_functions(is
);