src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "os/os_misc.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  34 #include "core/ilo_fence.h"
  35 #include "core/ilo_format.h"
  36 #include "core/intel_winsys.h"
  37
  38 #include "ilo_context.h"
  39 #include "ilo_resource.h"
  40 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  41 #include "ilo_public.h"
  42 #include "ilo_screen.h"
  43
  44 struct pipe_fence_handle {
  45    struct pipe_reference reference;
  46
  47    struct ilo_fence fence;
  48 };
  49
  50 static float
  51 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  52 {
  53    switch (param) {
  54    case PIPE_CAPF_MAX_LINE_WIDTH:
  55       /* in U3.7, defined in 3DSTATE_SF */
  56       return 7.0f;
  57    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  58       /* line width minus one, which is reserved for AA region */
  59       return 6.0f;
  60    case PIPE_CAPF_MAX_POINT_WIDTH:
  61       /* in U8.3, defined in 3DSTATE_SF */
  62       return 255.0f;
  63    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  64       /* same as point width, as we ignore rasterizer->point_smooth */
  65       return 255.0f;
  66    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  67       /* [2.0, 16.0], defined in SAMPLER_STATE */
  68       return 16.0f;
  69    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  70       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  71       return 15.0f;
  72    case PIPE_CAPF_GUARD_BAND_LEFT:
  73    case PIPE_CAPF_GUARD_BAND_TOP:
  74    case PIPE_CAPF_GUARD_BAND_RIGHT:
  75    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  76       /* what are these for? */
  77       return 0.0f;
  78
  79    default:
  80       return 0.0f;
  81    }
  82 }
  83
  84 static int
  85 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  86                      enum pipe_shader_cap param)
  87 {
  88    switch (shader) {
  89    case PIPE_SHADER_FRAGMENT:
  90    case PIPE_SHADER_VERTEX:
  91    case PIPE_SHADER_GEOMETRY:
  92       break;
  93    default:
  94       return 0;
  95    }
  96
  97    switch (param) {
  98    /* the limits are copied from the classic driver */
  99    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 100       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 101    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 102       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 103    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 104       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 105    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 106       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 107    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 108       return UINT_MAX;
 109    case PIPE_SHADER_CAP_MAX_INPUTS:
 110    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 111       /* this is limited by how many attributes SF can remap */
 112       return 16;
 113    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 114       return 1024 * sizeof(float[4]);
 115    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 116       return ILO_MAX_CONST_BUFFERS;
 117    case PIPE_SHADER_CAP_MAX_TEMPS:
 118       return 256;
 119    case PIPE_SHADER_CAP_MAX_PREDS:
 120       return 0;
 121    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 122       return 1;
 123    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 124       return 0;
 125    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 126       return 0;
 127    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 128       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 129    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 130       return 1;
 131    case PIPE_SHADER_CAP_SUBROUTINES:
 132       return 0;
 133    case PIPE_SHADER_CAP_INTEGERS:
 134       return 1;
 135    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 136       return ILO_MAX_SAMPLERS;
 137    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 138       return ILO_MAX_SAMPLER_VIEWS;
 139    case PIPE_SHADER_CAP_PREFERRED_IR:
 140       return PIPE_SHADER_IR_TGSI;
 141    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 142       return 1;
 143
 144    default:
 145       return 0;
 146    }
 147 }
 148
 149 static int
 150 ilo_get_video_param(struct pipe_screen *screen,
 151                     enum pipe_video_profile profile,
 152                     enum pipe_video_entrypoint entrypoint,
 153                     enum pipe_video_cap param)
 154 {
 155    switch (param) {
 156    case PIPE_VIDEO_CAP_SUPPORTED:
 157       return vl_profile_supported(screen, profile, entrypoint);
 158    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 159       return 1;
 160    case PIPE_VIDEO_CAP_MAX_WIDTH:
 161    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 162       return vl_video_buffer_max_size(screen);
 163    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 164       return PIPE_FORMAT_NV12;
 165    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 166       return 1;
 167    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 168       return 1;
 169    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 170       return 0;
 171    case PIPE_VIDEO_CAP_MAX_LEVEL:
 172       return vl_level_supported(screen, profile);
 173    default:
 174       return 0;
 175    }
 176 }
 177
 178 static int
 179 ilo_get_compute_param(struct pipe_screen *screen,
 180                       enum pipe_compute_cap param,
 181                       void *ret)
 182 {
 183    struct ilo_screen *is = ilo_screen(screen);
 184    union {
 185       const char *ir_target;
 186       uint64_t grid_dimension;
 187       uint64_t max_grid_size[3];
 188       uint64_t max_block_size[3];
 189       uint64_t max_threads_per_block;
 190       uint64_t max_global_size;
 191       uint64_t max_local_size;
 192       uint64_t max_private_size;
 193       uint64_t max_input_size;
 194       uint64_t max_mem_alloc_size;
 195       uint32_t max_clock_frequency;
 196       uint32_t max_compute_units;
 197       uint32_t images_supported;
 198    } val;
 199    const void *ptr;
 200    int size;
 201
 202    switch (param) {
 203    case PIPE_COMPUTE_CAP_IR_TARGET:
 204       val.ir_target = "ilog";
 205
 206       ptr = val.ir_target;
 207       size = strlen(val.ir_target) + 1;
 208       break;
 209    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 210       val.grid_dimension = Elements(val.max_grid_size);
 211
 212       ptr = &val.grid_dimension;
 213       size = sizeof(val.grid_dimension);
 214       break;
 215    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 216       val.max_grid_size[0] = 0xffffffffu;
 217       val.max_grid_size[1] = 0xffffffffu;
 218       val.max_grid_size[2] = 0xffffffffu;
 219
 220       ptr = &val.max_grid_size;
 221       size = sizeof(val.max_grid_size);
 222       break;
 223    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 224       val.max_block_size[0] = 1024;
 225       val.max_block_size[1] = 1024;
 226       val.max_block_size[2] = 1024;
 227
 228       ptr = &val.max_block_size;
 229       size = sizeof(val.max_block_size);
 230       break;
 231
 232    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 233       val.max_threads_per_block = 1024;
 234
 235       ptr = &val.max_threads_per_block;
 236       size = sizeof(val.max_threads_per_block);
 237       break;
 238    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 239       /* \see ilo_max_resource_size */
 240       val.max_global_size = 1u << 31;
 241
 242       ptr = &val.max_global_size;
 243       size = sizeof(val.max_global_size);
 244       break;
 245    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 246       /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
 247       val.max_local_size = 64 * 1024;
 248
 249       ptr = &val.max_local_size;
 250       size = sizeof(val.max_local_size);
 251       break;
 252    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 253       /* scratch size */
 254       val.max_private_size = 12 * 1024;
 255
 256       ptr = &val.max_private_size;
 257       size = sizeof(val.max_private_size);
 258       break;
 259    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 260       val.max_input_size = 1024;
 261
 262       ptr = &val.max_input_size;
 263       size = sizeof(val.max_input_size);
 264       break;
 265    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 266       val.max_mem_alloc_size = 1u << 31;
 267
 268       ptr = &val.max_mem_alloc_size;
 269       size = sizeof(val.max_mem_alloc_size);
 270       break;
 271    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 272       val.max_clock_frequency = 1000;
 273
 274       ptr = &val.max_clock_frequency;
 275       size = sizeof(val.max_clock_frequency);
 276       break;
 277    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 278       val.max_compute_units = is->dev.eu_count;
 279
 280       ptr = &val.max_compute_units;
 281       size = sizeof(val.max_compute_units);
 282       break;
 283    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 284       val.images_supported = 1;
 285
 286       ptr = &val.images_supported;
 287       size = sizeof(val.images_supported);
 288       break;
 289    default:
 290       ptr = NULL;
 291       size = 0;
 292       break;
 293    }
 294
 295    if (ret)
 296       memcpy(ret, ptr, size);
 297
 298    return size;
 299 }
 300
 301 static int
 302 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 303 {
 304    struct ilo_screen *is = ilo_screen(screen);
 305
 306    switch (param) {
 307    case PIPE_CAP_NPOT_TEXTURES:
 308    case PIPE_CAP_TWO_SIDED_STENCIL:
 309       return true;
 310    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 311       return 0; /* TODO */
 312    case PIPE_CAP_ANISOTROPIC_FILTER:
 313    case PIPE_CAP_POINT_SPRITE:
 314       return true;
 315    case PIPE_CAP_MAX_RENDER_TARGETS:
 316       return ILO_MAX_DRAW_BUFFERS;
 317    case PIPE_CAP_OCCLUSION_QUERY:
 318    case PIPE_CAP_QUERY_TIME_ELAPSED:
 319    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 320    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 321       return true;
 322    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 323       /*
 324        * As defined in SURFACE_STATE, we have
 325        *
 326        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 327        *  GEN6           8192x8192x512            2048x2048x2048
 328        *  GEN7         16384x16384x2048           2048x2048x2048
 329        */
 330       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 331    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 332       return 12;
 333    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 334       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
 335    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 336       return false;
 337    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 338    case PIPE_CAP_SM3:
 339       return true;
 340    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 341       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 342          return 0;
 343       return ILO_MAX_SO_BUFFERS;
 344    case PIPE_CAP_PRIMITIVE_RESTART:
 345       return true;
 346    case PIPE_CAP_INDEP_BLEND_ENABLE:
 347    case PIPE_CAP_INDEP_BLEND_FUNC:
 348       return true;
 349    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 350       return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
 351    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 352    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 353    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 354    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 355    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 356       return true;
 357    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 358       return false;
 359    case PIPE_CAP_TGSI_INSTANCEID:
 360    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 361       return true;
 362    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 363       return false;
 364    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 365       return true;
 366    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 367    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 368       return true;
 369    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 370    case PIPE_CAP_MIN_TEXEL_OFFSET:
 371       return -8;
 372    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 373    case PIPE_CAP_MAX_TEXEL_OFFSET:
 374       return 7;
 375    case PIPE_CAP_CONDITIONAL_RENDER:
 376    case PIPE_CAP_TEXTURE_BARRIER:
 377       return true;
 378    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 379       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 380    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 381       return ILO_MAX_SO_BINDINGS;
 382    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 383       if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
 384          return is->dev.has_gen7_sol_reset;
 385       else
 386          return false; /* TODO */
 387    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 388       return false;
 389    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 390       return true;
 391    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 392       return false;
 393    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 394       return 140;
 395    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 396    case PIPE_CAP_USER_VERTEX_BUFFERS:
 397       return false;
 398    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 399    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 400    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 401       return false;
 402    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 403       return 2048;
 404    case PIPE_CAP_COMPUTE:
 405       return false; /* TODO */
 406    case PIPE_CAP_USER_INDEX_BUFFERS:
 407    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 408       return true;
 409    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 410       /* imposed by OWord (Dual) Block Read */
 411       return 16;
 412    case PIPE_CAP_START_INSTANCE:
 413       return true;
 414    case PIPE_CAP_QUERY_TIMESTAMP:
 415       return is->dev.has_timestamp;
 416    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 417       return false; /* TODO */
 418    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 419       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 420    case PIPE_CAP_CUBE_MAP_ARRAY:
 421    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 422       return true;
 423    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 424       return 1;
 425    case PIPE_CAP_TGSI_TEXCOORD:
 426       return false;
 427    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 428    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 429       return true;
 430    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 431       return 0;
 432    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 433       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 434       return 1 << 27;
 435    case PIPE_CAP_MAX_VIEWPORTS:
 436       return ILO_MAX_VIEWPORTS;
 437    case PIPE_CAP_ENDIANNESS:
 438       return PIPE_ENDIAN_LITTLE;
 439    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 440       return true;
 441    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 442    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 443    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 444    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 445    case PIPE_CAP_TEXTURE_GATHER_SM5:
 446       return 0;
 447    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 448       return true;
 449    case PIPE_CAP_FAKE_SW_MSAA:
 450    case PIPE_CAP_TEXTURE_QUERY_LOD:
 451    case PIPE_CAP_SAMPLE_SHADING:
 452    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 453    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 454    case PIPE_CAP_MAX_VERTEX_STREAMS:
 455    case PIPE_CAP_DRAW_INDIRECT:
 456    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 457    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 458    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 459    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 460    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 461       return 0;
 462
 463    case PIPE_CAP_VENDOR_ID:
 464       return 0x8086;
 465    case PIPE_CAP_DEVICE_ID:
 466       return is->dev.devid;
 467    case PIPE_CAP_ACCELERATED:
 468       return true;
 469    case PIPE_CAP_VIDEO_MEMORY: {
 470       /* Once a batch uses more than 75% of the maximum mappable size, we
 471        * assume that there's some fragmentation, and we start doing extra
 472        * flushing, etc.  That's the big cliff apps will care about.
 473        */
 474       const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
 475       uint64_t system_memory;
 476
 477       if (!os_get_total_physical_memory(&system_memory))
 478          return 0;
 479
 480       return (int) (MIN2(gpu_memory, system_memory) >> 20);
 481    }
 482    case PIPE_CAP_UMA:
 483       return true;
 484    case PIPE_CAP_CLIP_HALFZ:
 485       return true;
 486    case PIPE_CAP_VERTEXID_NOBASE:
 487       return false;
 488    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 489       return true;
 490
 491    default:
 492       return 0;
 493    }
 494 }
 495
 496 static const char *
 497 ilo_get_vendor(struct pipe_screen *screen)
 498 {
 499    return "LunarG, Inc.";
 500 }
 501
 502 static const char *
 503 ilo_get_device_vendor(struct pipe_screen *screen)
 504 {
 505    return "Intel";
 506 }
 507
 508 static const char *
 509 ilo_get_name(struct pipe_screen *screen)
 510 {
 511    struct ilo_screen *is = ilo_screen(screen);
 512    const char *chipset = NULL;
 513
 514    if (gen_is_chv(is->dev.devid)) {
 515       chipset = "Intel(R) Cherryview";
 516    } else if (gen_is_bdw(is->dev.devid)) {
 517       /* this is likely wrong */
 518       if (gen_is_desktop(is->dev.devid))
 519          chipset = "Intel(R) Broadwell Desktop";
 520       else if (gen_is_mobile(is->dev.devid))
 521          chipset = "Intel(R) Broadwell Mobile";
 522       else if (gen_is_server(is->dev.devid))
 523          chipset = "Intel(R) Broadwell Server";
 524    } else if (gen_is_vlv(is->dev.devid)) {
 525       chipset = "Intel(R) Bay Trail";
 526    } else if (gen_is_hsw(is->dev.devid)) {
 527       if (gen_is_desktop(is->dev.devid))
 528          chipset = "Intel(R) Haswell Desktop";
 529       else if (gen_is_mobile(is->dev.devid))
 530          chipset = "Intel(R) Haswell Mobile";
 531       else if (gen_is_server(is->dev.devid))
 532          chipset = "Intel(R) Haswell Server";
 533    } else if (gen_is_ivb(is->dev.devid)) {
 534       if (gen_is_desktop(is->dev.devid))
 535          chipset = "Intel(R) Ivybridge Desktop";
 536       else if (gen_is_mobile(is->dev.devid))
 537          chipset = "Intel(R) Ivybridge Mobile";
 538       else if (gen_is_server(is->dev.devid))
 539          chipset = "Intel(R) Ivybridge Server";
 540    } else if (gen_is_snb(is->dev.devid)) {
 541       if (gen_is_desktop(is->dev.devid))
 542          chipset = "Intel(R) Sandybridge Desktop";
 543       else if (gen_is_mobile(is->dev.devid))
 544          chipset = "Intel(R) Sandybridge Mobile";
 545       else if (gen_is_server(is->dev.devid))
 546          chipset = "Intel(R) Sandybridge Server";
 547    }
 548
 549    if (!chipset)
 550       chipset = "Unknown Intel Chipset";
 551
 552    return chipset;
 553 }
 554
 555 static uint64_t
 556 ilo_get_timestamp(struct pipe_screen *screen)
 557 {
 558    struct ilo_screen *is = ilo_screen(screen);
 559    union {
 560       uint64_t val;
 561       uint32_t dw[2];
 562    } timestamp;
 563
 564    intel_winsys_read_reg(is->dev.winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 565
 566    /*
 567     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 568     *
 569     *     "Note: This timestamp register reflects the value of the PCU TSC.
 570     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 571     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 572     *      hours)."
 573     *
 574     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 575     * of the timestamp.  We will have to live with a timestamp that rolls over
 576     * every ~343 seconds.
 577     *
 578     * See also brw_get_timestamp().
 579     */
 580    return (uint64_t) timestamp.dw[1] * 80;
 581 }
 582
 583 static boolean
 584 ilo_is_format_supported(struct pipe_screen *screen,
 585                         enum pipe_format format,
 586                         enum pipe_texture_target target,
 587                         unsigned sample_count,
 588                         unsigned bindings)
 589 {
 590    struct ilo_screen *is = ilo_screen(screen);
 591    const struct ilo_dev *dev = &is->dev;
 592
 593    if (!util_format_is_supported(format, bindings))
 594       return false;
 595
 596    /* no MSAA support yet */
 597    if (sample_count > 1)
 598       return false;
 599
 600    if ((bindings & PIPE_BIND_DEPTH_STENCIL) &&
 601        !ilo_format_support_zs(dev, format))
 602       return false;
 603
 604    if ((bindings & PIPE_BIND_RENDER_TARGET) &&
 605        !ilo_format_support_rt(dev, format))
 606       return false;
 607
 608    if ((bindings & PIPE_BIND_SAMPLER_VIEW) &&
 609        !ilo_format_support_sampler(dev, format))
 610       return false;
 611
 612    if ((bindings & PIPE_BIND_VERTEX_BUFFER) &&
 613        !ilo_format_support_vb(dev, format))
 614       return false;
 615
 616    return true;
 617 }
 618
 619 static boolean
 620 ilo_is_video_format_supported(struct pipe_screen *screen,
 621                               enum pipe_format format,
 622                               enum pipe_video_profile profile,
 623                               enum pipe_video_entrypoint entrypoint)
 624 {
 625    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 626 }
 627
 628 static void
 629 ilo_screen_fence_reference(struct pipe_screen *screen,
 630                            struct pipe_fence_handle **ptr,
 631                            struct pipe_fence_handle *fence)
 632 {
 633    struct pipe_fence_handle *old;
 634
 635    if (likely(ptr)) {
 636       old = *ptr;
 637       *ptr = fence;
 638    } else {
 639       old = NULL;
 640    }
 641
 642    STATIC_ASSERT(&((struct pipe_fence_handle *) NULL)->reference == NULL);
 643    if (pipe_reference(&old->reference, &fence->reference)) {
 644       ilo_fence_cleanup(&old->fence);
 645       FREE(old);
 646    }
 647 }
 648
 649 static boolean
 650 ilo_screen_fence_finish(struct pipe_screen *screen,
 651                         struct pipe_fence_handle *fence,
 652                         uint64_t timeout)
 653 {
 654    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 655    bool signaled;
 656
 657    signaled = ilo_fence_wait(&fence->fence, wait_timeout);
 658    /* XXX not thread safe */
 659    if (signaled)
 660       ilo_fence_set_seq_bo(&fence->fence, NULL);
 661
 662    return signaled;
 663 }
 664
 665 static boolean
 666 ilo_screen_fence_signalled(struct pipe_screen *screen,
 667                            struct pipe_fence_handle *fence)
 668 {
 669    return ilo_screen_fence_finish(screen, fence, 0);
 670 }
 671
 672 /**
 673  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 674  * before waited on or checked.
 675  */
 676 struct pipe_fence_handle *
 677 ilo_screen_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 678 {
 679    struct ilo_screen *is = ilo_screen(screen);
 680    struct pipe_fence_handle *fence;
 681
 682    fence = CALLOC_STRUCT(pipe_fence_handle);
 683    if (!fence)
 684       return NULL;
 685
 686    pipe_reference_init(&fence->reference, 1);
 687
 688    ilo_fence_init(&fence->fence, &is->dev);
 689    ilo_fence_set_seq_bo(&fence->fence, bo);
 690
 691    return fence;
 692 }
 693
 694 static void
 695 ilo_screen_destroy(struct pipe_screen *screen)
 696 {
 697    struct ilo_screen *is = ilo_screen(screen);
 698
 699    ilo_dev_cleanup(&is->dev);
 700
 701    FREE(is);
 702 }
 703
 704 struct pipe_screen *
 705 ilo_screen_create(struct intel_winsys *ws)
 706 {
 707    struct ilo_screen *is;
 708
 709    ilo_debug_init("ILO_DEBUG");
 710
 711    is = CALLOC_STRUCT(ilo_screen);
 712    if (!is)
 713       return NULL;
 714
 715    if (!ilo_dev_init(&is->dev, ws)) {
 716       FREE(is);
 717       return NULL;
 718    }
 719
 720    util_format_s3tc_init();
 721
 722    is->base.destroy = ilo_screen_destroy;
 723    is->base.get_name = ilo_get_name;
 724    is->base.get_vendor = ilo_get_vendor;
 725    is->base.get_device_vendor = ilo_get_device_vendor;
 726    is->base.get_param = ilo_get_param;
 727    is->base.get_paramf = ilo_get_paramf;
 728    is->base.get_shader_param = ilo_get_shader_param;
 729    is->base.get_video_param = ilo_get_video_param;
 730    is->base.get_compute_param = ilo_get_compute_param;
 731
 732    is->base.get_timestamp = ilo_get_timestamp;
 733
 734    is->base.is_format_supported = ilo_is_format_supported;
 735    is->base.is_video_format_supported = ilo_is_video_format_supported;
 736
 737    is->base.flush_frontbuffer = NULL;
 738
 739    is->base.fence_reference = ilo_screen_fence_reference;
 740    is->base.fence_signalled = ilo_screen_fence_signalled;
 741    is->base.fence_finish = ilo_screen_fence_finish;
 742
 743    is->base.get_driver_query_info = NULL;
 744
 745    ilo_init_context_functions(is);
 746    ilo_init_resource_functions(is);
 747
 748    return &is->base;
 749 }