src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  32 #include "intel_winsys.h"
  33
  34 #include "ilo_context.h"
  35 #include "ilo_format.h"
  36 #include "ilo_resource.h"
  37 #include "ilo_public.h"
  38 #include "ilo_screen.h"
  39
  40 int ilo_debug;
  41
  42 static const struct debug_named_value ilo_debug_flags[] = {
  43    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  44    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  45    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  46    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  47    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  48    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  49    { "flush",     ILO_DEBUG_FLUSH,    "Show batch buffer flushes" },
  50    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  51    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  52    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  53    DEBUG_NAMED_VALUE_END
  54 };
  55
  56 static float
  57 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  58 {
  59    switch (param) {
  60    case PIPE_CAPF_MAX_LINE_WIDTH:
  61       /* in U3.7, defined in 3DSTATE_SF */
  62       return 7.0f;
  63    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  64       /* line width minus one, which is reserved for AA region */
  65       return 6.0f;
  66    case PIPE_CAPF_MAX_POINT_WIDTH:
  67       /* in U8.3, defined in 3DSTATE_SF */
  68       return 255.0f;
  69    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  70       /* same as point width, as we ignore rasterizer->point_smooth */
  71       return 255.0f;
  72    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  73       /* [2.0, 16.0], defined in SAMPLER_STATE */
  74       return 16.0f;
  75    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  76       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  77       return 15.0f;
  78    case PIPE_CAPF_GUARD_BAND_LEFT:
  79    case PIPE_CAPF_GUARD_BAND_TOP:
  80    case PIPE_CAPF_GUARD_BAND_RIGHT:
  81    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  82       /* what are these for? */
  83       return 0.0f;
  84
  85    default:
  86       return 0.0f;
  87    }
  88 }
  89
  90 static int
  91 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  92                      enum pipe_shader_cap param)
  93 {
  94    switch (shader) {
  95    case PIPE_SHADER_FRAGMENT:
  96    case PIPE_SHADER_VERTEX:
  97    case PIPE_SHADER_GEOMETRY:
  98       break;
  99    default:
 100       return 0;
 101    }
 102
 103    switch (param) {
 104    /* the limits are copied from the classic driver */
 105    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 106       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 107    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 108       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 109    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 110       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 111    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 112       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 113    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 114       return UINT_MAX;
 115    case PIPE_SHADER_CAP_MAX_INPUTS:
 116       /* this is limited by how many attributes SF can remap */
 117       return 16;
 118    case PIPE_SHADER_CAP_MAX_CONSTS:
 119       return 1024;
 120    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 121       return ILO_MAX_CONST_BUFFERS;
 122    case PIPE_SHADER_CAP_MAX_TEMPS:
 123       return 256;
 124    case PIPE_SHADER_CAP_MAX_ADDRS:
 125       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 126    case PIPE_SHADER_CAP_MAX_PREDS:
 127       return 0;
 128    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 129       return 1;
 130    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 131       return 0;
 132    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133       return 0;
 134    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 135       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 136    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 137       return 1;
 138    case PIPE_SHADER_CAP_SUBROUTINES:
 139       return 0;
 140    case PIPE_SHADER_CAP_INTEGERS:
 141       return 1;
 142    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 143       return ILO_MAX_SAMPLERS;
 144    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 145       return ILO_MAX_SAMPLER_VIEWS;
 146    case PIPE_SHADER_CAP_PREFERRED_IR:
 147       return PIPE_SHADER_IR_TGSI;
 148    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 149       return 1;
 150
 151    default:
 152       return 0;
 153    }
 154 }
 155
 156 static int
 157 ilo_get_video_param(struct pipe_screen *screen,
 158                     enum pipe_video_profile profile,
 159                     enum pipe_video_entrypoint entrypoint,
 160                     enum pipe_video_cap param)
 161 {
 162    switch (param) {
 163    case PIPE_VIDEO_CAP_SUPPORTED:
 164       return vl_profile_supported(screen, profile, entrypoint);
 165    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 166       return 1;
 167    case PIPE_VIDEO_CAP_MAX_WIDTH:
 168    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 169       return vl_video_buffer_max_size(screen);
 170    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 171       return PIPE_FORMAT_NV12;
 172    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 173       return 1;
 174    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 175       return 1;
 176    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 177       return 0;
 178    case PIPE_VIDEO_CAP_MAX_LEVEL:
 179       return vl_level_supported(screen, profile);
 180    default:
 181       return 0;
 182    }
 183 }
 184
 185 static int
 186 ilo_get_compute_param(struct pipe_screen *screen,
 187                       enum pipe_compute_cap param,
 188                       void *ret)
 189 {
 190    union {
 191       const char *ir_target;
 192       uint64_t grid_dimension;
 193       uint64_t max_grid_size[3];
 194       uint64_t max_block_size[3];
 195       uint64_t max_threads_per_block;
 196       uint64_t max_global_size;
 197       uint64_t max_local_size;
 198       uint64_t max_private_size;
 199       uint64_t max_input_size;
 200       uint64_t max_mem_alloc_size;
 201    } val;
 202    const void *ptr;
 203    int size;
 204
 205    /* XXX some randomly chosen values */
 206    switch (param) {
 207    case PIPE_COMPUTE_CAP_IR_TARGET:
 208       val.ir_target = "ilog";
 209
 210       ptr = val.ir_target;
 211       size = strlen(val.ir_target) + 1;
 212       break;
 213    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 214       val.grid_dimension = Elements(val.max_grid_size);
 215
 216       ptr = &val.grid_dimension;
 217       size = sizeof(val.grid_dimension);
 218       break;
 219    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 220       val.max_grid_size[0] = 65535;
 221       val.max_grid_size[1] = 65535;
 222       val.max_grid_size[2] = 1;
 223
 224       ptr = &val.max_grid_size;
 225       size = sizeof(val.max_grid_size);
 226       break;
 227    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 228       val.max_block_size[0] = 512;
 229       val.max_block_size[1] = 512;
 230       val.max_block_size[2] = 512;
 231
 232       ptr = &val.max_block_size;
 233       size = sizeof(val.max_block_size);
 234       break;
 235
 236    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 237       val.max_threads_per_block = 512;
 238
 239       ptr = &val.max_threads_per_block;
 240       size = sizeof(val.max_threads_per_block);
 241       break;
 242    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 243       val.max_global_size = 4;
 244
 245       ptr = &val.max_global_size;
 246       size = sizeof(val.max_global_size);
 247       break;
 248    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 249       val.max_local_size = 64 * 1024;
 250
 251       ptr = &val.max_local_size;
 252       size = sizeof(val.max_local_size);
 253       break;
 254    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 255       val.max_private_size = 32768;
 256
 257       ptr = &val.max_private_size;
 258       size = sizeof(val.max_private_size);
 259       break;
 260    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 261       val.max_input_size = 256;
 262
 263       ptr = &val.max_input_size;
 264       size = sizeof(val.max_input_size);
 265       break;
 266    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 267       val.max_mem_alloc_size = 128 * 1024 * 1024;
 268
 269       ptr = &val.max_mem_alloc_size;
 270       size = sizeof(val.max_mem_alloc_size);
 271       break;
 272    default:
 273       ptr = NULL;
 274       size = 0;
 275       break;
 276    }
 277
 278    if (ret)
 279       memcpy(ret, ptr, size);
 280
 281    return size;
 282 }
 283
 284 static int
 285 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 286 {
 287    struct ilo_screen *is = ilo_screen(screen);
 288
 289    switch (param) {
 290    case PIPE_CAP_NPOT_TEXTURES:
 291    case PIPE_CAP_TWO_SIDED_STENCIL:
 292       return true;
 293    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 294       return 0; /* TODO */
 295    case PIPE_CAP_ANISOTROPIC_FILTER:
 296    case PIPE_CAP_POINT_SPRITE:
 297       return true;
 298    case PIPE_CAP_MAX_RENDER_TARGETS:
 299       return ILO_MAX_DRAW_BUFFERS;
 300    case PIPE_CAP_OCCLUSION_QUERY:
 301    case PIPE_CAP_QUERY_TIME_ELAPSED:
 302    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 303    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 304       return true;
 305    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 306       /*
 307        * As defined in SURFACE_STATE, we have
 308        *
 309        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 310        *  GEN6           8192x8192x512            2048x2048x2048
 311        *  GEN7         16384x16384x2048           2048x2048x2048
 312        *
 313        * However, when the texutre size is large, things become unstable.  We
 314        * require the maximum texture size to be 2^30 bytes in
 315        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 316        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 317        * than 2^26 pixels.
 318        *
 319        * For 3D textures, we have to set the maximum number of levels to 9,
 320        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 321        * which has at most 2^26 pixels.  And for cube textures, we has to set
 322        * it to 12.
 323        */
 324       return 14;
 325    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 326       return 9;
 327    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 328       return 12;
 329    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 330       return false;
 331    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 332    case PIPE_CAP_SM3:
 333       return true;
 334    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 335       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 336          return 0;
 337       return ILO_MAX_SO_BUFFERS;
 338    case PIPE_CAP_PRIMITIVE_RESTART:
 339       return true;
 340    case PIPE_CAP_INDEP_BLEND_ENABLE:
 341    case PIPE_CAP_INDEP_BLEND_FUNC:
 342       return true;
 343    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 344       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 345    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 346    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 347    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 348    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 349    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 350       return true;
 351    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 352       return false;
 353    case PIPE_CAP_TGSI_INSTANCEID:
 354    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 355       return true;
 356    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 357       return false;
 358    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 359       return true;
 360    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 361    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 362       return true;
 363    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 364    case PIPE_CAP_MIN_TEXEL_OFFSET:
 365       return -8;
 366    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 367    case PIPE_CAP_MAX_TEXEL_OFFSET:
 368       return 7;
 369    case PIPE_CAP_CONDITIONAL_RENDER:
 370    case PIPE_CAP_TEXTURE_BARRIER:
 371       return true;
 372    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 373       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 374    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 375       return ILO_MAX_SO_BINDINGS;
 376    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 377    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 378    case PIPE_CAP_MAX_VERTEX_STREAMS:
 379       return 0;
 380    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 381       if (is->dev.gen >= ILO_GEN(7))
 382          return is->dev.has_gen7_sol_reset;
 383       else
 384          return false; /* TODO */
 385    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 386       return false;
 387    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 388       return true;
 389    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 390       return false;
 391    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 392       return 140;
 393    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 394    case PIPE_CAP_USER_VERTEX_BUFFERS:
 395       return false;
 396    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 397    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 398    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 399       return false;
 400    case PIPE_CAP_COMPUTE:
 401       return false; /* TODO */
 402    case PIPE_CAP_USER_INDEX_BUFFERS:
 403    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 404       return true;
 405    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 406       /* imposed by OWord (Dual) Block Read */
 407       return 16;
 408    case PIPE_CAP_START_INSTANCE:
 409       return true;
 410    case PIPE_CAP_QUERY_TIMESTAMP:
 411       return is->dev.has_timestamp;
 412    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 413       return false; /* TODO */
 414    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 415       return 64;
 416    case PIPE_CAP_CUBE_MAP_ARRAY:
 417    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 418       return true;
 419    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 420       return 1;
 421    case PIPE_CAP_TGSI_TEXCOORD:
 422       return false;
 423    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 424    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 425       return true;
 426    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 427       return 0;
 428    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 429       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 430       return 1 << 27;
 431    case PIPE_CAP_MAX_VIEWPORTS:
 432       return ILO_MAX_VIEWPORTS;
 433    case PIPE_CAP_ENDIANNESS:
 434       return PIPE_ENDIAN_LITTLE;
 435    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 436       return true;
 437    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 438    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 439    case PIPE_CAP_TEXTURE_GATHER_SM5:
 440    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 441    case PIPE_CAP_FAKE_SW_MSAA:
 442    case PIPE_CAP_TEXTURE_QUERY_LOD:
 443    case PIPE_CAP_SAMPLE_SHADING:
 444    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 445    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 446       return 0;
 447
 448    default:
 449       return 0;
 450    }
 451 }
 452
 453 static const char *
 454 ilo_get_vendor(struct pipe_screen *screen)
 455 {
 456    return "LunarG, Inc.";
 457 }
 458
 459 static const char *
 460 ilo_get_name(struct pipe_screen *screen)
 461 {
 462    struct ilo_screen *is = ilo_screen(screen);
 463    const char *chipset = NULL;
 464
 465    if (gen_is_vlv(is->dev.devid)) {
 466       chipset = "Intel(R) Bay Trail";
 467    }
 468    else if (gen_is_hsw(is->dev.devid)) {
 469       if (gen_is_desktop(is->dev.devid))
 470          chipset = "Intel(R) Haswell Desktop";
 471       else if (gen_is_mobile(is->dev.devid))
 472          chipset = "Intel(R) Haswell Mobile";
 473       else if (gen_is_server(is->dev.devid))
 474          chipset = "Intel(R) Haswell Server";
 475    }
 476    else if (gen_is_ivb(is->dev.devid)) {
 477       if (gen_is_desktop(is->dev.devid))
 478          chipset = "Intel(R) Ivybridge Desktop";
 479       else if (gen_is_mobile(is->dev.devid))
 480          chipset = "Intel(R) Ivybridge Mobile";
 481       else if (gen_is_server(is->dev.devid))
 482          chipset = "Intel(R) Ivybridge Server";
 483    }
 484    else if (gen_is_snb(is->dev.devid)) {
 485       if (gen_is_desktop(is->dev.devid))
 486          chipset = "Intel(R) Sandybridge Desktop";
 487       else if (gen_is_mobile(is->dev.devid))
 488          chipset = "Intel(R) Sandybridge Mobile";
 489       else if (gen_is_server(is->dev.devid))
 490          chipset = "Intel(R) Sandybridge Server";
 491    }
 492
 493    if (!chipset)
 494       chipset = "Unknown Intel Chipset";
 495
 496    return chipset;
 497 }
 498
 499 static uint64_t
 500 ilo_get_timestamp(struct pipe_screen *screen)
 501 {
 502    struct ilo_screen *is = ilo_screen(screen);
 503    union {
 504       uint64_t val;
 505       uint32_t dw[2];
 506    } timestamp;
 507
 508    intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 509
 510    /*
 511     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 512     *
 513     *     "Note: This timestamp register reflects the value of the PCU TSC.
 514     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 515     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 516     *      hours)."
 517     *
 518     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 519     * of the timestamp.  We will have to live with a timestamp that rolls over
 520     * every ~343 seconds.
 521     *
 522     * See also brw_get_timestamp().
 523     */
 524    return (uint64_t) timestamp.dw[1] * 80;
 525 }
 526
 527 static void
 528 ilo_fence_reference(struct pipe_screen *screen,
 529                     struct pipe_fence_handle **p,
 530                     struct pipe_fence_handle *f)
 531 {
 532    struct ilo_fence *fence = ilo_fence(f);
 533    struct ilo_fence *old;
 534
 535    if (likely(p)) {
 536       old = ilo_fence(*p);
 537       *p = f;
 538    }
 539    else {
 540       old = NULL;
 541    }
 542
 543    STATIC_ASSERT(&((struct ilo_fence *) NULL)->reference == NULL);
 544    if (pipe_reference(&old->reference, &fence->reference)) {
 545       if (old->bo)
 546          intel_bo_unreference(old->bo);
 547       FREE(old);
 548    }
 549 }
 550
 551 static boolean
 552 ilo_fence_signalled(struct pipe_screen *screen,
 553                     struct pipe_fence_handle *f)
 554 {
 555    struct ilo_fence *fence = ilo_fence(f);
 556
 557    /* mark signalled if the bo is idle */
 558    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 559       intel_bo_unreference(fence->bo);
 560       fence->bo = NULL;
 561    }
 562
 563    return (fence->bo == NULL);
 564 }
 565
 566 static boolean
 567 ilo_fence_finish(struct pipe_screen *screen,
 568                  struct pipe_fence_handle *f,
 569                  uint64_t timeout)
 570 {
 571    struct ilo_fence *fence = ilo_fence(f);
 572    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 573
 574    /* already signalled */
 575    if (!fence->bo)
 576       return true;
 577
 578    /* wait and see if it returns error */
 579    if (intel_bo_wait(fence->bo, wait_timeout))
 580       return false;
 581
 582    /* mark signalled */
 583    intel_bo_unreference(fence->bo);
 584    fence->bo = NULL;
 585
 586    return true;
 587 }
 588
 589 static void
 590 ilo_screen_destroy(struct pipe_screen *screen)
 591 {
 592    struct ilo_screen *is = ilo_screen(screen);
 593
 594    /* as it seems, winsys is owned by the screen */
 595    intel_winsys_destroy(is->winsys);
 596
 597    FREE(is);
 598 }
 599
 600 static bool
 601 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 602 {
 603    dev->devid = info->devid;
 604    dev->max_batch_size = info->max_batch_size;
 605    dev->has_llc = info->has_llc;
 606    dev->has_address_swizzling = info->has_address_swizzling;
 607    dev->has_logical_context = info->has_logical_context;
 608    dev->has_ppgtt = info->has_ppgtt;
 609    dev->has_timestamp = info->has_timestamp;
 610    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 611
 612    if (!dev->has_logical_context) {
 613       ilo_err("missing hardware logical context support\n");
 614       return false;
 615    }
 616
 617    /*
 618     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 619     * writes on GEN6.
 620     *
 621     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 622     *
 623     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 624     *      code is in a secure environment, independent of address space.
 625     *      Under this condition, this bit only specifies the address space
 626     *      (GGTT or PPGTT). All commands are executed "as-is""
 627     *
 628     * We need PPGTT to be enabled on GEN6 too.
 629     */
 630    if (!dev->has_ppgtt) {
 631       /* experiments show that it does not really matter... */
 632       ilo_warn("PPGTT disabled\n");
 633    }
 634
 635    /*
 636     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 637     *
 638     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 639     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 640     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 641     *      to an EU GRF register. Read/write access to the URB is generally
 642     *      supported on a row-granular basis."
 643     *
 644     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 645     *
 646     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 647     *      128k        4096        2048
 648     *      256k        8096        4096"
 649     */
 650
 651    if (gen_is_hsw(info->devid)) {
 652       dev->gen = ILO_GEN(7.5);
 653       dev->gt = gen_get_hsw_gt(info->devid);
 654       dev->urb_size = ((dev->gt == 3) ? 512 :
 655                        (dev->gt == 2) ? 256 : 128) * 1024;
 656    }
 657    else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 658       dev->gen = ILO_GEN(7);
 659       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 660       dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
 661    }
 662    else if (gen_is_snb(info->devid)) {
 663       dev->gen = ILO_GEN(6);
 664       dev->gt = gen_get_snb_gt(info->devid);
 665       dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
 666    }
 667    else {
 668       ilo_err("unknown GPU generation\n");
 669       return false;
 670    }
 671
 672    return true;
 673 }
 674
 675 struct pipe_screen *
 676 ilo_screen_create(struct intel_winsys *ws)
 677 {
 678    struct ilo_screen *is;
 679    const struct intel_winsys_info *info;
 680
 681    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 682
 683    is = CALLOC_STRUCT(ilo_screen);
 684    if (!is)
 685       return NULL;
 686
 687    is->winsys = ws;
 688
 689    info = intel_winsys_get_info(is->winsys);
 690    if (!init_dev(&is->dev, info)) {
 691       FREE(is);
 692       return NULL;
 693    }
 694
 695    util_format_s3tc_init();
 696
 697    is->base.destroy = ilo_screen_destroy;
 698    is->base.get_name = ilo_get_name;
 699    is->base.get_vendor = ilo_get_vendor;
 700    is->base.get_param = ilo_get_param;
 701    is->base.get_paramf = ilo_get_paramf;
 702    is->base.get_shader_param = ilo_get_shader_param;
 703    is->base.get_video_param = ilo_get_video_param;
 704    is->base.get_compute_param = ilo_get_compute_param;
 705
 706    is->base.get_timestamp = ilo_get_timestamp;
 707
 708    is->base.flush_frontbuffer = NULL;
 709
 710    is->base.fence_reference = ilo_fence_reference;
 711    is->base.fence_signalled = ilo_fence_signalled;
 712    is->base.fence_finish = ilo_fence_finish;
 713
 714    is->base.get_driver_query_info = NULL;
 715
 716    ilo_init_format_functions(is);
 717    ilo_init_context_functions(is);
 718    ilo_init_resource_functions(is);
 719
 720    return &is->base;
 721 }