2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "os/os_misc.h"
29 #include "util/u_format_s3tc.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
33 #include "intel_winsys.h"
35 #include "ilo_context.h"
36 #include "ilo_format.h"
37 #include "ilo_resource.h"
38 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
39 #include "ilo_public.h"
40 #include "ilo_screen.h"
44 static const struct debug_named_value ilo_debug_flags
[] = {
45 { "3d", ILO_DEBUG_3D
, "Dump 3D commands and states" },
46 { "vs", ILO_DEBUG_VS
, "Dump vertex shaders" },
47 { "gs", ILO_DEBUG_GS
, "Dump geometry shaders" },
48 { "fs", ILO_DEBUG_FS
, "Dump fragment shaders" },
49 { "cs", ILO_DEBUG_CS
, "Dump compute shaders" },
50 { "draw", ILO_DEBUG_DRAW
, "Show draw information" },
51 { "flush", ILO_DEBUG_FLUSH
, "Show batch buffer flushes" },
52 { "nohw", ILO_DEBUG_NOHW
, "Do not send commands to HW" },
53 { "nocache", ILO_DEBUG_NOCACHE
, "Always invalidate HW caches" },
54 { "nohiz", ILO_DEBUG_NOHIZ
, "Disable HiZ" },
59 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
62 case PIPE_CAPF_MAX_LINE_WIDTH
:
63 /* in U3.7, defined in 3DSTATE_SF */
65 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
66 /* line width minus one, which is reserved for AA region */
68 case PIPE_CAPF_MAX_POINT_WIDTH
:
69 /* in U8.3, defined in 3DSTATE_SF */
71 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
72 /* same as point width, as we ignore rasterizer->point_smooth */
74 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
75 /* [2.0, 16.0], defined in SAMPLER_STATE */
77 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
78 /* [-16.0, 16.0), defined in SAMPLER_STATE */
80 case PIPE_CAPF_GUARD_BAND_LEFT
:
81 case PIPE_CAPF_GUARD_BAND_TOP
:
82 case PIPE_CAPF_GUARD_BAND_RIGHT
:
83 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
84 /* what are these for? */
93 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
94 enum pipe_shader_cap param
)
97 case PIPE_SHADER_FRAGMENT
:
98 case PIPE_SHADER_VERTEX
:
99 case PIPE_SHADER_GEOMETRY
:
106 /* the limits are copied from the classic driver */
107 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
108 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
109 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
110 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
111 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
112 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
113 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
114 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
115 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
117 case PIPE_SHADER_CAP_MAX_INPUTS
:
118 /* this is limited by how many attributes SF can remap */
120 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
121 return 1024 * sizeof(float[4]);
122 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
123 return ILO_MAX_CONST_BUFFERS
;
124 case PIPE_SHADER_CAP_MAX_TEMPS
:
126 case PIPE_SHADER_CAP_MAX_PREDS
:
128 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
130 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
132 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
134 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
135 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
136 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
138 case PIPE_SHADER_CAP_SUBROUTINES
:
140 case PIPE_SHADER_CAP_INTEGERS
:
142 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
143 return ILO_MAX_SAMPLERS
;
144 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
145 return ILO_MAX_SAMPLER_VIEWS
;
146 case PIPE_SHADER_CAP_PREFERRED_IR
:
147 return PIPE_SHADER_IR_TGSI
;
148 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
157 ilo_get_video_param(struct pipe_screen
*screen
,
158 enum pipe_video_profile profile
,
159 enum pipe_video_entrypoint entrypoint
,
160 enum pipe_video_cap param
)
163 case PIPE_VIDEO_CAP_SUPPORTED
:
164 return vl_profile_supported(screen
, profile
, entrypoint
);
165 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
167 case PIPE_VIDEO_CAP_MAX_WIDTH
:
168 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
169 return vl_video_buffer_max_size(screen
);
170 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
171 return PIPE_FORMAT_NV12
;
172 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
174 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
176 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
178 case PIPE_VIDEO_CAP_MAX_LEVEL
:
179 return vl_level_supported(screen
, profile
);
186 ilo_get_compute_param(struct pipe_screen
*screen
,
187 enum pipe_compute_cap param
,
191 const char *ir_target
;
192 uint64_t grid_dimension
;
193 uint64_t max_grid_size
[3];
194 uint64_t max_block_size
[3];
195 uint64_t max_threads_per_block
;
196 uint64_t max_global_size
;
197 uint64_t max_local_size
;
198 uint64_t max_private_size
;
199 uint64_t max_input_size
;
200 uint64_t max_mem_alloc_size
;
205 /* XXX some randomly chosen values */
207 case PIPE_COMPUTE_CAP_IR_TARGET
:
208 val
.ir_target
= "ilog";
211 size
= strlen(val
.ir_target
) + 1;
213 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
214 val
.grid_dimension
= Elements(val
.max_grid_size
);
216 ptr
= &val
.grid_dimension
;
217 size
= sizeof(val
.grid_dimension
);
219 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
220 val
.max_grid_size
[0] = 65535;
221 val
.max_grid_size
[1] = 65535;
222 val
.max_grid_size
[2] = 1;
224 ptr
= &val
.max_grid_size
;
225 size
= sizeof(val
.max_grid_size
);
227 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
228 val
.max_block_size
[0] = 512;
229 val
.max_block_size
[1] = 512;
230 val
.max_block_size
[2] = 512;
232 ptr
= &val
.max_block_size
;
233 size
= sizeof(val
.max_block_size
);
236 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
237 val
.max_threads_per_block
= 512;
239 ptr
= &val
.max_threads_per_block
;
240 size
= sizeof(val
.max_threads_per_block
);
242 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
243 val
.max_global_size
= 4;
245 ptr
= &val
.max_global_size
;
246 size
= sizeof(val
.max_global_size
);
248 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
249 val
.max_local_size
= 64 * 1024;
251 ptr
= &val
.max_local_size
;
252 size
= sizeof(val
.max_local_size
);
254 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
255 val
.max_private_size
= 32768;
257 ptr
= &val
.max_private_size
;
258 size
= sizeof(val
.max_private_size
);
260 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
261 val
.max_input_size
= 256;
263 ptr
= &val
.max_input_size
;
264 size
= sizeof(val
.max_input_size
);
266 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
267 val
.max_mem_alloc_size
= 128 * 1024 * 1024;
269 ptr
= &val
.max_mem_alloc_size
;
270 size
= sizeof(val
.max_mem_alloc_size
);
279 memcpy(ret
, ptr
, size
);
285 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
287 struct ilo_screen
*is
= ilo_screen(screen
);
290 case PIPE_CAP_NPOT_TEXTURES
:
291 case PIPE_CAP_TWO_SIDED_STENCIL
:
293 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
295 case PIPE_CAP_ANISOTROPIC_FILTER
:
296 case PIPE_CAP_POINT_SPRITE
:
298 case PIPE_CAP_MAX_RENDER_TARGETS
:
299 return ILO_MAX_DRAW_BUFFERS
;
300 case PIPE_CAP_OCCLUSION_QUERY
:
301 case PIPE_CAP_QUERY_TIME_ELAPSED
:
302 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
303 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
305 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
307 * As defined in SURFACE_STATE, we have
309 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
310 * GEN6 8192x8192x512 2048x2048x2048
311 * GEN7 16384x16384x2048 2048x2048x2048
313 return (is
->dev
.gen
>= ILO_GEN(7)) ? 15 : 14;
314 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
316 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
317 return (is
->dev
.gen
>= ILO_GEN(7)) ? 15 : 14;
318 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
320 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
323 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
324 if (is
->dev
.gen
>= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
326 return ILO_MAX_SO_BUFFERS
;
327 case PIPE_CAP_PRIMITIVE_RESTART
:
329 case PIPE_CAP_INDEP_BLEND_ENABLE
:
330 case PIPE_CAP_INDEP_BLEND_FUNC
:
332 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
333 return (is
->dev
.gen
>= ILO_GEN(7)) ? 2048 : 512;
334 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
335 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
336 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
337 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
338 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
340 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
342 case PIPE_CAP_TGSI_INSTANCEID
:
343 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
345 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
347 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
349 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
350 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
352 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
353 case PIPE_CAP_MIN_TEXEL_OFFSET
:
355 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
356 case PIPE_CAP_MAX_TEXEL_OFFSET
:
358 case PIPE_CAP_CONDITIONAL_RENDER
:
359 case PIPE_CAP_TEXTURE_BARRIER
:
361 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
362 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
363 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
364 return ILO_MAX_SO_BINDINGS
;
365 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
366 if (is
->dev
.gen
>= ILO_GEN(7))
367 return is
->dev
.has_gen7_sol_reset
;
369 return false; /* TODO */
370 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
372 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
374 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
376 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
378 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
379 case PIPE_CAP_USER_VERTEX_BUFFERS
:
381 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
382 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
383 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
385 case PIPE_CAP_COMPUTE
:
386 return false; /* TODO */
387 case PIPE_CAP_USER_INDEX_BUFFERS
:
388 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
390 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
391 /* imposed by OWord (Dual) Block Read */
393 case PIPE_CAP_START_INSTANCE
:
395 case PIPE_CAP_QUERY_TIMESTAMP
:
396 return is
->dev
.has_timestamp
;
397 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
398 return false; /* TODO */
399 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
400 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
401 case PIPE_CAP_CUBE_MAP_ARRAY
:
402 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
404 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
406 case PIPE_CAP_TGSI_TEXCOORD
:
408 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
409 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
411 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
413 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
414 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
416 case PIPE_CAP_MAX_VIEWPORTS
:
417 return ILO_MAX_VIEWPORTS
;
418 case PIPE_CAP_ENDIANNESS
:
419 return PIPE_ENDIAN_LITTLE
;
420 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
422 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
423 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
424 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
425 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
426 case PIPE_CAP_TEXTURE_GATHER_SM5
:
428 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
430 case PIPE_CAP_FAKE_SW_MSAA
:
431 case PIPE_CAP_TEXTURE_QUERY_LOD
:
432 case PIPE_CAP_SAMPLE_SHADING
:
433 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
434 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
435 case PIPE_CAP_MAX_VERTEX_STREAMS
:
436 case PIPE_CAP_DRAW_INDIRECT
:
437 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
440 case PIPE_CAP_VENDOR_ID
:
442 case PIPE_CAP_DEVICE_ID
:
443 return is
->dev
.devid
;
444 case PIPE_CAP_ACCELERATED
:
446 case PIPE_CAP_VIDEO_MEMORY
: {
447 /* Once a batch uses more than 75% of the maximum mappable size, we
448 * assume that there's some fragmentation, and we start doing extra
449 * flushing, etc. That's the big cliff apps will care about.
451 const int gpu_mappable_megabytes
=
452 intel_winsys_get_aperture_size(is
->winsys
) * 3 / 4;
453 uint64_t system_memory
;
455 if (!os_get_total_physical_memory(&system_memory
))
458 return MIN2(gpu_mappable_megabytes
, (int)(system_memory
>> 20));
469 ilo_get_vendor(struct pipe_screen
*screen
)
471 return "LunarG, Inc.";
475 ilo_get_name(struct pipe_screen
*screen
)
477 struct ilo_screen
*is
= ilo_screen(screen
);
478 const char *chipset
= NULL
;
480 if (gen_is_vlv(is
->dev
.devid
)) {
481 chipset
= "Intel(R) Bay Trail";
483 else if (gen_is_hsw(is
->dev
.devid
)) {
484 if (gen_is_desktop(is
->dev
.devid
))
485 chipset
= "Intel(R) Haswell Desktop";
486 else if (gen_is_mobile(is
->dev
.devid
))
487 chipset
= "Intel(R) Haswell Mobile";
488 else if (gen_is_server(is
->dev
.devid
))
489 chipset
= "Intel(R) Haswell Server";
491 else if (gen_is_ivb(is
->dev
.devid
)) {
492 if (gen_is_desktop(is
->dev
.devid
))
493 chipset
= "Intel(R) Ivybridge Desktop";
494 else if (gen_is_mobile(is
->dev
.devid
))
495 chipset
= "Intel(R) Ivybridge Mobile";
496 else if (gen_is_server(is
->dev
.devid
))
497 chipset
= "Intel(R) Ivybridge Server";
499 else if (gen_is_snb(is
->dev
.devid
)) {
500 if (gen_is_desktop(is
->dev
.devid
))
501 chipset
= "Intel(R) Sandybridge Desktop";
502 else if (gen_is_mobile(is
->dev
.devid
))
503 chipset
= "Intel(R) Sandybridge Mobile";
504 else if (gen_is_server(is
->dev
.devid
))
505 chipset
= "Intel(R) Sandybridge Server";
509 chipset
= "Unknown Intel Chipset";
515 ilo_get_timestamp(struct pipe_screen
*screen
)
517 struct ilo_screen
*is
= ilo_screen(screen
);
523 intel_winsys_read_reg(is
->winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
526 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
528 * "Note: This timestamp register reflects the value of the PCU TSC.
529 * The PCU TSC counts 10ns increments; this timestamp reflects bits
530 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
533 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
534 * of the timestamp. We will have to live with a timestamp that rolls over
535 * every ~343 seconds.
537 * See also brw_get_timestamp().
539 return (uint64_t) timestamp
.dw
[1] * 80;
543 ilo_fence_reference(struct pipe_screen
*screen
,
544 struct pipe_fence_handle
**p
,
545 struct pipe_fence_handle
*f
)
547 struct ilo_fence
*fence
= ilo_fence(f
);
548 struct ilo_fence
*old
;
558 STATIC_ASSERT(&((struct ilo_fence
*) NULL
)->reference
== NULL
);
559 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
561 intel_bo_unreference(old
->bo
);
567 ilo_fence_signalled(struct pipe_screen
*screen
,
568 struct pipe_fence_handle
*f
)
570 struct ilo_fence
*fence
= ilo_fence(f
);
572 /* mark signalled if the bo is idle */
573 if (fence
->bo
&& !intel_bo_is_busy(fence
->bo
)) {
574 intel_bo_unreference(fence
->bo
);
578 return (fence
->bo
== NULL
);
582 ilo_fence_finish(struct pipe_screen
*screen
,
583 struct pipe_fence_handle
*f
,
586 struct ilo_fence
*fence
= ilo_fence(f
);
587 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
589 /* already signalled */
593 /* wait and see if it returns error */
594 if (intel_bo_wait(fence
->bo
, wait_timeout
))
598 intel_bo_unreference(fence
->bo
);
605 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
606 * before waited on or checked.
609 ilo_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
611 struct ilo_fence
*fence
;
613 fence
= CALLOC_STRUCT(ilo_fence
);
617 pipe_reference_init(&fence
->reference
, 1);
620 intel_bo_reference(bo
);
627 ilo_screen_destroy(struct pipe_screen
*screen
)
629 struct ilo_screen
*is
= ilo_screen(screen
);
631 /* as it seems, winsys is owned by the screen */
632 intel_winsys_destroy(is
->winsys
);
638 init_dev(struct ilo_dev_info
*dev
, const struct intel_winsys_info
*info
)
640 dev
->devid
= info
->devid
;
641 dev
->max_batch_size
= info
->max_batch_size
;
642 dev
->has_llc
= info
->has_llc
;
643 dev
->has_address_swizzling
= info
->has_address_swizzling
;
644 dev
->has_logical_context
= info
->has_logical_context
;
645 dev
->has_ppgtt
= info
->has_ppgtt
;
646 dev
->has_timestamp
= info
->has_timestamp
;
647 dev
->has_gen7_sol_reset
= info
->has_gen7_sol_reset
;
649 if (!dev
->has_logical_context
) {
650 ilo_err("missing hardware logical context support\n");
655 * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
658 * From the Sandy Bridge PRM, volume 1 part 3, page 101:
660 * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
661 * code is in a secure environment, independent of address space.
662 * Under this condition, this bit only specifies the address space
663 * (GGTT or PPGTT). All commands are executed "as-is""
665 * We need PPGTT to be enabled on GEN6 too.
667 if (!dev
->has_ppgtt
) {
668 /* experiments show that it does not really matter... */
669 ilo_warn("PPGTT disabled\n");
673 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
675 * "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
676 * as 1024 256-bit rows. The GT2 product's URB provides 64KB of
677 * storage, arranged as 2048 256-bit rows. A row corresponds in size
678 * to an EU GRF register. Read/write access to the URB is generally
679 * supported on a row-granular basis."
681 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
683 * "URB Size URB Rows URB Rows when SLM Enabled
688 if (gen_is_hsw(info
->devid
)) {
689 dev
->gen
= ILO_GEN(7.5);
690 dev
->gt
= gen_get_hsw_gt(info
->devid
);
691 dev
->urb_size
= ((dev
->gt
== 3) ? 512 :
692 (dev
->gt
== 2) ? 256 : 128) * 1024;
694 else if (gen_is_ivb(info
->devid
) || gen_is_vlv(info
->devid
)) {
695 dev
->gen
= ILO_GEN(7);
696 dev
->gt
= (gen_is_ivb(info
->devid
)) ? gen_get_ivb_gt(info
->devid
) : 1;
697 dev
->urb_size
= ((dev
->gt
== 2) ? 256 : 128) * 1024;
699 else if (gen_is_snb(info
->devid
)) {
700 dev
->gen
= ILO_GEN(6);
701 dev
->gt
= gen_get_snb_gt(info
->devid
);
702 dev
->urb_size
= ((dev
->gt
== 2) ? 64 : 32) * 1024;
705 ilo_err("unknown GPU generation\n");
713 ilo_screen_create(struct intel_winsys
*ws
)
715 struct ilo_screen
*is
;
716 const struct intel_winsys_info
*info
;
718 ilo_debug
= debug_get_flags_option("ILO_DEBUG", ilo_debug_flags
, 0);
720 is
= CALLOC_STRUCT(ilo_screen
);
726 info
= intel_winsys_get_info(is
->winsys
);
727 if (!init_dev(&is
->dev
, info
)) {
732 util_format_s3tc_init();
734 is
->base
.destroy
= ilo_screen_destroy
;
735 is
->base
.get_name
= ilo_get_name
;
736 is
->base
.get_vendor
= ilo_get_vendor
;
737 is
->base
.get_param
= ilo_get_param
;
738 is
->base
.get_paramf
= ilo_get_paramf
;
739 is
->base
.get_shader_param
= ilo_get_shader_param
;
740 is
->base
.get_video_param
= ilo_get_video_param
;
741 is
->base
.get_compute_param
= ilo_get_compute_param
;
743 is
->base
.get_timestamp
= ilo_get_timestamp
;
745 is
->base
.flush_frontbuffer
= NULL
;
747 is
->base
.fence_reference
= ilo_fence_reference
;
748 is
->base
.fence_signalled
= ilo_fence_signalled
;
749 is
->base
.fence_finish
= ilo_fence_finish
;
751 is
->base
.get_driver_query_info
= NULL
;
753 ilo_init_format_functions(is
);
754 ilo_init_context_functions(is
);
755 ilo_init_resource_functions(is
);