src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_format_s3tc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "intel_chipset.h"
  32 #include "intel_reg.h" /* for TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_public.h"
  39 #include "ilo_screen.h"
  40
  41 int ilo_debug;
  42
  43 static const struct debug_named_value ilo_debug_flags[] = {
  44    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  50    { "flush",     ILO_DEBUG_FLUSH,    "Show batch buffer flushes" },
  51    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  52    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  53    DEBUG_NAMED_VALUE_END
  54 };
  55
  56 static float
  57 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  58 {
  59    switch (param) {
  60    case PIPE_CAPF_MAX_LINE_WIDTH:
  61       /* in U3.7, defined in 3DSTATE_SF */
  62       return 7.0f;
  63    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  64       /* line width minus one, which is reserved for AA region */
  65       return 6.0f;
  66    case PIPE_CAPF_MAX_POINT_WIDTH:
  67       /* in U8.3, defined in 3DSTATE_SF */
  68       return 255.0f;
  69    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  70       /* same as point width, as we ignore rasterizer->point_smooth */
  71       return 255.0f;
  72    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  73       /* [2.0, 16.0], defined in SAMPLER_STATE */
  74       return 16.0f;
  75    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  76       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  77       return 15.0f;
  78    case PIPE_CAPF_GUARD_BAND_LEFT:
  79    case PIPE_CAPF_GUARD_BAND_TOP:
  80    case PIPE_CAPF_GUARD_BAND_RIGHT:
  81    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  82       /* what are these for? */
  83       return 0.0f;
  84
  85    default:
  86       return 0.0f;
  87    }
  88 }
  89
  90 static int
  91 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  92                      enum pipe_shader_cap param)
  93 {
  94    switch (shader) {
  95    case PIPE_SHADER_FRAGMENT:
  96    case PIPE_SHADER_VERTEX:
  97    case PIPE_SHADER_GEOMETRY:
  98       break;
  99    default:
 100       return 0;
 101    }
 102
 103    switch (param) {
 104    /* the limits are copied from the classic driver */
 105    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 106       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 107    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 108       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 109    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 110       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 111    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 112       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 113    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 114       return UINT_MAX;
 115    case PIPE_SHADER_CAP_MAX_INPUTS:
 116       /* this is limited by how many attributes SF can remap */
 117       return 16;
 118    case PIPE_SHADER_CAP_MAX_CONSTS:
 119       return 1024;
 120    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 121       return ILO_MAX_CONST_BUFFERS;
 122    case PIPE_SHADER_CAP_MAX_TEMPS:
 123       return 256;
 124    case PIPE_SHADER_CAP_MAX_ADDRS:
 125       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 126    case PIPE_SHADER_CAP_MAX_PREDS:
 127       return 0;
 128    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 129       return 1;
 130    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 131       return 0;
 132    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133       return 0;
 134    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 135       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 136    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 137       return 1;
 138    case PIPE_SHADER_CAP_SUBROUTINES:
 139       return 0;
 140    case PIPE_SHADER_CAP_INTEGERS:
 141       return 1;
 142    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 143       return ILO_MAX_SAMPLERS;
 144    case PIPE_SHADER_CAP_PREFERRED_IR:
 145       return PIPE_SHADER_IR_TGSI;
 146    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 147       return 1;
 148
 149    default:
 150       return 0;
 151    }
 152 }
 153
 154 static int
 155 ilo_get_video_param(struct pipe_screen *screen,
 156                     enum pipe_video_profile profile,
 157                     enum pipe_video_entrypoint entrypoint,
 158                     enum pipe_video_cap param)
 159 {
 160    switch (param) {
 161    case PIPE_VIDEO_CAP_SUPPORTED:
 162       return vl_profile_supported(screen, profile, entrypoint);
 163    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 164       return 1;
 165    case PIPE_VIDEO_CAP_MAX_WIDTH:
 166    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 167       return vl_video_buffer_max_size(screen);
 168    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 169       return PIPE_FORMAT_NV12;
 170    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 171       return 1;
 172    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 173       return 1;
 174    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 175       return 0;
 176    case PIPE_VIDEO_CAP_MAX_LEVEL:
 177       return vl_level_supported(screen, profile);
 178    default:
 179       return 0;
 180    }
 181 }
 182
 183 static int
 184 ilo_get_compute_param(struct pipe_screen *screen,
 185                       enum pipe_compute_cap param,
 186                       void *ret)
 187 {
 188    union {
 189       const char *ir_target;
 190       uint64_t grid_dimension;
 191       uint64_t max_grid_size[3];
 192       uint64_t max_block_size[3];
 193       uint64_t max_threads_per_block;
 194       uint64_t max_global_size;
 195       uint64_t max_local_size;
 196       uint64_t max_private_size;
 197       uint64_t max_input_size;
 198       uint64_t max_mem_alloc_size;
 199    } val;
 200    const void *ptr;
 201    int size;
 202
 203    /* XXX some randomly chosen values */
 204    switch (param) {
 205    case PIPE_COMPUTE_CAP_IR_TARGET:
 206       val.ir_target = "ilog";
 207
 208       ptr = val.ir_target;
 209       size = strlen(val.ir_target) + 1;
 210       break;
 211    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 212       val.grid_dimension = Elements(val.max_grid_size);
 213
 214       ptr = &val.grid_dimension;
 215       size = sizeof(val.grid_dimension);
 216       break;
 217    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 218       val.max_grid_size[0] = 65535;
 219       val.max_grid_size[1] = 65535;
 220       val.max_grid_size[2] = 1;
 221
 222       ptr = &val.max_grid_size;
 223       size = sizeof(val.max_grid_size);
 224       break;
 225    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 226       val.max_block_size[0] = 512;
 227       val.max_block_size[1] = 512;
 228       val.max_block_size[2] = 512;
 229
 230       ptr = &val.max_block_size;
 231       size = sizeof(val.max_block_size);
 232       break;
 233
 234    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 235       val.max_threads_per_block = 512;
 236
 237       ptr = &val.max_threads_per_block;
 238       size = sizeof(val.max_threads_per_block);
 239       break;
 240    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 241       val.max_global_size = 4;
 242
 243       ptr = &val.max_global_size;
 244       size = sizeof(val.max_global_size);
 245       break;
 246    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 247       val.max_local_size = 64 * 1024;
 248
 249       ptr = &val.max_local_size;
 250       size = sizeof(val.max_local_size);
 251       break;
 252    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 253       val.max_private_size = 32768;
 254
 255       ptr = &val.max_private_size;
 256       size = sizeof(val.max_private_size);
 257       break;
 258    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 259       val.max_input_size = 256;
 260
 261       ptr = &val.max_input_size;
 262       size = sizeof(val.max_input_size);
 263       break;
 264    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 265       val.max_mem_alloc_size = 128 * 1024 * 1024;
 266
 267       ptr = &val.max_mem_alloc_size;
 268       size = sizeof(val.max_mem_alloc_size);
 269       break;
 270    default:
 271       ptr = NULL;
 272       size = 0;
 273       break;
 274    }
 275
 276    if (ret)
 277       memcpy(ret, ptr, size);
 278
 279    return size;
 280 }
 281
 282 static int
 283 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 284 {
 285    struct ilo_screen *is = ilo_screen(screen);
 286
 287    switch (param) {
 288    case PIPE_CAP_NPOT_TEXTURES:
 289    case PIPE_CAP_TWO_SIDED_STENCIL:
 290       return true;
 291    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 292       return 0; /* TODO */
 293    case PIPE_CAP_ANISOTROPIC_FILTER:
 294    case PIPE_CAP_POINT_SPRITE:
 295       return true;
 296    case PIPE_CAP_MAX_RENDER_TARGETS:
 297       return ILO_MAX_DRAW_BUFFERS;
 298    case PIPE_CAP_OCCLUSION_QUERY:
 299    case PIPE_CAP_QUERY_TIME_ELAPSED:
 300    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 301    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 302       return true;
 303    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 304       /*
 305        * As defined in SURFACE_STATE, we have
 306        *
 307        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 308        *  GEN6           8192x8192x512            2048x2048x2048
 309        *  GEN7         16384x16384x2048           2048x2048x2048
 310        *
 311        * However, when the texutre size is large, things become unstable.  We
 312        * require the maximum texture size to be 2^30 bytes in
 313        * screen->can_create_resource().  Since the maximum pixel size is 2^4
 314        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
 315        * than 2^26 pixels.
 316        *
 317        * For 3D textures, we have to set the maximum number of levels to 9,
 318        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
 319        * which has at most 2^26 pixels.  And for cube textures, we has to set
 320        * it to 12.
 321        */
 322       return 14;
 323    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 324       return 9;
 325    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 326       return 12;
 327    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 328       return false;
 329    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 330    case PIPE_CAP_SM3:
 331       return true;
 332    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 333       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 334          return 0;
 335       return ILO_MAX_SO_BUFFERS;
 336    case PIPE_CAP_PRIMITIVE_RESTART:
 337       return true;
 338    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 339       return ILO_MAX_SAMPLERS * 2;
 340    case PIPE_CAP_INDEP_BLEND_ENABLE:
 341    case PIPE_CAP_INDEP_BLEND_FUNC:
 342       return true;
 343    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 344       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 345    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 346    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 347    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 348    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 349    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 350       return true;
 351    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 352       return false;
 353    case PIPE_CAP_TGSI_INSTANCEID:
 354    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 355       return true;
 356    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 357       return false;
 358    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 359       return true;
 360    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 361    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 362    case PIPE_CAP_SCALED_RESOLVE:
 363       return true;
 364    case PIPE_CAP_MIN_TEXEL_OFFSET:
 365       return -8;
 366    case PIPE_CAP_MAX_TEXEL_OFFSET:
 367       return 7;
 368    case PIPE_CAP_CONDITIONAL_RENDER:
 369    case PIPE_CAP_TEXTURE_BARRIER:
 370       return true;
 371    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 372       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 373    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 374       return ILO_MAX_SO_BINDINGS;
 375    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 376       if (is->dev.gen >= ILO_GEN(7))
 377          return is->dev.has_gen7_sol_reset;
 378       else
 379          return false; /* TODO */
 380    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 381       return false;
 382    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 383       return true;
 384    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 385       return false;
 386    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 387       return 140;
 388    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 389    case PIPE_CAP_USER_VERTEX_BUFFERS:
 390       return false;
 391    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 392    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 393    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 394       return false;
 395    case PIPE_CAP_COMPUTE:
 396       return false; /* TODO */
 397    case PIPE_CAP_USER_INDEX_BUFFERS:
 398    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 399       return true;
 400    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 401       /* imposed by OWord (Dual) Block Read */
 402       return 16;
 403    case PIPE_CAP_START_INSTANCE:
 404    case PIPE_CAP_QUERY_TIMESTAMP:
 405       return true;
 406    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 407       return false; /* TODO */
 408    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 409       return 0;
 410    case PIPE_CAP_CUBE_MAP_ARRAY:
 411    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 412       return true;
 413    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 414       return 1;
 415    case PIPE_CAP_TGSI_TEXCOORD:
 416       return false;
 417    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 418       return true;
 419    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 420       return false; /* TODO */
 421    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 422       return 0;
 423    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 424       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
 425       return 1 << 27;
 426    case PIPE_CAP_MAX_VIEWPORTS:
 427       return ILO_MAX_VIEWPORTS;
 428    case PIPE_CAP_ENDIANNESS:
 429       return PIPE_ENDIAN_LITTLE;
 430
 431    default:
 432       return 0;
 433    }
 434 }
 435
 436 static const char *
 437 ilo_get_vendor(struct pipe_screen *screen)
 438 {
 439    return "LunarG, Inc.";
 440 }
 441
 442 static const char *
 443 ilo_get_name(struct pipe_screen *screen)
 444 {
 445    struct ilo_screen *is = ilo_screen(screen);
 446    const char *chipset;
 447
 448    /* stolen from classic i965 */
 449    switch (is->dev.devid) {
 450    case PCI_CHIP_SANDYBRIDGE_GT1:
 451    case PCI_CHIP_SANDYBRIDGE_GT2:
 452    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 453       chipset = "Intel(R) Sandybridge Desktop";
 454       break;
 455    case PCI_CHIP_SANDYBRIDGE_M_GT1:
 456    case PCI_CHIP_SANDYBRIDGE_M_GT2:
 457    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 458       chipset = "Intel(R) Sandybridge Mobile";
 459       break;
 460    case PCI_CHIP_SANDYBRIDGE_S:
 461       chipset = "Intel(R) Sandybridge Server";
 462       break;
 463    case PCI_CHIP_IVYBRIDGE_GT1:
 464    case PCI_CHIP_IVYBRIDGE_GT2:
 465       chipset = "Intel(R) Ivybridge Desktop";
 466       break;
 467    case PCI_CHIP_IVYBRIDGE_M_GT1:
 468    case PCI_CHIP_IVYBRIDGE_M_GT2:
 469       chipset = "Intel(R) Ivybridge Mobile";
 470       break;
 471    case PCI_CHIP_IVYBRIDGE_S_GT1:
 472    case PCI_CHIP_IVYBRIDGE_S_GT2:
 473       chipset = "Intel(R) Ivybridge Server";
 474       break;
 475    case PCI_CHIP_BAYTRAIL_M_1:
 476    case PCI_CHIP_BAYTRAIL_M_2:
 477    case PCI_CHIP_BAYTRAIL_M_3:
 478    case PCI_CHIP_BAYTRAIL_M_4:
 479    case PCI_CHIP_BAYTRAIL_D:
 480       chipset = "Intel(R) Bay Trail";
 481       break;
 482    case PCI_CHIP_HASWELL_GT1:
 483    case PCI_CHIP_HASWELL_GT2:
 484    case PCI_CHIP_HASWELL_GT3:
 485    case PCI_CHIP_HASWELL_SDV_GT1:
 486    case PCI_CHIP_HASWELL_SDV_GT2:
 487    case PCI_CHIP_HASWELL_SDV_GT3:
 488    case PCI_CHIP_HASWELL_ULT_GT1:
 489    case PCI_CHIP_HASWELL_ULT_GT2:
 490    case PCI_CHIP_HASWELL_ULT_GT3:
 491    case PCI_CHIP_HASWELL_CRW_GT1:
 492    case PCI_CHIP_HASWELL_CRW_GT2:
 493    case PCI_CHIP_HASWELL_CRW_GT3:
 494       chipset = "Intel(R) Haswell Desktop";
 495       break;
 496    case PCI_CHIP_HASWELL_M_GT1:
 497    case PCI_CHIP_HASWELL_M_GT2:
 498    case PCI_CHIP_HASWELL_M_GT3:
 499    case PCI_CHIP_HASWELL_SDV_M_GT1:
 500    case PCI_CHIP_HASWELL_SDV_M_GT2:
 501    case PCI_CHIP_HASWELL_SDV_M_GT3:
 502    case PCI_CHIP_HASWELL_ULT_M_GT1:
 503    case PCI_CHIP_HASWELL_ULT_M_GT2:
 504    case PCI_CHIP_HASWELL_ULT_M_GT3:
 505    case PCI_CHIP_HASWELL_CRW_M_GT1:
 506    case PCI_CHIP_HASWELL_CRW_M_GT2:
 507    case PCI_CHIP_HASWELL_CRW_M_GT3:
 508       chipset = "Intel(R) Haswell Mobile";
 509       break;
 510    case PCI_CHIP_HASWELL_S_GT1:
 511    case PCI_CHIP_HASWELL_S_GT2:
 512    case PCI_CHIP_HASWELL_S_GT3:
 513    case PCI_CHIP_HASWELL_SDV_S_GT1:
 514    case PCI_CHIP_HASWELL_SDV_S_GT2:
 515    case PCI_CHIP_HASWELL_SDV_S_GT3:
 516    case PCI_CHIP_HASWELL_ULT_S_GT1:
 517    case PCI_CHIP_HASWELL_ULT_S_GT2:
 518    case PCI_CHIP_HASWELL_ULT_S_GT3:
 519    case PCI_CHIP_HASWELL_CRW_S_GT1:
 520    case PCI_CHIP_HASWELL_CRW_S_GT2:
 521    case PCI_CHIP_HASWELL_CRW_S_GT3:
 522       chipset = "Intel(R) Haswell Server";
 523       break;
 524    default:
 525       chipset = "Unknown Intel Chipset";
 526       break;
 527    }
 528
 529    return chipset;
 530 }
 531
 532 static uint64_t
 533 ilo_get_timestamp(struct pipe_screen *screen)
 534 {
 535    struct ilo_screen *is = ilo_screen(screen);
 536    union {
 537       uint64_t val;
 538       uint32_t dw[2];
 539    } timestamp;
 540
 541    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 542
 543    /*
 544     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 545     *
 546     *     "Note: This timestamp register reflects the value of the PCU TSC.
 547     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 548     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 549     *      hours)."
 550     *
 551     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 552     * of the timestamp.  We will have to live with a timestamp that rolls over
 553     * every ~343 seconds.
 554     *
 555     * See also brw_get_timestamp().
 556     */
 557    return (uint64_t) timestamp.dw[1] * 80;
 558 }
 559
 560 static void
 561 ilo_fence_reference(struct pipe_screen *screen,
 562                     struct pipe_fence_handle **p,
 563                     struct pipe_fence_handle *f)
 564 {
 565    struct ilo_fence **ptr = (struct ilo_fence **) p;
 566    struct ilo_fence *fence = ilo_fence(f);
 567
 568    if (!ptr) {
 569       /* still need to reference fence */
 570       if (fence)
 571          pipe_reference(NULL, &fence->reference);
 572       return;
 573    }
 574
 575    /* reference fence and dereference the one pointed to by ptr */
 576    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
 577       struct ilo_fence *old = *ptr;
 578
 579       if (old->bo)
 580          intel_bo_unreference(old->bo);
 581       FREE(old);
 582    }
 583
 584    *ptr = fence;
 585 }
 586
 587 static boolean
 588 ilo_fence_signalled(struct pipe_screen *screen,
 589                     struct pipe_fence_handle *f)
 590 {
 591    struct ilo_fence *fence = ilo_fence(f);
 592
 593    /* mark signalled if the bo is idle */
 594    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 595       intel_bo_unreference(fence->bo);
 596       fence->bo = NULL;
 597    }
 598
 599    return (fence->bo == NULL);
 600 }
 601
 602 static boolean
 603 ilo_fence_finish(struct pipe_screen *screen,
 604                  struct pipe_fence_handle *f,
 605                  uint64_t timeout)
 606 {
 607    struct ilo_fence *fence = ilo_fence(f);
 608    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 609
 610    /* already signalled */
 611    if (!fence->bo)
 612       return true;
 613
 614    /* wait and see if it returns error */
 615    if (intel_bo_wait(fence->bo, wait_timeout))
 616       return false;
 617
 618    /* mark signalled */
 619    intel_bo_unreference(fence->bo);
 620    fence->bo = NULL;
 621
 622    return true;
 623 }
 624
 625 static void
 626 ilo_screen_destroy(struct pipe_screen *screen)
 627 {
 628    struct ilo_screen *is = ilo_screen(screen);
 629
 630    /* as it seems, winsys is owned by the screen */
 631    intel_winsys_destroy(is->winsys);
 632
 633    FREE(is);
 634 }
 635
 636 static bool
 637 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 638 {
 639    dev->devid = info->devid;
 640    dev->has_llc = info->has_llc;
 641    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 642    dev->has_address_swizzling = info->has_address_swizzling;
 643
 644    /*
 645     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 646     *
 647     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 648     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 649     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 650     *      to an EU GRF register. Read/write access to the URB is generally
 651     *      supported on a row-granular basis."
 652     *
 653     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 654     *
 655     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 656     *      128k        4096        2048
 657     *      256k        8096        4096"
 658     */
 659
 660    if (IS_HASWELL(info->devid)) {
 661       dev->gen = ILO_GEN(7.5);
 662
 663       if (IS_HSW_GT3(info->devid)) {
 664          dev->gt = 3;
 665          dev->urb_size = 512 * 1024;
 666       }
 667       else if (IS_HSW_GT2(info->devid)) {
 668          dev->gt = 2;
 669          dev->urb_size = 256 * 1024;
 670       }
 671       else {
 672          dev->gt = 1;
 673          dev->urb_size = 128 * 1024;
 674       }
 675    }
 676    else if (IS_GEN7(info->devid)) {
 677       dev->gen = ILO_GEN(7);
 678
 679       if (IS_IVB_GT2(info->devid)) {
 680          dev->gt = 2;
 681          dev->urb_size = 256 * 1024;
 682       }
 683       else {
 684          dev->gt = 1;
 685          dev->urb_size = 128 * 1024;
 686       }
 687    }
 688    else if (IS_GEN6(info->devid)) {
 689       dev->gen = ILO_GEN(6);
 690
 691       if (IS_SNB_GT2(info->devid)) {
 692          dev->gt = 2;
 693          dev->urb_size = 64 * 1024;
 694       }
 695       else {
 696          dev->gt = 1;
 697          dev->urb_size = 32 * 1024;
 698       }
 699    }
 700    else {
 701       ilo_err("unknown GPU generation\n");
 702       return false;
 703    }
 704
 705    return true;
 706 }
 707
 708 struct pipe_screen *
 709 ilo_screen_create(struct intel_winsys *ws)
 710 {
 711    struct ilo_screen *is;
 712    const struct intel_winsys_info *info;
 713
 714    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 715
 716    is = CALLOC_STRUCT(ilo_screen);
 717    if (!is)
 718       return NULL;
 719
 720    is->winsys = ws;
 721
 722    intel_winsys_enable_reuse(is->winsys);
 723
 724    info = intel_winsys_get_info(is->winsys);
 725    if (!init_dev(&is->dev, info)) {
 726       FREE(is);
 727       return NULL;
 728    }
 729
 730    util_format_s3tc_init();
 731
 732    is->base.destroy = ilo_screen_destroy;
 733    is->base.get_name = ilo_get_name;
 734    is->base.get_vendor = ilo_get_vendor;
 735    is->base.get_param = ilo_get_param;
 736    is->base.get_paramf = ilo_get_paramf;
 737    is->base.get_shader_param = ilo_get_shader_param;
 738    is->base.get_video_param = ilo_get_video_param;
 739    is->base.get_compute_param = ilo_get_compute_param;
 740
 741    is->base.get_timestamp = ilo_get_timestamp;
 742
 743    is->base.flush_frontbuffer = NULL;
 744
 745    is->base.fence_reference = ilo_fence_reference;
 746    is->base.fence_signalled = ilo_fence_signalled;
 747    is->base.fence_finish = ilo_fence_finish;
 748
 749    is->base.get_driver_query_info = NULL;
 750
 751    ilo_init_format_functions(is);
 752    ilo_init_context_functions(is);
 753    ilo_init_resource_functions(is);
 754
 755    return &is->base;
 756 }