src/gallium/drivers/ilo/ilo_screen.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "os/os_misc.h"
  29 #include "util/u_format_s3tc.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
  33 #include "intel_winsys.h"
  34
  35 #include "ilo_context.h"
  36 #include "ilo_format.h"
  37 #include "ilo_resource.h"
  38 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
  39 #include "ilo_public.h"
  40 #include "ilo_screen.h"
  41
  42 int ilo_debug;
  43
  44 static const struct debug_named_value ilo_debug_flags[] = {
  45    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  46    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  47    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  48    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  49    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  50    { "draw",      ILO_DEBUG_DRAW,     "Show draw information" },
  51    { "flush",     ILO_DEBUG_FLUSH,    "Show batch buffer flushes" },
  52    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  53    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  54    { "nohiz",     ILO_DEBUG_NOHIZ,    "Disable HiZ" },
  55    DEBUG_NAMED_VALUE_END
  56 };
  57
  58 static float
  59 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  60 {
  61    switch (param) {
  62    case PIPE_CAPF_MAX_LINE_WIDTH:
  63       /* in U3.7, defined in 3DSTATE_SF */
  64       return 7.0f;
  65    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  66       /* line width minus one, which is reserved for AA region */
  67       return 6.0f;
  68    case PIPE_CAPF_MAX_POINT_WIDTH:
  69       /* in U8.3, defined in 3DSTATE_SF */
  70       return 255.0f;
  71    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  72       /* same as point width, as we ignore rasterizer->point_smooth */
  73       return 255.0f;
  74    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  75       /* [2.0, 16.0], defined in SAMPLER_STATE */
  76       return 16.0f;
  77    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  78       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  79       return 15.0f;
  80    case PIPE_CAPF_GUARD_BAND_LEFT:
  81    case PIPE_CAPF_GUARD_BAND_TOP:
  82    case PIPE_CAPF_GUARD_BAND_RIGHT:
  83    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  84       /* what are these for? */
  85       return 0.0f;
  86
  87    default:
  88       return 0.0f;
  89    }
  90 }
  91
  92 static int
  93 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  94                      enum pipe_shader_cap param)
  95 {
  96    switch (shader) {
  97    case PIPE_SHADER_FRAGMENT:
  98    case PIPE_SHADER_VERTEX:
  99    case PIPE_SHADER_GEOMETRY:
 100       break;
 101    default:
 102       return 0;
 103    }
 104
 105    switch (param) {
 106    /* the limits are copied from the classic driver */
 107    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 108       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
 109    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 110       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 111    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 112       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 113    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 114       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
 115    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 116       return UINT_MAX;
 117    case PIPE_SHADER_CAP_MAX_INPUTS:
 118       /* this is limited by how many attributes SF can remap */
 119       return 16;
 120    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 121       return 1024 * sizeof(float[4]);
 122    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 123       return ILO_MAX_CONST_BUFFERS;
 124    case PIPE_SHADER_CAP_MAX_TEMPS:
 125       return 256;
 126    case PIPE_SHADER_CAP_MAX_PREDS:
 127       return 0;
 128    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 129       return 1;
 130    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 131       return 0;
 132    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133       return 0;
 134    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 135       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
 136    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 137       return 1;
 138    case PIPE_SHADER_CAP_SUBROUTINES:
 139       return 0;
 140    case PIPE_SHADER_CAP_INTEGERS:
 141       return 1;
 142    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 143       return ILO_MAX_SAMPLERS;
 144    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 145       return ILO_MAX_SAMPLER_VIEWS;
 146    case PIPE_SHADER_CAP_PREFERRED_IR:
 147       return PIPE_SHADER_IR_TGSI;
 148    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 149       return 1;
 150
 151    default:
 152       return 0;
 153    }
 154 }
 155
 156 static int
 157 ilo_get_video_param(struct pipe_screen *screen,
 158                     enum pipe_video_profile profile,
 159                     enum pipe_video_entrypoint entrypoint,
 160                     enum pipe_video_cap param)
 161 {
 162    switch (param) {
 163    case PIPE_VIDEO_CAP_SUPPORTED:
 164       return vl_profile_supported(screen, profile, entrypoint);
 165    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 166       return 1;
 167    case PIPE_VIDEO_CAP_MAX_WIDTH:
 168    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 169       return vl_video_buffer_max_size(screen);
 170    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 171       return PIPE_FORMAT_NV12;
 172    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 173       return 1;
 174    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 175       return 1;
 176    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 177       return 0;
 178    case PIPE_VIDEO_CAP_MAX_LEVEL:
 179       return vl_level_supported(screen, profile);
 180    default:
 181       return 0;
 182    }
 183 }
 184
 185 static int
 186 ilo_get_compute_param(struct pipe_screen *screen,
 187                       enum pipe_compute_cap param,
 188                       void *ret)
 189 {
 190    union {
 191       const char *ir_target;
 192       uint64_t grid_dimension;
 193       uint64_t max_grid_size[3];
 194       uint64_t max_block_size[3];
 195       uint64_t max_threads_per_block;
 196       uint64_t max_global_size;
 197       uint64_t max_local_size;
 198       uint64_t max_private_size;
 199       uint64_t max_input_size;
 200       uint64_t max_mem_alloc_size;
 201    } val;
 202    const void *ptr;
 203    int size;
 204
 205    /* XXX some randomly chosen values */
 206    switch (param) {
 207    case PIPE_COMPUTE_CAP_IR_TARGET:
 208       val.ir_target = "ilog";
 209
 210       ptr = val.ir_target;
 211       size = strlen(val.ir_target) + 1;
 212       break;
 213    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 214       val.grid_dimension = Elements(val.max_grid_size);
 215
 216       ptr = &val.grid_dimension;
 217       size = sizeof(val.grid_dimension);
 218       break;
 219    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 220       val.max_grid_size[0] = 65535;
 221       val.max_grid_size[1] = 65535;
 222       val.max_grid_size[2] = 1;
 223
 224       ptr = &val.max_grid_size;
 225       size = sizeof(val.max_grid_size);
 226       break;
 227    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 228       val.max_block_size[0] = 512;
 229       val.max_block_size[1] = 512;
 230       val.max_block_size[2] = 512;
 231
 232       ptr = &val.max_block_size;
 233       size = sizeof(val.max_block_size);
 234       break;
 235
 236    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 237       val.max_threads_per_block = 512;
 238
 239       ptr = &val.max_threads_per_block;
 240       size = sizeof(val.max_threads_per_block);
 241       break;
 242    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 243       val.max_global_size = 4;
 244
 245       ptr = &val.max_global_size;
 246       size = sizeof(val.max_global_size);
 247       break;
 248    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 249       val.max_local_size = 64 * 1024;
 250
 251       ptr = &val.max_local_size;
 252       size = sizeof(val.max_local_size);
 253       break;
 254    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 255       val.max_private_size = 32768;
 256
 257       ptr = &val.max_private_size;
 258       size = sizeof(val.max_private_size);
 259       break;
 260    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 261       val.max_input_size = 256;
 262
 263       ptr = &val.max_input_size;
 264       size = sizeof(val.max_input_size);
 265       break;
 266    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 267       val.max_mem_alloc_size = 128 * 1024 * 1024;
 268
 269       ptr = &val.max_mem_alloc_size;
 270       size = sizeof(val.max_mem_alloc_size);
 271       break;
 272    default:
 273       ptr = NULL;
 274       size = 0;
 275       break;
 276    }
 277
 278    if (ret)
 279       memcpy(ret, ptr, size);
 280
 281    return size;
 282 }
 283
 284 static int
 285 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
 286 {
 287    struct ilo_screen *is = ilo_screen(screen);
 288
 289    switch (param) {
 290    case PIPE_CAP_NPOT_TEXTURES:
 291    case PIPE_CAP_TWO_SIDED_STENCIL:
 292       return true;
 293    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 294       return 0; /* TODO */
 295    case PIPE_CAP_ANISOTROPIC_FILTER:
 296    case PIPE_CAP_POINT_SPRITE:
 297       return true;
 298    case PIPE_CAP_MAX_RENDER_TARGETS:
 299       return ILO_MAX_DRAW_BUFFERS;
 300    case PIPE_CAP_OCCLUSION_QUERY:
 301    case PIPE_CAP_QUERY_TIME_ELAPSED:
 302    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 303    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
 304       return true;
 305    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 306       /*
 307        * As defined in SURFACE_STATE, we have
 308        *
 309        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
 310        *  GEN6           8192x8192x512            2048x2048x2048
 311        *  GEN7         16384x16384x2048           2048x2048x2048
 312        */
 313       return (is->dev.gen >= ILO_GEN(7)) ? 15 : 14;
 314    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 315       return 12;
 316    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 317       return (is->dev.gen >= ILO_GEN(7)) ? 15 : 14;
 318    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 319       return false;
 320    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 321    case PIPE_CAP_SM3:
 322       return true;
 323    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 324       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
 325          return 0;
 326       return ILO_MAX_SO_BUFFERS;
 327    case PIPE_CAP_PRIMITIVE_RESTART:
 328       return true;
 329    case PIPE_CAP_INDEP_BLEND_ENABLE:
 330    case PIPE_CAP_INDEP_BLEND_FUNC:
 331       return true;
 332    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 333       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
 334    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 335    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 336    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 337    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 338    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 339       return true;
 340    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 341       return false;
 342    case PIPE_CAP_TGSI_INSTANCEID:
 343    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 344       return true;
 345    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 346       return false;
 347    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 348       return true;
 349    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 350    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 351       return true;
 352    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 353    case PIPE_CAP_MIN_TEXEL_OFFSET:
 354       return -8;
 355    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 356    case PIPE_CAP_MAX_TEXEL_OFFSET:
 357       return 7;
 358    case PIPE_CAP_CONDITIONAL_RENDER:
 359    case PIPE_CAP_TEXTURE_BARRIER:
 360       return true;
 361    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 362       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
 363    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 364       return ILO_MAX_SO_BINDINGS;
 365    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 366       if (is->dev.gen >= ILO_GEN(7))
 367          return is->dev.has_gen7_sol_reset;
 368       else
 369          return false; /* TODO */
 370    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 371       return false;
 372    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 373       return true;
 374    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 375       return false;
 376    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 377       return 140;
 378    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 379    case PIPE_CAP_USER_VERTEX_BUFFERS:
 380       return false;
 381    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 382    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 383    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 384       return false;
 385    case PIPE_CAP_COMPUTE:
 386       return false; /* TODO */
 387    case PIPE_CAP_USER_INDEX_BUFFERS:
 388    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 389       return true;
 390    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 391       /* imposed by OWord (Dual) Block Read */
 392       return 16;
 393    case PIPE_CAP_START_INSTANCE:
 394       return true;
 395    case PIPE_CAP_QUERY_TIMESTAMP:
 396       return is->dev.has_timestamp;
 397    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 398       return false; /* TODO */
 399    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 400       return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
 401    case PIPE_CAP_CUBE_MAP_ARRAY:
 402    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 403       return true;
 404    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 405       return 1;
 406    case PIPE_CAP_TGSI_TEXCOORD:
 407       return false;
 408    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 409    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 410       return true;
 411    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 412       return 0;
 413    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 414       /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
 415       return 1 << 27;
 416    case PIPE_CAP_MAX_VIEWPORTS:
 417       return ILO_MAX_VIEWPORTS;
 418    case PIPE_CAP_ENDIANNESS:
 419       return PIPE_ENDIAN_LITTLE;
 420    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 421       return true;
 422    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 423    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 424    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 425    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 426    case PIPE_CAP_TEXTURE_GATHER_SM5:
 427       return 0;
 428    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 429       return true;
 430    case PIPE_CAP_FAKE_SW_MSAA:
 431    case PIPE_CAP_TEXTURE_QUERY_LOD:
 432    case PIPE_CAP_SAMPLE_SHADING:
 433    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 434    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 435    case PIPE_CAP_MAX_VERTEX_STREAMS:
 436    case PIPE_CAP_DRAW_INDIRECT:
 437    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 438       return 0;
 439
 440    case PIPE_CAP_VENDOR_ID:
 441       return 0x8086;
 442    case PIPE_CAP_DEVICE_ID:
 443       return is->dev.devid;
 444    case PIPE_CAP_ACCELERATED:
 445       return true;
 446    case PIPE_CAP_VIDEO_MEMORY: {
 447       /* Once a batch uses more than 75% of the maximum mappable size, we
 448        * assume that there's some fragmentation, and we start doing extra
 449        * flushing, etc.  That's the big cliff apps will care about.
 450        */
 451       const uint64_t gpu_mappable_megabytes = is->dev.aperture_total * 3 / 4;
 452       uint64_t system_memory;
 453
 454       if (!os_get_total_physical_memory(&system_memory))
 455          return 0;
 456
 457       return MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20));
 458    }
 459    case PIPE_CAP_UMA:
 460       return true;
 461
 462    default:
 463       return 0;
 464    }
 465 }
 466
 467 static const char *
 468 ilo_get_vendor(struct pipe_screen *screen)
 469 {
 470    return "LunarG, Inc.";
 471 }
 472
 473 static const char *
 474 ilo_get_name(struct pipe_screen *screen)
 475 {
 476    struct ilo_screen *is = ilo_screen(screen);
 477    const char *chipset = NULL;
 478
 479    if (gen_is_vlv(is->dev.devid)) {
 480       chipset = "Intel(R) Bay Trail";
 481    }
 482    else if (gen_is_hsw(is->dev.devid)) {
 483       if (gen_is_desktop(is->dev.devid))
 484          chipset = "Intel(R) Haswell Desktop";
 485       else if (gen_is_mobile(is->dev.devid))
 486          chipset = "Intel(R) Haswell Mobile";
 487       else if (gen_is_server(is->dev.devid))
 488          chipset = "Intel(R) Haswell Server";
 489    }
 490    else if (gen_is_ivb(is->dev.devid)) {
 491       if (gen_is_desktop(is->dev.devid))
 492          chipset = "Intel(R) Ivybridge Desktop";
 493       else if (gen_is_mobile(is->dev.devid))
 494          chipset = "Intel(R) Ivybridge Mobile";
 495       else if (gen_is_server(is->dev.devid))
 496          chipset = "Intel(R) Ivybridge Server";
 497    }
 498    else if (gen_is_snb(is->dev.devid)) {
 499       if (gen_is_desktop(is->dev.devid))
 500          chipset = "Intel(R) Sandybridge Desktop";
 501       else if (gen_is_mobile(is->dev.devid))
 502          chipset = "Intel(R) Sandybridge Mobile";
 503       else if (gen_is_server(is->dev.devid))
 504          chipset = "Intel(R) Sandybridge Server";
 505    }
 506
 507    if (!chipset)
 508       chipset = "Unknown Intel Chipset";
 509
 510    return chipset;
 511 }
 512
 513 static uint64_t
 514 ilo_get_timestamp(struct pipe_screen *screen)
 515 {
 516    struct ilo_screen *is = ilo_screen(screen);
 517    union {
 518       uint64_t val;
 519       uint32_t dw[2];
 520    } timestamp;
 521
 522    intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);
 523
 524    /*
 525     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
 526     *
 527     *     "Note: This timestamp register reflects the value of the PCU TSC.
 528     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
 529     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
 530     *      hours)."
 531     *
 532     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
 533     * of the timestamp.  We will have to live with a timestamp that rolls over
 534     * every ~343 seconds.
 535     *
 536     * See also brw_get_timestamp().
 537     */
 538    return (uint64_t) timestamp.dw[1] * 80;
 539 }
 540
 541 static void
 542 ilo_fence_reference(struct pipe_screen *screen,
 543                     struct pipe_fence_handle **p,
 544                     struct pipe_fence_handle *f)
 545 {
 546    struct ilo_fence *fence = ilo_fence(f);
 547    struct ilo_fence *old;
 548
 549    if (likely(p)) {
 550       old = ilo_fence(*p);
 551       *p = f;
 552    }
 553    else {
 554       old = NULL;
 555    }
 556
 557    STATIC_ASSERT(&((struct ilo_fence *) NULL)->reference == NULL);
 558    if (pipe_reference(&old->reference, &fence->reference)) {
 559       if (old->bo)
 560          intel_bo_unreference(old->bo);
 561       FREE(old);
 562    }
 563 }
 564
 565 static boolean
 566 ilo_fence_signalled(struct pipe_screen *screen,
 567                     struct pipe_fence_handle *f)
 568 {
 569    struct ilo_fence *fence = ilo_fence(f);
 570
 571    /* mark signalled if the bo is idle */
 572    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
 573       intel_bo_unreference(fence->bo);
 574       fence->bo = NULL;
 575    }
 576
 577    return (fence->bo == NULL);
 578 }
 579
 580 static boolean
 581 ilo_fence_finish(struct pipe_screen *screen,
 582                  struct pipe_fence_handle *f,
 583                  uint64_t timeout)
 584 {
 585    struct ilo_fence *fence = ilo_fence(f);
 586    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
 587
 588    /* already signalled */
 589    if (!fence->bo)
 590       return true;
 591
 592    /* wait and see if it returns error */
 593    if (intel_bo_wait(fence->bo, wait_timeout))
 594       return false;
 595
 596    /* mark signalled */
 597    intel_bo_unreference(fence->bo);
 598    fence->bo = NULL;
 599
 600    return true;
 601 }
 602
 603 /**
 604  * Create a fence for \p bo.  When \p bo is not NULL, it must be submitted
 605  * before waited on or checked.
 606  */
 607 struct ilo_fence *
 608 ilo_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
 609 {
 610    struct ilo_fence *fence;
 611
 612    fence = CALLOC_STRUCT(ilo_fence);
 613    if (!fence)
 614       return NULL;
 615
 616    pipe_reference_init(&fence->reference, 1);
 617
 618    if (bo)
 619       intel_bo_reference(bo);
 620    fence->bo = bo;
 621
 622    return fence;
 623 }
 624
 625 static void
 626 ilo_screen_destroy(struct pipe_screen *screen)
 627 {
 628    struct ilo_screen *is = ilo_screen(screen);
 629
 630    /* as it seems, winsys is owned by the screen */
 631    intel_winsys_destroy(is->winsys);
 632
 633    FREE(is);
 634 }
 635
 636 static bool
 637 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 638 {
 639    dev->devid = info->devid;
 640    dev->aperture_total = info->aperture_total;
 641    dev->aperture_mappable = info->aperture_mappable;
 642    dev->max_batch_size = info->max_batch_size;
 643    dev->has_llc = info->has_llc;
 644    dev->has_address_swizzling = info->has_address_swizzling;
 645    dev->has_logical_context = info->has_logical_context;
 646    dev->has_ppgtt = info->has_ppgtt;
 647    dev->has_timestamp = info->has_timestamp;
 648    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
 649
 650    if (!dev->has_logical_context) {
 651       ilo_err("missing hardware logical context support\n");
 652       return false;
 653    }
 654
 655    /*
 656     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
 657     * writes on GEN6.
 658     *
 659     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
 660     *
 661     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
 662     *      code is in a secure environment, independent of address space.
 663     *      Under this condition, this bit only specifies the address space
 664     *      (GGTT or PPGTT). All commands are executed "as-is""
 665     *
 666     * We need PPGTT to be enabled on GEN6 too.
 667     */
 668    if (!dev->has_ppgtt) {
 669       /* experiments show that it does not really matter... */
 670       ilo_warn("PPGTT disabled\n");
 671    }
 672
 673    /*
 674     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
 675     *
 676     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
 677     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
 678     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
 679     *      to an EU GRF register. Read/write access to the URB is generally
 680     *      supported on a row-granular basis."
 681     *
 682     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
 683     *
 684     *     "URB Size    URB Rows    URB Rows when SLM Enabled
 685     *      128k        4096        2048
 686     *      256k        8096        4096"
 687     */
 688
 689    if (gen_is_hsw(info->devid)) {
 690       dev->gen = ILO_GEN(7.5);
 691       dev->gt = gen_get_hsw_gt(info->devid);
 692       dev->urb_size = ((dev->gt == 3) ? 512 :
 693                        (dev->gt == 2) ? 256 : 128) * 1024;
 694    }
 695    else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
 696       dev->gen = ILO_GEN(7);
 697       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
 698       dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
 699    }
 700    else if (gen_is_snb(info->devid)) {
 701       dev->gen = ILO_GEN(6);
 702       dev->gt = gen_get_snb_gt(info->devid);
 703       dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
 704    }
 705    else {
 706       ilo_err("unknown GPU generation\n");
 707       return false;
 708    }
 709
 710    return true;
 711 }
 712
 713 struct pipe_screen *
 714 ilo_screen_create(struct intel_winsys *ws)
 715 {
 716    struct ilo_screen *is;
 717    const struct intel_winsys_info *info;
 718
 719    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
 720
 721    is = CALLOC_STRUCT(ilo_screen);
 722    if (!is)
 723       return NULL;
 724
 725    is->winsys = ws;
 726
 727    info = intel_winsys_get_info(is->winsys);
 728    if (!init_dev(&is->dev, info)) {
 729       FREE(is);
 730       return NULL;
 731    }
 732
 733    util_format_s3tc_init();
 734
 735    is->base.destroy = ilo_screen_destroy;
 736    is->base.get_name = ilo_get_name;
 737    is->base.get_vendor = ilo_get_vendor;
 738    is->base.get_param = ilo_get_param;
 739    is->base.get_paramf = ilo_get_paramf;
 740    is->base.get_shader_param = ilo_get_shader_param;
 741    is->base.get_video_param = ilo_get_video_param;
 742    is->base.get_compute_param = ilo_get_compute_param;
 743
 744    is->base.get_timestamp = ilo_get_timestamp;
 745
 746    is->base.flush_frontbuffer = NULL;
 747
 748    is->base.fence_reference = ilo_fence_reference;
 749    is->base.fence_signalled = ilo_fence_signalled;
 750    is->base.fence_finish = ilo_fence_finish;
 751
 752    is->base.get_driver_query_info = NULL;
 753
 754    ilo_init_format_functions(is);
 755    ilo_init_context_functions(is);
 756    ilo_init_resource_functions(is);
 757
 758    return &is->base;
 759 }