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ilo: update outdated gen assertions for Gen8
[mesa.git] / src / gallium / drivers / ilo / ilo_state_3d_bottom.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2012-2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_half.h"
32
33 #include "ilo_context.h"
34 #include "ilo_format.h"
35 #include "ilo_resource.h"
36 #include "ilo_shader.h"
37 #include "ilo_state.h"
38 #include "ilo_state_3d.h"
39
40 static void
41 rasterizer_init_clip(const struct ilo_dev_info *dev,
42 const struct pipe_rasterizer_state *state,
43 struct ilo_rasterizer_clip *clip)
44 {
45 uint32_t dw1, dw2, dw3;
46
47 ILO_DEV_ASSERT(dev, 6, 8);
48
49 dw1 = GEN6_CLIP_DW1_STATISTICS;
50
51 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
52 /*
53 * From the Ivy Bridge PRM, volume 2 part 1, page 219:
54 *
55 * "Workaround : Due to Hardware issue "EarlyCull" needs to be
56 * enabled only for the cases where the incoming primitive topology
57 * into the clipper guaranteed to be Trilist."
58 *
59 * What does this mean?
60 */
61 dw1 |= 0 << 19 |
62 GEN7_CLIP_DW1_EARLY_CULL_ENABLE;
63
64 if (ilo_dev_gen(dev) < ILO_GEN(8)) {
65 if (state->front_ccw)
66 dw1 |= GEN7_CLIP_DW1_FRONTWINDING_CCW;
67
68 switch (state->cull_face) {
69 case PIPE_FACE_NONE:
70 dw1 |= GEN7_CLIP_DW1_CULLMODE_NONE;
71 break;
72 case PIPE_FACE_FRONT:
73 dw1 |= GEN7_CLIP_DW1_CULLMODE_FRONT;
74 break;
75 case PIPE_FACE_BACK:
76 dw1 |= GEN7_CLIP_DW1_CULLMODE_BACK;
77 break;
78 case PIPE_FACE_FRONT_AND_BACK:
79 dw1 |= GEN7_CLIP_DW1_CULLMODE_BOTH;
80 break;
81 }
82 }
83 }
84
85 dw2 = GEN6_CLIP_DW2_CLIP_ENABLE |
86 GEN6_CLIP_DW2_XY_TEST_ENABLE |
87 state->clip_plane_enable << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
88 GEN6_CLIP_DW2_CLIPMODE_NORMAL;
89
90 if (state->clip_halfz)
91 dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
92 else
93 dw2 |= GEN6_CLIP_DW2_APIMODE_OGL;
94
95 if (ilo_dev_gen(dev) < ILO_GEN(8) && state->depth_clip)
96 dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE;
97
98 if (state->flatshade_first) {
99 dw2 |= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
100 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
101 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
102 }
103 else {
104 dw2 |= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
105 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
106 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
107 }
108
109 dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT |
110 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT;
111
112 clip->payload[0] = dw1;
113 clip->payload[1] = dw2;
114 clip->payload[2] = dw3;
115
116 clip->can_enable_guardband = true;
117
118 /*
119 * There are several reasons that guard band test should be disabled
120 *
121 * - GL wide points (to avoid partially visibie object)
122 * - GL wide or AA lines (to avoid partially visibie object)
123 */
124 if (state->point_size_per_vertex || state->point_size > 1.0f)
125 clip->can_enable_guardband = false;
126 if (state->line_smooth || state->line_width > 1.0f)
127 clip->can_enable_guardband = false;
128 }
129
130 static void
131 rasterizer_init_sf_depth_offset_gen6(const struct ilo_dev_info *dev,
132 const struct pipe_rasterizer_state *state,
133 struct ilo_rasterizer_sf *sf)
134 {
135 ILO_DEV_ASSERT(dev, 6, 8);
136
137 /*
138 * Scale the constant term. The minimum representable value used by the HW
139 * is not large enouch to be the minimum resolvable difference.
140 */
141 sf->dw_depth_offset_const = fui(state->offset_units * 2.0f);
142 sf->dw_depth_offset_scale = fui(state->offset_scale);
143 sf->dw_depth_offset_clamp = fui(state->offset_clamp);
144 }
145
146 static void
147 rasterizer_init_sf_gen6(const struct ilo_dev_info *dev,
148 const struct pipe_rasterizer_state *state,
149 struct ilo_rasterizer_sf *sf)
150 {
151 int line_width, point_width;
152 uint32_t dw1, dw2, dw3;
153
154 ILO_DEV_ASSERT(dev, 6, 7.5);
155
156 /*
157 * From the Sandy Bridge PRM, volume 2 part 1, page 248:
158 *
159 * "This bit (Statistics Enable) should be set whenever clipping is
160 * enabled and the Statistics Enable bit is set in CLIP_STATE. It
161 * should be cleared if clipping is disabled or Statistics Enable in
162 * CLIP_STATE is clear."
163 */
164 dw1 = GEN7_SF_DW1_STATISTICS |
165 GEN7_SF_DW1_VIEWPORT_ENABLE;
166
167 /* XXX GEN6 path seems to work fine for GEN7 */
168 if (false && ilo_dev_gen(dev) >= ILO_GEN(7)) {
169 /*
170 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
171 *
172 * "This bit (Legacy Global Depth Bias Enable, Global Depth Offset
173 * Enable Solid , Global Depth Offset Enable Wireframe, and Global
174 * Depth Offset Enable Point) should be set whenever non zero depth
175 * bias (Slope, Bias) values are used. Setting this bit may have
176 * some degradation of performance for some workloads."
177 */
178 if (state->offset_tri || state->offset_line || state->offset_point) {
179 /* XXX need to scale offset_const according to the depth format */
180 dw1 |= GEN7_SF_DW1_LEGACY_DEPTH_OFFSET;
181
182 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID |
183 GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME |
184 GEN7_SF_DW1_DEPTH_OFFSET_POINT;
185 }
186 } else {
187 if (state->offset_tri)
188 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID;
189 if (state->offset_line)
190 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME;
191 if (state->offset_point)
192 dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_POINT;
193 }
194
195 switch (state->fill_front) {
196 case PIPE_POLYGON_MODE_FILL:
197 dw1 |= GEN7_SF_DW1_FRONTFACE_SOLID;
198 break;
199 case PIPE_POLYGON_MODE_LINE:
200 dw1 |= GEN7_SF_DW1_FRONTFACE_WIREFRAME;
201 break;
202 case PIPE_POLYGON_MODE_POINT:
203 dw1 |= GEN7_SF_DW1_FRONTFACE_POINT;
204 break;
205 }
206
207 switch (state->fill_back) {
208 case PIPE_POLYGON_MODE_FILL:
209 dw1 |= GEN7_SF_DW1_BACKFACE_SOLID;
210 break;
211 case PIPE_POLYGON_MODE_LINE:
212 dw1 |= GEN7_SF_DW1_BACKFACE_WIREFRAME;
213 break;
214 case PIPE_POLYGON_MODE_POINT:
215 dw1 |= GEN7_SF_DW1_BACKFACE_POINT;
216 break;
217 }
218
219 if (state->front_ccw)
220 dw1 |= GEN7_SF_DW1_FRONTWINDING_CCW;
221
222 dw2 = 0;
223
224 if (state->line_smooth) {
225 /*
226 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
227 *
228 * "This field (Anti-aliasing Enable) must be disabled if any of the
229 * render targets have integer (UINT or SINT) surface format."
230 *
231 * From the Sandy Bridge PRM, volume 2 part 1, page 317:
232 *
233 * "This field (Hierarchical Depth Buffer Enable) must be disabled
234 * if Anti-aliasing Enable in 3DSTATE_SF is enabled.
235 *
236 * TODO We do not check those yet.
237 */
238 dw2 |= GEN7_SF_DW2_AA_LINE_ENABLE |
239 GEN7_SF_DW2_AA_LINE_CAP_1_0;
240 }
241
242 switch (state->cull_face) {
243 case PIPE_FACE_NONE:
244 dw2 |= GEN7_SF_DW2_CULLMODE_NONE;
245 break;
246 case PIPE_FACE_FRONT:
247 dw2 |= GEN7_SF_DW2_CULLMODE_FRONT;
248 break;
249 case PIPE_FACE_BACK:
250 dw2 |= GEN7_SF_DW2_CULLMODE_BACK;
251 break;
252 case PIPE_FACE_FRONT_AND_BACK:
253 dw2 |= GEN7_SF_DW2_CULLMODE_BOTH;
254 break;
255 }
256
257 /*
258 * Smooth lines should intersect ceil(line_width) or (ceil(line_width) + 1)
259 * pixels in the minor direction. We have to make the lines slightly
260 * thicker, 0.5 pixel on both sides, so that they intersect that many
261 * pixels are considered into the lines.
262 *
263 * Line width is in U3.7.
264 */
265 line_width = (int)
266 ((state->line_width + (float) state->line_smooth) * 128.0f + 0.5f);
267 line_width = CLAMP(line_width, 0, 1023);
268
269 /* use GIQ rules */
270 if (line_width == 128 && !state->line_smooth)
271 line_width = 0;
272
273 dw2 |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
274
275 if (ilo_dev_gen(dev) == ILO_GEN(7.5) && state->line_stipple_enable)
276 dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE;
277
278 if (state->scissor)
279 dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
280
281 dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
282 GEN7_SF_DW3_SUBPIXEL_8BITS;
283
284 if (state->line_last_pixel)
285 dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
286
287 if (state->flatshade_first) {
288 dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
289 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
290 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
291 } else {
292 dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
293 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
294 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
295 }
296
297 if (!state->point_size_per_vertex)
298 dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH;
299
300 /* in U8.3 */
301 point_width = (int) (state->point_size * 8.0f + 0.5f);
302 point_width = CLAMP(point_width, 1, 2047);
303
304 dw3 |= point_width;
305
306 STATIC_ASSERT(Elements(sf->payload) >= 3);
307 sf->payload[0] = dw1;
308 sf->payload[1] = dw2;
309 sf->payload[2] = dw3;
310
311 if (state->multisample) {
312 sf->dw_msaa = GEN7_SF_DW2_MSRASTMODE_ON_PATTERN;
313
314 /*
315 * From the Sandy Bridge PRM, volume 2 part 1, page 251:
316 *
317 * "Software must not program a value of 0.0 when running in
318 * MSRASTMODE_ON_xxx modes - zero-width lines are not available
319 * when multisampling rasterization is enabled."
320 */
321 if (!line_width) {
322 line_width = 128; /* 1.0f */
323
324 sf->dw_msaa |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
325 }
326 } else {
327 sf->dw_msaa = 0;
328 }
329
330 rasterizer_init_sf_depth_offset_gen6(dev, state, sf);
331 /* 3DSTATE_RASTER is Gen8+ only */
332 sf->dw_raster = 0;
333 }
334
335 static uint32_t
336 rasterizer_get_sf_raster_gen8(const struct ilo_dev_info *dev,
337 const struct pipe_rasterizer_state *state)
338 {
339 uint32_t dw = 0;
340
341 ILO_DEV_ASSERT(dev, 8, 8);
342
343 if (state->front_ccw)
344 dw |= GEN8_RASTER_DW1_FRONTWINDING_CCW;
345
346 switch (state->cull_face) {
347 case PIPE_FACE_NONE:
348 dw |= GEN8_RASTER_DW1_CULLMODE_NONE;
349 break;
350 case PIPE_FACE_FRONT:
351 dw |= GEN8_RASTER_DW1_CULLMODE_FRONT;
352 break;
353 case PIPE_FACE_BACK:
354 dw |= GEN8_RASTER_DW1_CULLMODE_BACK;
355 break;
356 case PIPE_FACE_FRONT_AND_BACK:
357 dw |= GEN8_RASTER_DW1_CULLMODE_BOTH;
358 break;
359 }
360
361 if (state->point_smooth)
362 dw |= GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE;
363
364 if (state->multisample)
365 dw |= GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE;
366
367 if (state->offset_tri)
368 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID;
369 if (state->offset_line)
370 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME;
371 if (state->offset_point)
372 dw|= GEN8_RASTER_DW1_DEPTH_OFFSET_POINT;
373
374 switch (state->fill_front) {
375 case PIPE_POLYGON_MODE_FILL:
376 dw |= GEN8_RASTER_DW1_FRONTFACE_SOLID;
377 break;
378 case PIPE_POLYGON_MODE_LINE:
379 dw |= GEN8_RASTER_DW1_FRONTFACE_WIREFRAME;
380 break;
381 case PIPE_POLYGON_MODE_POINT:
382 dw |= GEN8_RASTER_DW1_FRONTFACE_POINT;
383 break;
384 }
385
386 switch (state->fill_back) {
387 case PIPE_POLYGON_MODE_FILL:
388 dw |= GEN8_RASTER_DW1_BACKFACE_SOLID;
389 break;
390 case PIPE_POLYGON_MODE_LINE:
391 dw |= GEN8_RASTER_DW1_BACKFACE_WIREFRAME;
392 break;
393 case PIPE_POLYGON_MODE_POINT:
394 dw |= GEN8_RASTER_DW1_BACKFACE_POINT;
395 break;
396 }
397
398 if (state->line_smooth)
399 dw |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
400
401 if (state->scissor)
402 dw |= GEN8_RASTER_DW1_SCISSOR_ENABLE;
403
404 if (state->depth_clip)
405 dw |= GEN8_RASTER_DW1_Z_TEST_ENABLE;
406
407 return dw;
408 }
409
410 static void
411 rasterizer_init_sf_gen8(const struct ilo_dev_info *dev,
412 const struct pipe_rasterizer_state *state,
413 struct ilo_rasterizer_sf *sf)
414 {
415 int line_width, point_width;
416 uint32_t dw1, dw2, dw3;
417
418 ILO_DEV_ASSERT(dev, 8, 8);
419
420 /* in U3.7 */
421 line_width = (int)
422 ((state->line_width + (float) state->line_smooth) * 128.0f + 0.5f);
423 line_width = CLAMP(line_width, 0, 1023);
424
425 /* use GIQ rules */
426 if (line_width == 128 && !state->line_smooth)
427 line_width = 0;
428
429 /* in U8.3 */
430 point_width = (int) (state->point_size * 8.0f + 0.5f);
431 point_width = CLAMP(point_width, 1, 2047);
432
433 dw1 = GEN7_SF_DW1_STATISTICS |
434 GEN7_SF_DW1_VIEWPORT_ENABLE;
435
436 dw2 = line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
437 if (state->line_smooth)
438 dw2 |= GEN7_SF_DW2_AA_LINE_CAP_1_0;
439
440 dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
441 GEN7_SF_DW3_SUBPIXEL_8BITS |
442 point_width;
443
444 if (state->line_last_pixel)
445 dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
446
447 if (state->flatshade_first) {
448 dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
449 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
450 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
451 } else {
452 dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
453 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
454 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
455 }
456
457 if (!state->point_size_per_vertex)
458 dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH;
459
460 dw3 |= point_width;
461
462 STATIC_ASSERT(Elements(sf->payload) >= 3);
463 sf->payload[0] = dw1;
464 sf->payload[1] = dw2;
465 sf->payload[2] = dw3;
466
467 rasterizer_init_sf_depth_offset_gen6(dev, state, sf);
468
469 sf->dw_msaa = 0;
470 sf->dw_raster = rasterizer_get_sf_raster_gen8(dev, state);
471 }
472
473 static void
474 rasterizer_init_wm_gen6(const struct ilo_dev_info *dev,
475 const struct pipe_rasterizer_state *state,
476 struct ilo_rasterizer_wm *wm)
477 {
478 uint32_t dw5, dw6;
479
480 ILO_DEV_ASSERT(dev, 6, 6);
481
482 /* only the FF unit states are set, as in GEN7 */
483
484 dw5 = GEN6_WM_DW5_AA_LINE_WIDTH_2_0;
485
486 /* same value as in 3DSTATE_SF */
487 if (state->line_smooth)
488 dw5 |= GEN6_WM_DW5_AA_LINE_CAP_1_0;
489
490 if (state->poly_stipple_enable)
491 dw5 |= GEN6_WM_DW5_POLY_STIPPLE_ENABLE;
492 if (state->line_stipple_enable)
493 dw5 |= GEN6_WM_DW5_LINE_STIPPLE_ENABLE;
494
495 /*
496 * assertion that makes sure
497 *
498 * dw6 |= wm->dw_msaa_rast | wm->dw_msaa_disp;
499 *
500 * is valid
501 */
502 STATIC_ASSERT(GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL == 0 &&
503 GEN6_WM_DW6_MSDISPMODE_PERSAMPLE == 0);
504 dw6 = GEN6_WM_DW6_ZW_INTERP_PIXEL;
505
506 if (state->bottom_edge_rule)
507 dw6 |= GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT;
508
509 wm->dw_msaa_rast =
510 (state->multisample) ? GEN6_WM_DW6_MSRASTMODE_ON_PATTERN : 0;
511 wm->dw_msaa_disp = GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
512
513 STATIC_ASSERT(Elements(wm->payload) >= 2);
514 wm->payload[0] = dw5;
515 wm->payload[1] = dw6;
516 }
517
518 static void
519 rasterizer_init_wm_gen7(const struct ilo_dev_info *dev,
520 const struct pipe_rasterizer_state *state,
521 struct ilo_rasterizer_wm *wm)
522 {
523 uint32_t dw1, dw2;
524
525 ILO_DEV_ASSERT(dev, 7, 7.5);
526
527 /*
528 * assertion that makes sure
529 *
530 * dw1 |= wm->dw_msaa_rast;
531 * dw2 |= wm->dw_msaa_disp;
532 *
533 * is valid
534 */
535 STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL == 0 &&
536 GEN7_WM_DW2_MSDISPMODE_PERSAMPLE == 0);
537 dw1 = GEN7_WM_DW1_ZW_INTERP_PIXEL |
538 GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
539 dw2 = 0;
540
541 /* same value as in 3DSTATE_SF */
542 if (state->line_smooth)
543 dw1 |= GEN7_WM_DW1_AA_LINE_CAP_1_0;
544
545 if (state->poly_stipple_enable)
546 dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
547 if (state->line_stipple_enable)
548 dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
549
550 if (state->bottom_edge_rule)
551 dw1 |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
552
553 wm->dw_msaa_rast =
554 (state->multisample) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN : 0;
555 wm->dw_msaa_disp = GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
556
557 STATIC_ASSERT(Elements(wm->payload) >= 2);
558 wm->payload[0] = dw1;
559 wm->payload[1] = dw2;
560 }
561
562 static uint32_t
563 rasterizer_get_wm_gen8(const struct ilo_dev_info *dev,
564 const struct pipe_rasterizer_state *state)
565 {
566 uint32_t dw;
567
568 ILO_DEV_ASSERT(dev, 8, 8);
569
570 dw = GEN7_WM_DW1_ZW_INTERP_PIXEL |
571 GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
572
573 /* same value as in 3DSTATE_SF */
574 if (state->line_smooth)
575 dw |= GEN7_WM_DW1_AA_LINE_CAP_1_0;
576
577 if (state->poly_stipple_enable)
578 dw |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
579 if (state->line_stipple_enable)
580 dw |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
581
582 if (state->bottom_edge_rule)
583 dw |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
584
585 return dw;
586 }
587
588 void
589 ilo_gpe_init_rasterizer(const struct ilo_dev_info *dev,
590 const struct pipe_rasterizer_state *state,
591 struct ilo_rasterizer_state *rasterizer)
592 {
593 rasterizer_init_clip(dev, state, &rasterizer->clip);
594
595 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
596 memset(&rasterizer->wm, 0, sizeof(rasterizer->wm));
597 rasterizer->wm.payload[0] = rasterizer_get_wm_gen8(dev, state);
598
599 rasterizer_init_sf_gen8(dev, state, &rasterizer->sf);
600 } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
601 rasterizer_init_wm_gen7(dev, state, &rasterizer->wm);
602 rasterizer_init_sf_gen6(dev, state, &rasterizer->sf);
603 } else {
604 rasterizer_init_wm_gen6(dev, state, &rasterizer->wm);
605 rasterizer_init_sf_gen6(dev, state, &rasterizer->sf);
606 }
607 }
608
609 static void
610 fs_init_cso_gen6(const struct ilo_dev_info *dev,
611 const struct ilo_shader_state *fs,
612 struct ilo_shader_cso *cso)
613 {
614 int start_grf, input_count, sampler_count, interps, max_threads;
615 uint32_t dw2, dw4, dw5, dw6;
616
617 ILO_DEV_ASSERT(dev, 6, 6);
618
619 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
620 input_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT);
621 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
622 interps = ilo_shader_get_kernel_param(fs,
623 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS);
624
625 /* see brwCreateContext() */
626 max_threads = (dev->gt == 2) ? 80 : 40;
627
628 dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
629 dw2 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
630
631 dw4 = start_grf << GEN6_WM_DW4_URB_GRF_START0__SHIFT |
632 0 << GEN6_WM_DW4_URB_GRF_START1__SHIFT |
633 0 << GEN6_WM_DW4_URB_GRF_START2__SHIFT;
634
635 dw5 = (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT;
636
637 /*
638 * From the Sandy Bridge PRM, volume 2 part 1, page 275:
639 *
640 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that the
641 * PS kernel or color calculator has the ability to kill (discard)
642 * pixels or samples, other than due to depth or stencil testing.
643 * This bit is required to be ENABLED in the following situations:
644 *
645 * The API pixel shader program contains "killpix" or "discard"
646 * instructions, or other code in the pixel shader kernel that can
647 * cause the final pixel mask to differ from the pixel mask received
648 * on dispatch.
649 *
650 * A sampler with chroma key enabled with kill pixel mode is used by
651 * the pixel shader.
652 *
653 * Any render target has Alpha Test Enable or AlphaToCoverage Enable
654 * enabled.
655 *
656 * The pixel shader kernel generates and outputs oMask.
657 *
658 * Note: As ClipDistance clipping is fully supported in hardware and
659 * therefore not via PS instructions, there should be no need to
660 * ENABLE this bit due to ClipDistance clipping."
661 */
662 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
663 dw5 |= GEN6_WM_DW5_PS_KILL_PIXEL;
664
665 /*
666 * From the Sandy Bridge PRM, volume 2 part 1, page 275:
667 *
668 * "If a NULL Depth Buffer is selected, the Pixel Shader Computed Depth
669 * field must be set to disabled."
670 *
671 * TODO This is not checked yet.
672 */
673 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
674 dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH;
675
676 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
677 dw5 |= GEN6_WM_DW5_PS_USE_DEPTH;
678
679 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
680 dw5 |= GEN6_WM_DW5_PS_USE_W;
681
682 /*
683 * TODO set this bit only when
684 *
685 * a) fs writes colors and color is not masked, or
686 * b) fs writes depth, or
687 * c) fs or cc kills
688 */
689 if (true)
690 dw5 |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
691
692 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
693 dw5 |= GEN6_PS_DISPATCH_8 << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
694
695 dw6 = input_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
696 GEN6_WM_DW6_PS_POSOFFSET_NONE |
697 interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT;
698
699 STATIC_ASSERT(Elements(cso->payload) >= 4);
700 cso->payload[0] = dw2;
701 cso->payload[1] = dw4;
702 cso->payload[2] = dw5;
703 cso->payload[3] = dw6;
704 }
705
706 static uint32_t
707 fs_get_wm_gen7(const struct ilo_dev_info *dev,
708 const struct ilo_shader_state *fs)
709 {
710 uint32_t dw;
711
712 ILO_DEV_ASSERT(dev, 7, 7.5);
713
714 dw = ilo_shader_get_kernel_param(fs,
715 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) <<
716 GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT;
717
718 /*
719 * TODO set this bit only when
720 *
721 * a) fs writes colors and color is not masked, or
722 * b) fs writes depth, or
723 * c) fs or cc kills
724 */
725 dw |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
726
727 /*
728 * From the Ivy Bridge PRM, volume 2 part 1, page 278:
729 *
730 * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that
731 * the PS kernel or color calculator has the ability to kill
732 * (discard) pixels or samples, other than due to depth or stencil
733 * testing. This bit is required to be ENABLED in the following
734 * situations:
735 *
736 * - The API pixel shader program contains "killpix" or "discard"
737 * instructions, or other code in the pixel shader kernel that
738 * can cause the final pixel mask to differ from the pixel mask
739 * received on dispatch.
740 *
741 * - A sampler with chroma key enabled with kill pixel mode is used
742 * by the pixel shader.
743 *
744 * - Any render target has Alpha Test Enable or AlphaToCoverage
745 * Enable enabled.
746 *
747 * - The pixel shader kernel generates and outputs oMask.
748 *
749 * Note: As ClipDistance clipping is fully supported in hardware
750 * and therefore not via PS instructions, there should be no need
751 * to ENABLE this bit due to ClipDistance clipping."
752 */
753 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
754 dw |= GEN7_WM_DW1_PS_KILL_PIXEL;
755
756 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
757 dw |= GEN7_WM_DW1_PSCDEPTH_ON;
758
759 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
760 dw |= GEN7_WM_DW1_PS_USE_DEPTH;
761
762 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
763 dw |= GEN7_WM_DW1_PS_USE_W;
764
765 return dw;
766 }
767
768 static void
769 fs_init_cso_gen7(const struct ilo_dev_info *dev,
770 const struct ilo_shader_state *fs,
771 struct ilo_shader_cso *cso)
772 {
773 int start_grf, sampler_count, max_threads;
774 uint32_t dw2, dw4, dw5;
775
776 ILO_DEV_ASSERT(dev, 7, 7.5);
777
778 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
779 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
780
781 dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
782 dw2 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
783
784 dw4 = GEN7_PS_DW4_POSOFFSET_NONE;
785
786 /* see brwCreateContext() */
787 switch (ilo_dev_gen(dev)) {
788 case ILO_GEN(7.5):
789 max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
790 dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
791 dw4 |= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
792 break;
793 case ILO_GEN(7):
794 default:
795 max_threads = (dev->gt == 2) ? 172 : 48;
796 dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
797 break;
798 }
799
800 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
801 dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE;
802
803 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT))
804 dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
805
806 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
807 dw4 |= GEN6_PS_DISPATCH_8 << GEN7_PS_DW4_DISPATCH_MODE__SHIFT;
808
809 dw5 = start_grf << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
810 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
811 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
812
813 STATIC_ASSERT(Elements(cso->payload) >= 4);
814 cso->payload[0] = dw2;
815 cso->payload[1] = dw4;
816 cso->payload[2] = dw5;
817 cso->payload[3] = fs_get_wm_gen7(dev, fs);
818 }
819
820 static uint32_t
821 fs_get_psx_gen8(const struct ilo_dev_info *dev,
822 const struct ilo_shader_state *fs)
823 {
824 uint32_t dw;
825
826 ILO_DEV_ASSERT(dev, 8, 8);
827
828 dw = GEN8_PSX_DW1_DISPATCH_ENABLE;
829
830 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
831 dw |= GEN8_PSX_DW1_KILL_PIXEL;
832 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
833 dw |= GEN8_PSX_DW1_PSCDEPTH_ON;
834 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
835 dw |= GEN8_PSX_DW1_USE_DEPTH;
836 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
837 dw |= GEN8_PSX_DW1_USE_W;
838 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT))
839 dw |= GEN8_PSX_DW1_ATTR_ENABLE;
840
841 return dw;
842 }
843
844 static uint32_t
845 fs_get_wm_gen8(const struct ilo_dev_info *dev,
846 const struct ilo_shader_state *fs)
847 {
848 ILO_DEV_ASSERT(dev, 8, 8);
849
850 return ilo_shader_get_kernel_param(fs,
851 ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) <<
852 GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT;
853 }
854
855 static void
856 fs_init_cso_gen8(const struct ilo_dev_info *dev,
857 const struct ilo_shader_state *fs,
858 struct ilo_shader_cso *cso)
859 {
860 int start_grf, sampler_count;
861 uint32_t dw3, dw6, dw7;
862
863 ILO_DEV_ASSERT(dev, 8, 8);
864
865 start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG);
866 sampler_count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_SAMPLER_COUNT);
867
868 dw3 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
869 dw3 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
870
871 /* always 64? */
872 dw6 = (64 - 2) << GEN8_PS_DW6_MAX_THREADS__SHIFT |
873 GEN8_PS_DW6_POSOFFSET_NONE;
874 if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
875 dw6 |= GEN8_PS_DW6_PUSH_CONSTANT_ENABLE;
876
877 assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET));
878 dw6 |= GEN6_PS_DISPATCH_8 << GEN8_PS_DW6_DISPATCH_MODE__SHIFT;
879
880 dw7 = start_grf << GEN8_PS_DW7_URB_GRF_START0__SHIFT |
881 0 << GEN8_PS_DW7_URB_GRF_START1__SHIFT |
882 0 << GEN8_PS_DW7_URB_GRF_START2__SHIFT;
883
884 STATIC_ASSERT(Elements(cso->payload) >= 5);
885 cso->payload[0] = dw3;
886 cso->payload[1] = dw6;
887 cso->payload[2] = dw7;
888 cso->payload[3] = fs_get_psx_gen8(dev, fs);
889 cso->payload[4] = fs_get_wm_gen8(dev, fs);
890 }
891
892 void
893 ilo_gpe_init_fs_cso(const struct ilo_dev_info *dev,
894 const struct ilo_shader_state *fs,
895 struct ilo_shader_cso *cso)
896 {
897 if (ilo_dev_gen(dev) >= ILO_GEN(8))
898 fs_init_cso_gen8(dev, fs, cso);
899 else if (ilo_dev_gen(dev) >= ILO_GEN(7))
900 fs_init_cso_gen7(dev, fs, cso);
901 else
902 fs_init_cso_gen6(dev, fs, cso);
903 }
904
905 struct ilo_zs_surface_info {
906 int surface_type;
907 int format;
908
909 struct {
910 struct intel_bo *bo;
911 unsigned stride;
912 unsigned qpitch;
913 enum intel_tiling_mode tiling;
914 uint32_t offset;
915 } zs, stencil, hiz;
916
917 unsigned width, height, depth;
918 unsigned lod, first_layer, num_layers;
919 };
920
921 static void
922 zs_init_info_null(const struct ilo_dev_info *dev,
923 struct ilo_zs_surface_info *info)
924 {
925 ILO_DEV_ASSERT(dev, 6, 8);
926
927 memset(info, 0, sizeof(*info));
928
929 info->surface_type = GEN6_SURFTYPE_NULL;
930 info->format = GEN6_ZFORMAT_D32_FLOAT;
931 info->width = 1;
932 info->height = 1;
933 info->depth = 1;
934 info->num_layers = 1;
935 }
936
937 static void
938 zs_init_info(const struct ilo_dev_info *dev,
939 const struct ilo_texture *tex,
940 enum pipe_format format, unsigned level,
941 unsigned first_layer, unsigned num_layers,
942 struct ilo_zs_surface_info *info)
943 {
944 bool separate_stencil;
945
946 ILO_DEV_ASSERT(dev, 6, 8);
947
948 memset(info, 0, sizeof(*info));
949
950 info->surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
951
952 if (info->surface_type == GEN6_SURFTYPE_CUBE) {
953 /*
954 * From the Sandy Bridge PRM, volume 2 part 1, page 325-326:
955 *
956 * "For Other Surfaces (Cube Surfaces):
957 * This field (Minimum Array Element) is ignored."
958 *
959 * "For Other Surfaces (Cube Surfaces):
960 * This field (Render Target View Extent) is ignored."
961 *
962 * As such, we cannot set first_layer and num_layers on cube surfaces.
963 * To work around that, treat it as a 2D surface.
964 */
965 info->surface_type = GEN6_SURFTYPE_2D;
966 }
967
968 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
969 separate_stencil = true;
970 }
971 else {
972 /*
973 * From the Sandy Bridge PRM, volume 2 part 1, page 317:
974 *
975 * "This field (Separate Stencil Buffer Enable) must be set to the
976 * same value (enabled or disabled) as Hierarchical Depth Buffer
977 * Enable."
978 */
979 separate_stencil =
980 ilo_texture_can_enable_hiz(tex, level, first_layer, num_layers);
981 }
982
983 /*
984 * From the Sandy Bridge PRM, volume 2 part 1, page 317:
985 *
986 * "If this field (Hierarchical Depth Buffer Enable) is enabled, the
987 * Surface Format of the depth buffer cannot be
988 * D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. Use of stencil
989 * requires the separate stencil buffer."
990 *
991 * From the Ironlake PRM, volume 2 part 1, page 330:
992 *
993 * "If this field (Separate Stencil Buffer Enable) is disabled, the
994 * Surface Format of the depth buffer cannot be D24_UNORM_X8_UINT."
995 *
996 * There is no similar restriction for GEN6. But when D24_UNORM_X8_UINT
997 * is indeed used, the depth values output by the fragment shaders will
998 * be different when read back.
999 *
1000 * As for GEN7+, separate_stencil is always true.
1001 */
1002 switch (format) {
1003 case PIPE_FORMAT_Z16_UNORM:
1004 info->format = GEN6_ZFORMAT_D16_UNORM;
1005 break;
1006 case PIPE_FORMAT_Z32_FLOAT:
1007 info->format = GEN6_ZFORMAT_D32_FLOAT;
1008 break;
1009 case PIPE_FORMAT_Z24X8_UNORM:
1010 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1011 info->format = (separate_stencil) ?
1012 GEN6_ZFORMAT_D24_UNORM_X8_UINT :
1013 GEN6_ZFORMAT_D24_UNORM_S8_UINT;
1014 break;
1015 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1016 info->format = (separate_stencil) ?
1017 GEN6_ZFORMAT_D32_FLOAT :
1018 GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT;
1019 break;
1020 case PIPE_FORMAT_S8_UINT:
1021 if (separate_stencil) {
1022 info->format = GEN6_ZFORMAT_D32_FLOAT;
1023 break;
1024 }
1025 /* fall through */
1026 default:
1027 assert(!"unsupported depth/stencil format");
1028 zs_init_info_null(dev, info);
1029 return;
1030 break;
1031 }
1032
1033 if (format != PIPE_FORMAT_S8_UINT) {
1034 info->zs.bo = tex->bo;
1035 info->zs.stride = tex->layout.bo_stride;
1036
1037 assert(tex->layout.layer_height % 4 == 0);
1038 info->zs.qpitch = tex->layout.layer_height / 4;
1039
1040 info->zs.tiling = tex->layout.tiling;
1041 info->zs.offset = 0;
1042 }
1043
1044 if (tex->separate_s8 || format == PIPE_FORMAT_S8_UINT) {
1045 const struct ilo_texture *s8_tex =
1046 (tex->separate_s8) ? tex->separate_s8 : tex;
1047
1048 info->stencil.bo = s8_tex->bo;
1049
1050 /*
1051 * From the Sandy Bridge PRM, volume 2 part 1, page 329:
1052 *
1053 * "The pitch must be set to 2x the value computed based on width,
1054 * as the stencil buffer is stored with two rows interleaved."
1055 *
1056 * For GEN7, we still dobule the stride because we did not double the
1057 * slice widths when initializing the layout.
1058 */
1059 info->stencil.stride = s8_tex->layout.bo_stride * 2;
1060
1061 assert(s8_tex->layout.layer_height % 4 == 0);
1062 info->stencil.qpitch = s8_tex->layout.layer_height / 4;
1063
1064 info->stencil.tiling = s8_tex->layout.tiling;
1065
1066 if (ilo_dev_gen(dev) == ILO_GEN(6)) {
1067 unsigned x, y;
1068
1069 assert(s8_tex->layout.walk == ILO_LAYOUT_WALK_LOD);
1070
1071 /* offset to the level */
1072 ilo_layout_get_slice_pos(&s8_tex->layout, level, 0, &x, &y);
1073 ilo_layout_pos_to_mem(&s8_tex->layout, x, y, &x, &y);
1074 info->stencil.offset = ilo_layout_mem_to_raw(&s8_tex->layout, x, y);
1075 }
1076 }
1077
1078 if (ilo_texture_can_enable_hiz(tex, level, first_layer, num_layers)) {
1079 info->hiz.bo = tex->aux_bo;
1080 info->hiz.stride = tex->layout.aux_stride;
1081
1082 assert(tex->layout.aux_layer_height % 4 == 0);
1083 info->hiz.qpitch = tex->layout.aux_layer_height / 4;
1084
1085 info->hiz.tiling = INTEL_TILING_Y;
1086
1087 /* offset to the level */
1088 if (ilo_dev_gen(dev) == ILO_GEN(6))
1089 info->hiz.offset = tex->layout.aux_offsets[level];
1090 }
1091
1092 info->width = tex->layout.width0;
1093 info->height = tex->layout.height0;
1094 info->depth = (tex->base.target == PIPE_TEXTURE_3D) ?
1095 tex->base.depth0 : num_layers;
1096
1097 info->lod = level;
1098 info->first_layer = first_layer;
1099 info->num_layers = num_layers;
1100 }
1101
1102 void
1103 ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev,
1104 const struct ilo_texture *tex,
1105 enum pipe_format format, unsigned level,
1106 unsigned first_layer, unsigned num_layers,
1107 struct ilo_zs_surface *zs)
1108 {
1109 const int max_2d_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
1110 const int max_array_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 2048 : 512;
1111 struct ilo_zs_surface_info info;
1112 uint32_t dw1, dw2, dw3, dw4, dw5, dw6;
1113 int align_w = 8, align_h = 4;
1114
1115 ILO_DEV_ASSERT(dev, 6, 8);
1116
1117 if (tex) {
1118 zs_init_info(dev, tex, format, level, first_layer, num_layers, &info);
1119
1120 switch (tex->base.nr_samples) {
1121 case 2:
1122 align_w /= 2;
1123 break;
1124 case 4:
1125 align_w /= 2;
1126 align_h /= 2;
1127 break;
1128 case 8:
1129 align_w /= 4;
1130 align_h /= 2;
1131 break;
1132 case 16:
1133 align_w /= 4;
1134 align_h /= 4;
1135 break;
1136 default:
1137 break;
1138 }
1139 } else {
1140 zs_init_info_null(dev, &info);
1141 }
1142
1143 switch (info.surface_type) {
1144 case GEN6_SURFTYPE_NULL:
1145 break;
1146 case GEN6_SURFTYPE_1D:
1147 assert(info.width <= max_2d_size && info.height == 1 &&
1148 info.depth <= max_array_size);
1149 assert(info.first_layer < max_array_size - 1 &&
1150 info.num_layers <= max_array_size);
1151 break;
1152 case GEN6_SURFTYPE_2D:
1153 assert(info.width <= max_2d_size && info.height <= max_2d_size &&
1154 info.depth <= max_array_size);
1155 assert(info.first_layer < max_array_size - 1 &&
1156 info.num_layers <= max_array_size);
1157 break;
1158 case GEN6_SURFTYPE_3D:
1159 assert(info.width <= 2048 && info.height <= 2048 && info.depth <= 2048);
1160 assert(info.first_layer < 2048 && info.num_layers <= max_array_size);
1161 break;
1162 case GEN6_SURFTYPE_CUBE:
1163 assert(info.width <= max_2d_size && info.height <= max_2d_size &&
1164 info.depth == 1);
1165 assert(info.first_layer == 0 && info.num_layers == 1);
1166 assert(info.width == info.height);
1167 break;
1168 default:
1169 assert(!"unexpected depth surface type");
1170 break;
1171 }
1172
1173 dw1 = info.surface_type << GEN6_DEPTH_DW1_TYPE__SHIFT |
1174 info.format << GEN6_DEPTH_DW1_FORMAT__SHIFT;
1175
1176 if (info.zs.bo) {
1177 /* required for GEN6+ */
1178 assert(info.zs.tiling == INTEL_TILING_Y);
1179 assert(info.zs.stride > 0 && info.zs.stride < 128 * 1024 &&
1180 info.zs.stride % 128 == 0);
1181 assert(info.width <= info.zs.stride);
1182
1183 dw1 |= (info.zs.stride - 1);
1184 dw2 = info.zs.offset;
1185 } else {
1186 dw2 = 0;
1187 }
1188
1189 if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
1190 if (info.zs.bo)
1191 dw1 |= GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE;
1192
1193 if (info.stencil.bo)
1194 dw1 |= GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE;
1195
1196 if (info.hiz.bo)
1197 dw1 |= GEN7_DEPTH_DW1_HIZ_ENABLE;
1198
1199 dw3 = (info.height - 1) << GEN7_DEPTH_DW3_HEIGHT__SHIFT |
1200 (info.width - 1) << GEN7_DEPTH_DW3_WIDTH__SHIFT |
1201 info.lod << GEN7_DEPTH_DW3_LOD__SHIFT;
1202
1203 zs->dw_aligned_8x4 =
1204 (align(info.height, align_h) - 1) << GEN7_DEPTH_DW3_HEIGHT__SHIFT |
1205 (align(info.width, align_w) - 1) << GEN7_DEPTH_DW3_WIDTH__SHIFT |
1206 info.lod << GEN7_DEPTH_DW3_LOD__SHIFT;
1207
1208 dw4 = (info.depth - 1) << GEN7_DEPTH_DW4_DEPTH__SHIFT |
1209 info.first_layer << GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT;
1210
1211 dw5 = 0;
1212
1213 dw6 = (info.num_layers - 1) << GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT;
1214
1215 if (ilo_dev_gen(dev) >= ILO_GEN(8))
1216 dw6 |= info.zs.qpitch;
1217 } else {
1218 /* always Y-tiled */
1219 dw1 |= GEN6_TILING_Y << GEN6_DEPTH_DW1_TILING__SHIFT;
1220
1221 if (info.hiz.bo) {
1222 dw1 |= GEN6_DEPTH_DW1_HIZ_ENABLE |
1223 GEN6_DEPTH_DW1_SEPARATE_STENCIL;
1224 }
1225
1226 dw3 = (info.height - 1) << GEN6_DEPTH_DW3_HEIGHT__SHIFT |
1227 (info.width - 1) << GEN6_DEPTH_DW3_WIDTH__SHIFT |
1228 info.lod << GEN6_DEPTH_DW3_LOD__SHIFT |
1229 GEN6_DEPTH_DW3_MIPLAYOUT_BELOW;
1230
1231 zs->dw_aligned_8x4 =
1232 (align(info.height, align_h) - 1) << GEN6_DEPTH_DW3_HEIGHT__SHIFT |
1233 (align(info.width, align_w) - 1) << GEN6_DEPTH_DW3_WIDTH__SHIFT |
1234 info.lod << GEN6_DEPTH_DW3_LOD__SHIFT |
1235 GEN6_DEPTH_DW3_MIPLAYOUT_BELOW;
1236
1237 dw4 = (info.depth - 1) << GEN6_DEPTH_DW4_DEPTH__SHIFT |
1238 info.first_layer << GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT |
1239 (info.num_layers - 1) << GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT;
1240
1241 dw5 = 0;
1242
1243 dw6 = 0;
1244 }
1245
1246 STATIC_ASSERT(Elements(zs->payload) >= 12);
1247
1248 zs->payload[0] = dw1;
1249 zs->payload[1] = dw2;
1250 zs->payload[2] = dw3;
1251 zs->payload[3] = dw4;
1252 zs->payload[4] = dw5;
1253 zs->payload[5] = dw6;
1254
1255 /* do not increment reference count */
1256 zs->bo = info.zs.bo;
1257
1258 /* separate stencil */
1259 if (info.stencil.bo) {
1260 assert(info.stencil.stride > 0 && info.stencil.stride < 128 * 1024 &&
1261 info.stencil.stride % 128 == 0);
1262
1263 dw1 = (info.stencil.stride - 1) << GEN6_STENCIL_DW1_PITCH__SHIFT;
1264 if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
1265 dw1 |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
1266
1267 dw2 = info.stencil.offset;
1268 dw4 = info.stencil.qpitch;
1269 } else {
1270 dw1 = 0;
1271 dw2 = 0;
1272 dw4 = 0;
1273 }
1274
1275 zs->payload[6] = dw1;
1276 zs->payload[7] = dw2;
1277 zs->payload[8] = dw4;
1278 /* do not increment reference count */
1279 zs->separate_s8_bo = info.stencil.bo;
1280
1281 /* hiz */
1282 if (info.hiz.bo) {
1283 dw1 = (info.hiz.stride - 1) << GEN6_HIZ_DW1_PITCH__SHIFT;
1284 dw2 = info.hiz.offset;
1285 dw4 = info.hiz.qpitch;
1286 } else {
1287 dw1 = 0;
1288 dw2 = 0;
1289 dw4 = 0;
1290 }
1291
1292 zs->payload[9] = dw1;
1293 zs->payload[10] = dw2;
1294 zs->payload[11] = dw4;
1295 /* do not increment reference count */
1296 zs->hiz_bo = info.hiz.bo;
1297 }
1298
1299 static void
1300 viewport_get_guardband(const struct ilo_dev_info *dev,
1301 int center_x, int center_y,
1302 int *min_gbx, int *max_gbx,
1303 int *min_gby, int *max_gby)
1304 {
1305 /*
1306 * From the Sandy Bridge PRM, volume 2 part 1, page 234:
1307 *
1308 * "Per-Device Guardband Extents
1309 *
1310 * - Supported X,Y ScreenSpace "Guardband" Extent: [-16K,16K-1]
1311 * - Maximum Post-Clamp Delta (X or Y): 16K"
1312 *
1313 * "In addition, in order to be correctly rendered, objects must have a
1314 * screenspace bounding box not exceeding 8K in the X or Y direction.
1315 * This additional restriction must also be comprehended by software,
1316 * i.e., enforced by use of clipping."
1317 *
1318 * From the Ivy Bridge PRM, volume 2 part 1, page 248:
1319 *
1320 * "Per-Device Guardband Extents
1321 *
1322 * - Supported X,Y ScreenSpace "Guardband" Extent: [-32K,32K-1]
1323 * - Maximum Post-Clamp Delta (X or Y): N/A"
1324 *
1325 * "In addition, in order to be correctly rendered, objects must have a
1326 * screenspace bounding box not exceeding 8K in the X or Y direction.
1327 * This additional restriction must also be comprehended by software,
1328 * i.e., enforced by use of clipping."
1329 *
1330 * Combined, the bounding box of any object can not exceed 8K in both
1331 * width and height.
1332 *
1333 * Below we set the guardband as a squre of length 8K, centered at where
1334 * the viewport is. This makes sure all objects passing the GB test are
1335 * valid to the renderer, and those failing the XY clipping have a
1336 * better chance of passing the GB test.
1337 */
1338 const int max_extent = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 32768 : 16384;
1339 const int half_len = 8192 / 2;
1340
1341 /* make sure the guardband is within the valid range */
1342 if (center_x - half_len < -max_extent)
1343 center_x = -max_extent + half_len;
1344 else if (center_x + half_len > max_extent - 1)
1345 center_x = max_extent - half_len;
1346
1347 if (center_y - half_len < -max_extent)
1348 center_y = -max_extent + half_len;
1349 else if (center_y + half_len > max_extent - 1)
1350 center_y = max_extent - half_len;
1351
1352 *min_gbx = (float) (center_x - half_len);
1353 *max_gbx = (float) (center_x + half_len);
1354 *min_gby = (float) (center_y - half_len);
1355 *max_gby = (float) (center_y + half_len);
1356 }
1357
1358 void
1359 ilo_gpe_set_viewport_cso(const struct ilo_dev_info *dev,
1360 const struct pipe_viewport_state *state,
1361 struct ilo_viewport_cso *vp)
1362 {
1363 const float scale_x = fabs(state->scale[0]);
1364 const float scale_y = fabs(state->scale[1]);
1365 const float scale_z = fabs(state->scale[2]);
1366 int min_gbx, max_gbx, min_gby, max_gby;
1367
1368 ILO_DEV_ASSERT(dev, 6, 8);
1369
1370 viewport_get_guardband(dev,
1371 (int) state->translate[0],
1372 (int) state->translate[1],
1373 &min_gbx, &max_gbx, &min_gby, &max_gby);
1374
1375 /* matrix form */
1376 vp->m00 = state->scale[0];
1377 vp->m11 = state->scale[1];
1378 vp->m22 = state->scale[2];
1379 vp->m30 = state->translate[0];
1380 vp->m31 = state->translate[1];
1381 vp->m32 = state->translate[2];
1382
1383 /* guardband in NDC space */
1384 vp->min_gbx = ((float) min_gbx - state->translate[0]) / scale_x;
1385 vp->max_gbx = ((float) max_gbx - state->translate[0]) / scale_x;
1386 vp->min_gby = ((float) min_gby - state->translate[1]) / scale_y;
1387 vp->max_gby = ((float) max_gby - state->translate[1]) / scale_y;
1388
1389 /* viewport in screen space */
1390 vp->min_x = scale_x * -1.0f + state->translate[0];
1391 vp->max_x = scale_x * 1.0f + state->translate[0];
1392 vp->min_y = scale_y * -1.0f + state->translate[1];
1393 vp->max_y = scale_y * 1.0f + state->translate[1];
1394 vp->min_z = scale_z * -1.0f + state->translate[2];
1395 vp->max_z = scale_z * 1.0f + state->translate[2];
1396 }
1397
1398 /**
1399 * Translate a pipe logicop to the matching hardware logicop.
1400 */
1401 static int
1402 gen6_translate_pipe_logicop(unsigned logicop)
1403 {
1404 switch (logicop) {
1405 case PIPE_LOGICOP_CLEAR: return GEN6_LOGICOP_CLEAR;
1406 case PIPE_LOGICOP_NOR: return GEN6_LOGICOP_NOR;
1407 case PIPE_LOGICOP_AND_INVERTED: return GEN6_LOGICOP_AND_INVERTED;
1408 case PIPE_LOGICOP_COPY_INVERTED: return GEN6_LOGICOP_COPY_INVERTED;
1409 case PIPE_LOGICOP_AND_REVERSE: return GEN6_LOGICOP_AND_REVERSE;
1410 case PIPE_LOGICOP_INVERT: return GEN6_LOGICOP_INVERT;
1411 case PIPE_LOGICOP_XOR: return GEN6_LOGICOP_XOR;
1412 case PIPE_LOGICOP_NAND: return GEN6_LOGICOP_NAND;
1413 case PIPE_LOGICOP_AND: return GEN6_LOGICOP_AND;
1414 case PIPE_LOGICOP_EQUIV: return GEN6_LOGICOP_EQUIV;
1415 case PIPE_LOGICOP_NOOP: return GEN6_LOGICOP_NOOP;
1416 case PIPE_LOGICOP_OR_INVERTED: return GEN6_LOGICOP_OR_INVERTED;
1417 case PIPE_LOGICOP_COPY: return GEN6_LOGICOP_COPY;
1418 case PIPE_LOGICOP_OR_REVERSE: return GEN6_LOGICOP_OR_REVERSE;
1419 case PIPE_LOGICOP_OR: return GEN6_LOGICOP_OR;
1420 case PIPE_LOGICOP_SET: return GEN6_LOGICOP_SET;
1421 default:
1422 assert(!"unknown logicop function");
1423 return GEN6_LOGICOP_CLEAR;
1424 }
1425 }
1426
1427 /**
1428 * Translate a pipe blend function to the matching hardware blend function.
1429 */
1430 static int
1431 gen6_translate_pipe_blend(unsigned blend)
1432 {
1433 switch (blend) {
1434 case PIPE_BLEND_ADD: return GEN6_BLENDFUNCTION_ADD;
1435 case PIPE_BLEND_SUBTRACT: return GEN6_BLENDFUNCTION_SUBTRACT;
1436 case PIPE_BLEND_REVERSE_SUBTRACT: return GEN6_BLENDFUNCTION_REVERSE_SUBTRACT;
1437 case PIPE_BLEND_MIN: return GEN6_BLENDFUNCTION_MIN;
1438 case PIPE_BLEND_MAX: return GEN6_BLENDFUNCTION_MAX;
1439 default:
1440 assert(!"unknown blend function");
1441 return GEN6_BLENDFUNCTION_ADD;
1442 };
1443 }
1444
1445 /**
1446 * Translate a pipe blend factor to the matching hardware blend factor.
1447 */
1448 static int
1449 gen6_translate_pipe_blendfactor(unsigned blendfactor)
1450 {
1451 switch (blendfactor) {
1452 case PIPE_BLENDFACTOR_ONE: return GEN6_BLENDFACTOR_ONE;
1453 case PIPE_BLENDFACTOR_SRC_COLOR: return GEN6_BLENDFACTOR_SRC_COLOR;
1454 case PIPE_BLENDFACTOR_SRC_ALPHA: return GEN6_BLENDFACTOR_SRC_ALPHA;
1455 case PIPE_BLENDFACTOR_DST_ALPHA: return GEN6_BLENDFACTOR_DST_ALPHA;
1456 case PIPE_BLENDFACTOR_DST_COLOR: return GEN6_BLENDFACTOR_DST_COLOR;
1457 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE;
1458 case PIPE_BLENDFACTOR_CONST_COLOR: return GEN6_BLENDFACTOR_CONST_COLOR;
1459 case PIPE_BLENDFACTOR_CONST_ALPHA: return GEN6_BLENDFACTOR_CONST_ALPHA;
1460 case PIPE_BLENDFACTOR_SRC1_COLOR: return GEN6_BLENDFACTOR_SRC1_COLOR;
1461 case PIPE_BLENDFACTOR_SRC1_ALPHA: return GEN6_BLENDFACTOR_SRC1_ALPHA;
1462 case PIPE_BLENDFACTOR_ZERO: return GEN6_BLENDFACTOR_ZERO;
1463 case PIPE_BLENDFACTOR_INV_SRC_COLOR: return GEN6_BLENDFACTOR_INV_SRC_COLOR;
1464 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return GEN6_BLENDFACTOR_INV_SRC_ALPHA;
1465 case PIPE_BLENDFACTOR_INV_DST_ALPHA: return GEN6_BLENDFACTOR_INV_DST_ALPHA;
1466 case PIPE_BLENDFACTOR_INV_DST_COLOR: return GEN6_BLENDFACTOR_INV_DST_COLOR;
1467 case PIPE_BLENDFACTOR_INV_CONST_COLOR: return GEN6_BLENDFACTOR_INV_CONST_COLOR;
1468 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return GEN6_BLENDFACTOR_INV_CONST_ALPHA;
1469 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: return GEN6_BLENDFACTOR_INV_SRC1_COLOR;
1470 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return GEN6_BLENDFACTOR_INV_SRC1_ALPHA;
1471 default:
1472 assert(!"unknown blend factor");
1473 return GEN6_BLENDFACTOR_ONE;
1474 };
1475 }
1476
1477 /**
1478 * Translate a pipe stencil op to the matching hardware stencil op.
1479 */
1480 static int
1481 gen6_translate_pipe_stencil_op(unsigned stencil_op)
1482 {
1483 switch (stencil_op) {
1484 case PIPE_STENCIL_OP_KEEP: return GEN6_STENCILOP_KEEP;
1485 case PIPE_STENCIL_OP_ZERO: return GEN6_STENCILOP_ZERO;
1486 case PIPE_STENCIL_OP_REPLACE: return GEN6_STENCILOP_REPLACE;
1487 case PIPE_STENCIL_OP_INCR: return GEN6_STENCILOP_INCRSAT;
1488 case PIPE_STENCIL_OP_DECR: return GEN6_STENCILOP_DECRSAT;
1489 case PIPE_STENCIL_OP_INCR_WRAP: return GEN6_STENCILOP_INCR;
1490 case PIPE_STENCIL_OP_DECR_WRAP: return GEN6_STENCILOP_DECR;
1491 case PIPE_STENCIL_OP_INVERT: return GEN6_STENCILOP_INVERT;
1492 default:
1493 assert(!"unknown stencil op");
1494 return GEN6_STENCILOP_KEEP;
1495 }
1496 }
1497
1498 static int
1499 gen6_blend_factor_dst_alpha_forced_one(int factor)
1500 {
1501 switch (factor) {
1502 case GEN6_BLENDFACTOR_DST_ALPHA:
1503 return GEN6_BLENDFACTOR_ONE;
1504 case GEN6_BLENDFACTOR_INV_DST_ALPHA:
1505 case GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE:
1506 return GEN6_BLENDFACTOR_ZERO;
1507 default:
1508 return factor;
1509 }
1510 }
1511
1512 static uint32_t
1513 blend_get_rt_blend_enable_gen6(const struct ilo_dev_info *dev,
1514 const struct pipe_rt_blend_state *rt,
1515 bool dst_alpha_forced_one)
1516 {
1517 int rgb_src, rgb_dst, a_src, a_dst;
1518 uint32_t dw;
1519
1520 ILO_DEV_ASSERT(dev, 6, 7.5);
1521
1522 if (!rt->blend_enable)
1523 return 0;
1524
1525 rgb_src = gen6_translate_pipe_blendfactor(rt->rgb_src_factor);
1526 rgb_dst = gen6_translate_pipe_blendfactor(rt->rgb_dst_factor);
1527 a_src = gen6_translate_pipe_blendfactor(rt->alpha_src_factor);
1528 a_dst = gen6_translate_pipe_blendfactor(rt->alpha_dst_factor);
1529
1530 if (dst_alpha_forced_one) {
1531 rgb_src = gen6_blend_factor_dst_alpha_forced_one(rgb_src);
1532 rgb_dst = gen6_blend_factor_dst_alpha_forced_one(rgb_dst);
1533 a_src = gen6_blend_factor_dst_alpha_forced_one(a_src);
1534 a_dst = gen6_blend_factor_dst_alpha_forced_one(a_dst);
1535 }
1536
1537 dw = GEN6_RT_DW0_BLEND_ENABLE |
1538 gen6_translate_pipe_blend(rt->alpha_func) << 26 |
1539 a_src << 20 |
1540 a_dst << 15 |
1541 gen6_translate_pipe_blend(rt->rgb_func) << 11 |
1542 rgb_src << 5 |
1543 rgb_dst;
1544
1545 if (rt->rgb_func != rt->alpha_func ||
1546 rgb_src != a_src || rgb_dst != a_dst)
1547 dw |= GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE;
1548
1549 return dw;
1550 }
1551
1552 static uint32_t
1553 blend_get_rt_blend_enable_gen8(const struct ilo_dev_info *dev,
1554 const struct pipe_rt_blend_state *rt,
1555 bool dst_alpha_forced_one,
1556 bool *independent_alpha)
1557 {
1558 int rgb_src, rgb_dst, a_src, a_dst;
1559 uint32_t dw;
1560
1561 ILO_DEV_ASSERT(dev, 8, 8);
1562
1563 if (!rt->blend_enable) {
1564 *independent_alpha = false;
1565 return 0;
1566 }
1567
1568 rgb_src = gen6_translate_pipe_blendfactor(rt->rgb_src_factor);
1569 rgb_dst = gen6_translate_pipe_blendfactor(rt->rgb_dst_factor);
1570 a_src = gen6_translate_pipe_blendfactor(rt->alpha_src_factor);
1571 a_dst = gen6_translate_pipe_blendfactor(rt->alpha_dst_factor);
1572
1573 if (dst_alpha_forced_one) {
1574 rgb_src = gen6_blend_factor_dst_alpha_forced_one(rgb_src);
1575 rgb_dst = gen6_blend_factor_dst_alpha_forced_one(rgb_dst);
1576 a_src = gen6_blend_factor_dst_alpha_forced_one(a_src);
1577 a_dst = gen6_blend_factor_dst_alpha_forced_one(a_dst);
1578 }
1579
1580 dw = GEN8_RT_DW0_BLEND_ENABLE |
1581 rgb_src << 26 |
1582 rgb_dst << 21 |
1583 gen6_translate_pipe_blend(rt->rgb_func) << 18 |
1584 a_src << 13 |
1585 a_dst << 8 |
1586 gen6_translate_pipe_blend(rt->alpha_func) << 5;
1587
1588 *independent_alpha = (rt->rgb_func != rt->alpha_func ||
1589 rgb_src != a_src ||
1590 rgb_dst != a_dst);
1591
1592 return dw;
1593 }
1594
1595 static void
1596 blend_init_cso_gen6(const struct ilo_dev_info *dev,
1597 const struct pipe_blend_state *state,
1598 struct ilo_blend_state *blend,
1599 unsigned index)
1600 {
1601 const struct pipe_rt_blend_state *rt = &state->rt[index];
1602 struct ilo_blend_cso *cso = &blend->cso[index];
1603
1604 ILO_DEV_ASSERT(dev, 6, 7.5);
1605
1606 cso->payload[0] = 0;
1607 cso->payload[1] = GEN6_RT_DW1_COLORCLAMP_RTFORMAT |
1608 GEN6_RT_DW1_PRE_BLEND_CLAMP |
1609 GEN6_RT_DW1_POST_BLEND_CLAMP;
1610
1611 if (!(rt->colormask & PIPE_MASK_A))
1612 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_A;
1613 if (!(rt->colormask & PIPE_MASK_R))
1614 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_R;
1615 if (!(rt->colormask & PIPE_MASK_G))
1616 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_G;
1617 if (!(rt->colormask & PIPE_MASK_B))
1618 cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_B;
1619
1620 /*
1621 * From the Sandy Bridge PRM, volume 2 part 1, page 365:
1622 *
1623 * "Color Buffer Blending and Logic Ops must not be enabled
1624 * simultaneously, or behavior is UNDEFINED."
1625 *
1626 * Since state->logicop_enable takes precedence over rt->blend_enable,
1627 * no special care is needed.
1628 */
1629 if (state->logicop_enable) {
1630 cso->dw_blend = 0;
1631 cso->dw_blend_dst_alpha_forced_one = 0;
1632 } else {
1633 cso->dw_blend = blend_get_rt_blend_enable_gen6(dev, rt, false);
1634 cso->dw_blend_dst_alpha_forced_one =
1635 blend_get_rt_blend_enable_gen6(dev, rt, true);
1636 }
1637 }
1638
1639 static bool
1640 blend_init_cso_gen8(const struct ilo_dev_info *dev,
1641 const struct pipe_blend_state *state,
1642 struct ilo_blend_state *blend,
1643 unsigned index)
1644 {
1645 const struct pipe_rt_blend_state *rt = &state->rt[index];
1646 struct ilo_blend_cso *cso = &blend->cso[index];
1647 bool independent_alpha = false;
1648
1649 ILO_DEV_ASSERT(dev, 8, 8);
1650
1651 cso->payload[0] = 0;
1652 cso->payload[1] = GEN8_RT_DW1_COLORCLAMP_RTFORMAT |
1653 GEN8_RT_DW1_PRE_BLEND_CLAMP |
1654 GEN8_RT_DW1_POST_BLEND_CLAMP;
1655
1656 if (!(rt->colormask & PIPE_MASK_A))
1657 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_A;
1658 if (!(rt->colormask & PIPE_MASK_R))
1659 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_R;
1660 if (!(rt->colormask & PIPE_MASK_G))
1661 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_G;
1662 if (!(rt->colormask & PIPE_MASK_B))
1663 cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_B;
1664
1665 if (state->logicop_enable) {
1666 cso->dw_blend = 0;
1667 cso->dw_blend_dst_alpha_forced_one = 0;
1668 } else {
1669 bool tmp[2];
1670
1671 cso->dw_blend = blend_get_rt_blend_enable_gen8(dev, rt, false, &tmp[0]);
1672 cso->dw_blend_dst_alpha_forced_one =
1673 blend_get_rt_blend_enable_gen8(dev, rt, true, &tmp[1]);
1674
1675 if (tmp[0] || tmp[1])
1676 independent_alpha = true;
1677 }
1678
1679 return independent_alpha;
1680 }
1681
1682 static uint32_t
1683 blend_get_logicop_enable_gen6(const struct ilo_dev_info *dev,
1684 const struct pipe_blend_state *state)
1685 {
1686 ILO_DEV_ASSERT(dev, 6, 7.5);
1687
1688 if (!state->logicop_enable)
1689 return 0;
1690
1691 return GEN6_RT_DW1_LOGICOP_ENABLE |
1692 gen6_translate_pipe_logicop(state->logicop_func) << 18;
1693 }
1694
1695 static uint32_t
1696 blend_get_logicop_enable_gen8(const struct ilo_dev_info *dev,
1697 const struct pipe_blend_state *state)
1698 {
1699 ILO_DEV_ASSERT(dev, 8, 8);
1700
1701 if (!state->logicop_enable)
1702 return 0;
1703
1704 return GEN8_RT_DW1_LOGICOP_ENABLE |
1705 gen6_translate_pipe_logicop(state->logicop_func) << 27;
1706 }
1707
1708 static uint32_t
1709 blend_get_alpha_mod_gen6(const struct ilo_dev_info *dev,
1710 const struct pipe_blend_state *state,
1711 bool dual_blend)
1712 {
1713 uint32_t dw = 0;
1714
1715 ILO_DEV_ASSERT(dev, 6, 7.5);
1716
1717 if (state->alpha_to_coverage) {
1718 dw |= GEN6_RT_DW1_ALPHA_TO_COVERAGE;
1719 if (ilo_dev_gen(dev) >= ILO_GEN(7))
1720 dw |= GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER;
1721 }
1722 /*
1723 * From the Sandy Bridge PRM, volume 2 part 1, page 378:
1724 *
1725 * "If Dual Source Blending is enabled, this bit (AlphaToOne Enable)
1726 * must be disabled."
1727 */
1728 if (state->alpha_to_one && !dual_blend)
1729 dw |= GEN6_RT_DW1_ALPHA_TO_ONE;
1730
1731 return dw;
1732 }
1733
1734 static uint32_t
1735 blend_get_alpha_mod_gen8(const struct ilo_dev_info *dev,
1736 const struct pipe_blend_state *state,
1737 bool dual_blend)
1738 {
1739 uint32_t dw = 0;
1740
1741 ILO_DEV_ASSERT(dev, 8, 8);
1742
1743 if (state->alpha_to_coverage) {
1744 dw |= GEN8_BLEND_DW0_ALPHA_TO_COVERAGE |
1745 GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER;
1746 }
1747
1748 if (state->alpha_to_one && !dual_blend)
1749 dw |= GEN8_BLEND_DW0_ALPHA_TO_ONE;
1750
1751 return dw;
1752 }
1753
1754 static uint32_t
1755 blend_get_ps_blend_gen8(const struct ilo_dev_info *dev, uint32_t rt_dw0)
1756 {
1757 int rgb_src, rgb_dst, a_src, a_dst;
1758 uint32_t dw;
1759
1760 ILO_DEV_ASSERT(dev, 8, 8);
1761
1762 if (!(rt_dw0 & GEN8_RT_DW0_BLEND_ENABLE))
1763 return 0;
1764
1765 a_src = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_SRC_ALPHA_FACTOR);
1766 a_dst = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_DST_ALPHA_FACTOR);
1767 rgb_src = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_SRC_COLOR_FACTOR);
1768 rgb_dst = GEN_EXTRACT(rt_dw0, GEN8_RT_DW0_DST_COLOR_FACTOR);
1769
1770 dw = GEN8_PS_BLEND_DW1_BLEND_ENABLE;
1771 dw |= GEN_SHIFT32(a_src, GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR);
1772 dw |= GEN_SHIFT32(a_dst, GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR);
1773 dw |= GEN_SHIFT32(rgb_src, GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR);
1774 dw |= GEN_SHIFT32(rgb_dst, GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR);
1775
1776 if (a_src != rgb_src || a_dst != rgb_dst)
1777 dw |= GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE;
1778
1779 return dw;
1780 }
1781
1782 void
1783 ilo_gpe_init_blend(const struct ilo_dev_info *dev,
1784 const struct pipe_blend_state *state,
1785 struct ilo_blend_state *blend)
1786 {
1787 unsigned i;
1788
1789 ILO_DEV_ASSERT(dev, 6, 8);
1790
1791 blend->dual_blend = (util_blend_state_is_dual(state, 0) &&
1792 state->rt[0].blend_enable &&
1793 !state->logicop_enable);
1794 blend->alpha_to_coverage = state->alpha_to_coverage;
1795
1796 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
1797 bool independent_alpha;
1798
1799 blend->dw_alpha_mod =
1800 blend_get_alpha_mod_gen8(dev, state, blend->dual_blend);
1801 blend->dw_logicop = blend_get_logicop_enable_gen8(dev, state);
1802 blend->dw_shared = (state->dither) ? GEN8_BLEND_DW0_DITHER_ENABLE : 0;
1803
1804 independent_alpha = blend_init_cso_gen8(dev, state, blend, 0);
1805 if (independent_alpha)
1806 blend->dw_shared |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
1807
1808 blend->dw_ps_blend = blend_get_ps_blend_gen8(dev,
1809 blend->cso[0].dw_blend);
1810 blend->dw_ps_blend_dst_alpha_forced_one = blend_get_ps_blend_gen8(dev,
1811 blend->cso[0].dw_blend_dst_alpha_forced_one);
1812
1813 if (state->independent_blend_enable) {
1814 for (i = 1; i < Elements(blend->cso); i++) {
1815 independent_alpha = blend_init_cso_gen8(dev, state, blend, i);
1816 if (independent_alpha)
1817 blend->dw_shared |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
1818 }
1819 } else {
1820 for (i = 1; i < Elements(blend->cso); i++)
1821 blend->cso[i] = blend->cso[0];
1822 }
1823 } else {
1824 blend->dw_alpha_mod =
1825 blend_get_alpha_mod_gen6(dev, state, blend->dual_blend);
1826 blend->dw_logicop = blend_get_logicop_enable_gen6(dev, state);
1827 blend->dw_shared = (state->dither) ? GEN6_RT_DW1_DITHER_ENABLE : 0;
1828
1829 blend->dw_ps_blend = 0;
1830 blend->dw_ps_blend_dst_alpha_forced_one = 0;
1831
1832 blend_init_cso_gen6(dev, state, blend, 0);
1833 if (state->independent_blend_enable) {
1834 for (i = 1; i < Elements(blend->cso); i++)
1835 blend_init_cso_gen6(dev, state, blend, i);
1836 } else {
1837 for (i = 1; i < Elements(blend->cso); i++)
1838 blend->cso[i] = blend->cso[0];
1839 }
1840 }
1841 }
1842
1843 /**
1844 * Translate a pipe DSA test function to the matching hardware compare
1845 * function.
1846 */
1847 static int
1848 gen6_translate_dsa_func(unsigned func)
1849 {
1850 switch (func) {
1851 case PIPE_FUNC_NEVER: return GEN6_COMPAREFUNCTION_NEVER;
1852 case PIPE_FUNC_LESS: return GEN6_COMPAREFUNCTION_LESS;
1853 case PIPE_FUNC_EQUAL: return GEN6_COMPAREFUNCTION_EQUAL;
1854 case PIPE_FUNC_LEQUAL: return GEN6_COMPAREFUNCTION_LEQUAL;
1855 case PIPE_FUNC_GREATER: return GEN6_COMPAREFUNCTION_GREATER;
1856 case PIPE_FUNC_NOTEQUAL: return GEN6_COMPAREFUNCTION_NOTEQUAL;
1857 case PIPE_FUNC_GEQUAL: return GEN6_COMPAREFUNCTION_GEQUAL;
1858 case PIPE_FUNC_ALWAYS: return GEN6_COMPAREFUNCTION_ALWAYS;
1859 default:
1860 assert(!"unknown depth/stencil/alpha test function");
1861 return GEN6_COMPAREFUNCTION_NEVER;
1862 }
1863 }
1864
1865 static uint32_t
1866 dsa_get_stencil_enable_gen6(const struct ilo_dev_info *dev,
1867 const struct pipe_stencil_state *stencil0,
1868 const struct pipe_stencil_state *stencil1)
1869 {
1870 uint32_t dw;
1871
1872 ILO_DEV_ASSERT(dev, 6, 7.5);
1873
1874 if (!stencil0->enabled)
1875 return 0;
1876
1877 /*
1878 * From the Sandy Bridge PRM, volume 2 part 1, page 359:
1879 *
1880 * "If the Depth Buffer is either undefined or does not have a surface
1881 * format of D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT and separate
1882 * stencil buffer is disabled, Stencil Test Enable must be DISABLED"
1883 *
1884 * From the Sandy Bridge PRM, volume 2 part 1, page 370:
1885 *
1886 * "This field (Stencil Test Enable) cannot be enabled if
1887 * Surface Format in 3DSTATE_DEPTH_BUFFER is set to D16_UNORM."
1888 *
1889 * TODO We do not check these yet.
1890 */
1891 dw = GEN6_ZS_DW0_STENCIL_TEST_ENABLE |
1892 gen6_translate_dsa_func(stencil0->func) << 28 |
1893 gen6_translate_pipe_stencil_op(stencil0->fail_op) << 25 |
1894 gen6_translate_pipe_stencil_op(stencil0->zfail_op) << 22 |
1895 gen6_translate_pipe_stencil_op(stencil0->zpass_op) << 19;
1896 if (stencil0->writemask)
1897 dw |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
1898
1899 if (stencil1->enabled) {
1900 dw |= GEN6_ZS_DW0_STENCIL1_ENABLE |
1901 gen6_translate_dsa_func(stencil1->func) << 12 |
1902 gen6_translate_pipe_stencil_op(stencil1->fail_op) << 9 |
1903 gen6_translate_pipe_stencil_op(stencil1->zfail_op) << 6 |
1904 gen6_translate_pipe_stencil_op(stencil1->zpass_op) << 3;
1905 if (stencil1->writemask)
1906 dw |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
1907 }
1908
1909 return dw;
1910 }
1911
1912 static uint32_t
1913 dsa_get_stencil_enable_gen8(const struct ilo_dev_info *dev,
1914 const struct pipe_stencil_state *stencil0,
1915 const struct pipe_stencil_state *stencil1)
1916 {
1917 uint32_t dw;
1918
1919 ILO_DEV_ASSERT(dev, 8, 8);
1920
1921 if (!stencil0->enabled)
1922 return 0;
1923
1924 dw = gen6_translate_pipe_stencil_op(stencil0->fail_op) << 29 |
1925 gen6_translate_pipe_stencil_op(stencil0->zfail_op) << 26 |
1926 gen6_translate_pipe_stencil_op(stencil0->zpass_op) << 23 |
1927 gen6_translate_dsa_func(stencil0->func) << 8 |
1928 GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
1929 if (stencil0->writemask)
1930 dw |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
1931
1932 if (stencil1->enabled) {
1933 dw |= gen6_translate_dsa_func(stencil1->func) << 20 |
1934 gen6_translate_pipe_stencil_op(stencil1->fail_op) << 17 |
1935 gen6_translate_pipe_stencil_op(stencil1->zfail_op) << 14 |
1936 gen6_translate_pipe_stencil_op(stencil1->zpass_op) << 11 |
1937 GEN8_ZS_DW1_STENCIL1_ENABLE;
1938 if (stencil1->writemask)
1939 dw |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
1940 }
1941
1942 return dw;
1943 }
1944
1945 static uint32_t
1946 dsa_get_depth_enable_gen6(const struct ilo_dev_info *dev,
1947 const struct pipe_depth_state *state)
1948 {
1949 uint32_t dw;
1950
1951 ILO_DEV_ASSERT(dev, 6, 7.5);
1952
1953 /*
1954 * From the Sandy Bridge PRM, volume 2 part 1, page 360:
1955 *
1956 * "Enabling the Depth Test function without defining a Depth Buffer is
1957 * UNDEFINED."
1958 *
1959 * From the Sandy Bridge PRM, volume 2 part 1, page 375:
1960 *
1961 * "A Depth Buffer must be defined before enabling writes to it, or
1962 * operation is UNDEFINED."
1963 *
1964 * TODO We do not check these yet.
1965 */
1966 if (state->enabled) {
1967 dw = GEN6_ZS_DW2_DEPTH_TEST_ENABLE |
1968 gen6_translate_dsa_func(state->func) << 27;
1969 } else {
1970 dw = GEN6_COMPAREFUNCTION_ALWAYS << 27;
1971 }
1972
1973 if (state->writemask)
1974 dw |= GEN6_ZS_DW2_DEPTH_WRITE_ENABLE;
1975
1976 return dw;
1977 }
1978
1979 static uint32_t
1980 dsa_get_depth_enable_gen8(const struct ilo_dev_info *dev,
1981 const struct pipe_depth_state *state)
1982 {
1983 uint32_t dw;
1984
1985 ILO_DEV_ASSERT(dev, 8, 8);
1986
1987 if (state->enabled) {
1988 dw = GEN8_ZS_DW1_DEPTH_TEST_ENABLE |
1989 gen6_translate_dsa_func(state->func) << 5;
1990 } else {
1991 dw = GEN6_COMPAREFUNCTION_ALWAYS << 5;
1992 }
1993
1994 if (state->writemask)
1995 dw |= GEN8_ZS_DW1_DEPTH_WRITE_ENABLE;
1996
1997 return dw;
1998 }
1999
2000 static uint32_t
2001 dsa_get_alpha_enable_gen6(const struct ilo_dev_info *dev,
2002 const struct pipe_alpha_state *state)
2003 {
2004 uint32_t dw;
2005
2006 ILO_DEV_ASSERT(dev, 6, 8);
2007
2008 if (!state->enabled)
2009 return 0;
2010
2011 /* this will be ORed to BLEND_STATE */
2012 dw = GEN6_RT_DW1_ALPHA_TEST_ENABLE |
2013 gen6_translate_dsa_func(state->func) << 13;
2014
2015 return dw;
2016 }
2017
2018 void
2019 ilo_gpe_init_dsa(const struct ilo_dev_info *dev,
2020 const struct pipe_depth_stencil_alpha_state *state,
2021 struct ilo_dsa_state *dsa)
2022 {
2023 ILO_DEV_ASSERT(dev, 6, 8);
2024
2025 STATIC_ASSERT(Elements(dsa->payload) >= 3);
2026
2027 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
2028 const uint32_t dw_stencil = dsa_get_stencil_enable_gen8(dev,
2029 &state->stencil[0], &state->stencil[1]);
2030 const uint32_t dw_depth = dsa_get_depth_enable_gen8(dev, &state->depth);
2031
2032 assert(!(dw_stencil & dw_depth));
2033 dsa->payload[0] = dw_stencil | dw_depth;
2034 } else {
2035 dsa->payload[0] = dsa_get_stencil_enable_gen6(dev,
2036 &state->stencil[0], &state->stencil[1]);
2037 dsa->payload[2] = dsa_get_depth_enable_gen6(dev, &state->depth);
2038 }
2039
2040 dsa->payload[1] = state->stencil[0].valuemask << 24 |
2041 state->stencil[0].writemask << 16 |
2042 state->stencil[1].valuemask << 8 |
2043 state->stencil[1].writemask;
2044
2045 dsa->dw_blend_alpha = dsa_get_alpha_enable_gen6(dev, &state->alpha);
2046 dsa->dw_ps_blend_alpha = (state->alpha.enabled) ?
2047 GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE : 0;
2048
2049 dsa->alpha_ref = float_to_ubyte(state->alpha.ref_value);
2050 }
2051
2052 void
2053 ilo_gpe_set_scissor(const struct ilo_dev_info *dev,
2054 unsigned start_slot,
2055 unsigned num_states,
2056 const struct pipe_scissor_state *states,
2057 struct ilo_scissor_state *scissor)
2058 {
2059 unsigned i;
2060
2061 ILO_DEV_ASSERT(dev, 6, 8);
2062
2063 for (i = 0; i < num_states; i++) {
2064 uint16_t min_x, min_y, max_x, max_y;
2065
2066 /* both max and min are inclusive in SCISSOR_RECT */
2067 if (states[i].minx < states[i].maxx &&
2068 states[i].miny < states[i].maxy) {
2069 min_x = states[i].minx;
2070 min_y = states[i].miny;
2071 max_x = states[i].maxx - 1;
2072 max_y = states[i].maxy - 1;
2073 }
2074 else {
2075 /* we have to make min greater than max */
2076 min_x = 1;
2077 min_y = 1;
2078 max_x = 0;
2079 max_y = 0;
2080 }
2081
2082 scissor->payload[(start_slot + i) * 2 + 0] = min_y << 16 | min_x;
2083 scissor->payload[(start_slot + i) * 2 + 1] = max_y << 16 | max_x;
2084 }
2085
2086 if (!start_slot && num_states)
2087 scissor->scissor0 = states[0];
2088 }
2089
2090 void
2091 ilo_gpe_set_scissor_null(const struct ilo_dev_info *dev,
2092 struct ilo_scissor_state *scissor)
2093 {
2094 unsigned i;
2095
2096 for (i = 0; i < Elements(scissor->payload); i += 2) {
2097 scissor->payload[i + 0] = 1 << 16 | 1;
2098 scissor->payload[i + 1] = 0;
2099 }
2100 }
2101
2102 static void
2103 fb_set_blend_caps(const struct ilo_dev_info *dev,
2104 enum pipe_format format,
2105 struct ilo_fb_blend_caps *caps)
2106 {
2107 const struct util_format_description *desc =
2108 util_format_description(format);
2109 const int ch = util_format_get_first_non_void_channel(format);
2110
2111 memset(caps, 0, sizeof(*caps));
2112
2113 if (format == PIPE_FORMAT_NONE || desc->is_mixed)
2114 return;
2115
2116 /*
2117 * From the Sandy Bridge PRM, volume 2 part 1, page 365:
2118 *
2119 * "Logic Ops are only supported on *_UNORM surfaces (excluding _SRGB
2120 * variants), otherwise Logic Ops must be DISABLED."
2121 *
2122 * According to the classic driver, this is lifted on Gen8+.
2123 */
2124 if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
2125 caps->can_logicop = true;
2126 } else {
2127 caps->can_logicop = (ch >= 0 && desc->channel[ch].normalized &&
2128 desc->channel[ch].type == UTIL_FORMAT_TYPE_UNSIGNED &&
2129 desc->colorspace == UTIL_FORMAT_COLORSPACE_RGB);
2130 }
2131
2132 /* no blending for pure integer formats */
2133 caps->can_blend = !util_format_is_pure_integer(format);
2134
2135 /*
2136 * From the Sandy Bridge PRM, volume 2 part 1, page 382:
2137 *
2138 * "Alpha Test can only be enabled if Pixel Shader outputs a float
2139 * alpha value."
2140 */
2141 caps->can_alpha_test = !util_format_is_pure_integer(format);
2142
2143 caps->dst_alpha_forced_one =
2144 (ilo_translate_render_format(dev, format) !=
2145 ilo_translate_color_format(dev, format));
2146
2147 /* sanity check */
2148 if (caps->dst_alpha_forced_one) {
2149 enum pipe_format render_format;
2150
2151 switch (format) {
2152 case PIPE_FORMAT_B8G8R8X8_UNORM:
2153 render_format = PIPE_FORMAT_B8G8R8A8_UNORM;
2154 break;
2155 default:
2156 render_format = PIPE_FORMAT_NONE;
2157 break;
2158 }
2159
2160 assert(ilo_translate_render_format(dev, format) ==
2161 ilo_translate_color_format(dev, render_format));
2162 }
2163 }
2164
2165 void
2166 ilo_gpe_set_fb(const struct ilo_dev_info *dev,
2167 const struct pipe_framebuffer_state *state,
2168 struct ilo_fb_state *fb)
2169 {
2170 const struct pipe_surface *first_surf = NULL;
2171 int i;
2172
2173 ILO_DEV_ASSERT(dev, 6, 8);
2174
2175 util_copy_framebuffer_state(&fb->state, state);
2176
2177 ilo_gpe_init_view_surface_null(dev,
2178 (state->width) ? state->width : 1,
2179 (state->height) ? state->height : 1,
2180 1, 0, &fb->null_rt);
2181
2182 for (i = 0; i < state->nr_cbufs; i++) {
2183 if (state->cbufs[i]) {
2184 fb_set_blend_caps(dev, state->cbufs[i]->format, &fb->blend_caps[i]);
2185
2186 if (!first_surf)
2187 first_surf = state->cbufs[i];
2188 } else {
2189 fb_set_blend_caps(dev, PIPE_FORMAT_NONE, &fb->blend_caps[i]);
2190 }
2191 }
2192
2193 if (!first_surf && state->zsbuf)
2194 first_surf = state->zsbuf;
2195
2196 fb->num_samples = (first_surf) ? first_surf->texture->nr_samples : 1;
2197 if (!fb->num_samples)
2198 fb->num_samples = 1;
2199
2200 /*
2201 * The PRMs list several restrictions when the framebuffer has more than
2202 * one surface. It seems they are actually lifted on GEN6+.
2203 */
2204 }