2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
36 /* These seem to be passed around as function args, so it works out
37 * better to keep them as #defines:
39 #define BRW_FLUSH_READ_CACHE 0x1
40 #define BRW_FLUSH_STATE_CACHE 0x2
41 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
42 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
76 /* State structs for the various fixed function units:
83 GLuint grf_reg_count
:3;
85 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
90 GLuint ext_halt_exception_enable
:1;
91 GLuint sw_exception_enable
:1;
92 GLuint mask_stack_exception_enable
:1;
93 GLuint timeout_exception_enable
:1;
94 GLuint illegal_op_exception_enable
:1;
96 GLuint depth_coef_urb_read_offset
:6; /* WM only */
98 GLuint floating_point_mode
:1;
99 GLuint thread_priority
:1;
100 GLuint binding_table_entry_count
:8;
102 GLuint single_program_flow
:1;
107 GLuint per_thread_scratch_space
:4;
109 GLuint scratch_space_base_pointer
:22;
115 GLuint dispatch_grf_start_reg
:4;
116 GLuint urb_entry_read_offset
:6;
118 GLuint urb_entry_read_length
:6;
120 GLuint const_urb_entry_read_offset
:6;
122 GLuint const_urb_entry_read_length
:6;
128 struct brw_clip_unit_state
130 struct thread0 thread0
;
134 GLuint sw_exception_enable
:1;
136 GLuint mask_stack_exception_enable
:1;
138 GLuint illegal_op_exception_enable
:1;
140 GLuint floating_point_mode
:1;
141 GLuint thread_priority
:1;
142 GLuint binding_table_entry_count
:8;
144 GLuint single_program_flow
:1;
147 struct thread2 thread2
;
148 struct thread3 thread3
;
153 GLuint gs_output_stats
:1; /* not always */
154 GLuint stats_enable
:1;
155 GLuint nr_urb_entries
:7;
157 GLuint urb_entry_allocation_size
:5;
159 GLuint max_threads
:5; /* may be less */
167 GLuint userclip_enable_flags
:8;
168 GLuint userclip_must_clip
:1;
169 GLuint negative_w_clip_test
:1;
170 GLuint guard_band_enable
:1;
171 GLuint viewport_z_clip_enable
:1;
172 GLuint viewport_xy_clip_enable
:1;
173 GLuint vertex_position_space
:1;
181 GLuint clipper_viewport_state_ptr
:27;
185 GLfloat viewport_xmin
;
186 GLfloat viewport_xmax
;
187 GLfloat viewport_ymin
;
188 GLfloat viewport_ymax
;
191 struct gen6_blend_state
194 GLuint dest_blend_factor
:5;
195 GLuint source_blend_factor
:5;
199 GLuint ia_dest_blend_factor
:5;
200 GLuint ia_source_blend_factor
:5;
202 GLuint ia_blend_func
:3;
204 GLuint ia_blend_enable
:1;
205 GLuint blend_enable
:1;
209 GLuint post_blend_clamp_enable
:1;
210 GLuint pre_blend_clamp_enable
:1;
211 GLuint clamp_range
:2;
213 GLuint x_dither_offset
:2;
214 GLuint y_dither_offset
:2;
215 GLuint dither_enable
:1;
216 GLuint alpha_test_func
:3;
217 GLuint alpha_test_enable
:1;
219 GLuint logic_op_func
:4;
220 GLuint logic_op_enable
:1;
222 GLuint write_disable_b
:1;
223 GLuint write_disable_g
:1;
224 GLuint write_disable_r
:1;
225 GLuint write_disable_a
:1;
227 GLuint alpha_to_coverage_dither
:1;
228 GLuint alpha_to_one
:1;
229 GLuint alpha_to_coverage
:1;
233 struct gen6_color_calc_state
236 GLuint alpha_test_format
:1;
238 GLuint round_disable
:1;
239 GLuint bf_stencil_ref
:8;
240 GLuint stencil_ref
:8;
257 struct gen6_depth_stencil_state
261 GLuint bf_stencil_pass_depth_pass_op
:3;
262 GLuint bf_stencil_pass_depth_fail_op
:3;
263 GLuint bf_stencil_fail_op
:3;
264 GLuint bf_stencil_func
:3;
265 GLuint bf_stencil_enable
:1;
267 GLuint stencil_write_enable
:1;
268 GLuint stencil_pass_depth_pass_op
:3;
269 GLuint stencil_pass_depth_fail_op
:3;
270 GLuint stencil_fail_op
:3;
271 GLuint stencil_func
:3;
272 GLuint stencil_enable
:1;
276 GLuint bf_stencil_write_mask
:8;
277 GLuint bf_stencil_test_mask
:8;
278 GLuint stencil_write_mask
:8;
279 GLuint stencil_test_mask
:8;
284 GLuint depth_write_enable
:1;
285 GLuint depth_test_func
:3;
287 GLuint depth_test_enable
:1;
291 struct brw_cc_unit_state
296 GLuint bf_stencil_pass_depth_pass_op
:3;
297 GLuint bf_stencil_pass_depth_fail_op
:3;
298 GLuint bf_stencil_fail_op
:3;
299 GLuint bf_stencil_func
:3;
300 GLuint bf_stencil_enable
:1;
302 GLuint stencil_write_enable
:1;
303 GLuint stencil_pass_depth_pass_op
:3;
304 GLuint stencil_pass_depth_fail_op
:3;
305 GLuint stencil_fail_op
:3;
306 GLuint stencil_func
:3;
307 GLuint stencil_enable
:1;
313 GLuint bf_stencil_ref
:8;
314 GLuint stencil_write_mask
:8;
315 GLuint stencil_test_mask
:8;
316 GLuint stencil_ref
:8;
322 GLuint logicop_enable
:1;
324 GLuint depth_write_enable
:1;
325 GLuint depth_test_function
:3;
327 GLuint bf_stencil_write_mask
:8;
328 GLuint bf_stencil_test_mask
:8;
335 GLuint alpha_test_func
:3;
337 GLuint blend_enable
:1;
338 GLuint ia_blend_enable
:1;
340 GLuint alpha_test_format
:1;
347 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
353 GLuint ia_dest_blend_factor
:5;
354 GLuint ia_src_blend_factor
:5;
355 GLuint ia_blend_function
:3;
356 GLuint statistics_enable
:1;
357 GLuint logicop_func
:4;
359 GLuint dither_enable
:1;
364 GLuint clamp_post_alpha_blend
:1;
365 GLuint clamp_pre_alpha_blend
:1;
366 GLuint clamp_range
:2;
368 GLuint y_dither_offset
:2;
369 GLuint x_dither_offset
:2;
370 GLuint dest_blend_factor
:5;
371 GLuint src_blend_factor
:5;
372 GLuint blend_function
:3;
383 struct brw_sf_unit_state
385 struct thread0 thread0
;
386 struct thread1 thread1
;
387 struct thread2 thread2
;
388 struct thread3 thread3
;
393 GLuint stats_enable
:1;
394 GLuint nr_urb_entries
:7;
396 GLuint urb_entry_allocation_size
:5;
398 GLuint max_threads
:6;
404 GLuint front_winding
:1;
405 GLuint viewport_transform
:1;
407 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
413 GLuint dest_org_vbias
:4;
414 GLuint dest_org_hbias
:4;
416 GLuint disable_2x2_trifilter
:1;
417 GLuint disable_zero_pix_trifilter
:1;
418 GLuint point_rast_rule
:2;
419 GLuint line_endcap_aa_region_width
:2;
421 GLuint fast_scissor_disable
:1;
428 GLuint point_size
:11;
429 GLuint use_point_size_state
:1;
430 GLuint subpixel_precision
:1;
431 GLuint sprite_point
:1;
433 GLuint aa_line_distance_mode
:1;
435 GLuint linestrip_pv
:2;
436 GLuint tristrip_pv
:2;
437 GLuint line_last_pixel_enable
:1;
442 struct gen6_scissor_rect
450 struct brw_gs_unit_state
452 struct thread0 thread0
;
453 struct thread1 thread1
;
454 struct thread2 thread2
;
455 struct thread3 thread3
;
460 GLuint rendering_enable
:1; /* for Ironlake */
462 GLuint stats_enable
:1;
463 GLuint nr_urb_entries
:7;
465 GLuint urb_entry_allocation_size
:5;
467 GLuint max_threads
:5;
473 GLuint sampler_count
:3;
475 GLuint sampler_state_pointer
:27;
481 GLuint max_vp_index
:4;
483 GLuint svbi_post_inc_value
:10;
485 GLuint svbi_post_inc_enable
:1;
486 GLuint svbi_payload
:1;
487 GLuint discard_adjaceny
:1;
488 GLuint reorder_enable
:1;
494 struct brw_vs_unit_state
496 struct thread0 thread0
;
497 struct thread1 thread1
;
498 struct thread2 thread2
;
499 struct thread3 thread3
;
504 GLuint stats_enable
:1;
505 GLuint nr_urb_entries
:7;
507 GLuint urb_entry_allocation_size
:5;
509 GLuint max_threads
:6;
515 GLuint sampler_count
:3;
517 GLuint sampler_state_pointer
:27;
523 GLuint vert_cache_disable
:1;
529 struct brw_wm_unit_state
531 struct thread0 thread0
;
532 struct thread1 thread1
;
533 struct thread2 thread2
;
534 struct thread3 thread3
;
537 GLuint stats_enable
:1;
538 GLuint depth_buffer_clear
:1;
539 GLuint sampler_count
:3;
540 GLuint sampler_state_pointer
:27;
545 GLuint enable_8_pix
:1;
546 GLuint enable_16_pix
:1;
547 GLuint enable_32_pix
:1;
548 GLuint enable_con_32_pix
:1;
549 GLuint enable_con_64_pix
:1;
552 /* These next four bits are for Ironlake+ */
553 GLuint fast_span_coverage_enable
:1;
554 GLuint depth_buffer_clear
:1;
555 GLuint depth_buffer_resolve_enable
:1;
556 GLuint hierarchical_depth_buffer_resolve_enable
:1;
558 GLuint legacy_global_depth_bias
:1;
559 GLuint line_stipple
:1;
560 GLuint depth_offset
:1;
561 GLuint polygon_stipple
:1;
562 GLuint line_aa_region_width
:2;
563 GLuint line_endcap_aa_region_width
:2;
564 GLuint early_depth_test
:1;
565 GLuint thread_dispatch_enable
:1;
566 GLuint program_uses_depth
:1;
567 GLuint program_computes_depth
:1;
568 GLuint program_uses_killpixel
:1;
569 GLuint legacy_line_rast
: 1;
570 GLuint transposed_urb_read_enable
:1;
571 GLuint max_threads
:7;
574 GLfloat global_depth_offset_constant
;
575 GLfloat global_depth_offset_scale
;
577 /* for Ironlake only */
580 GLuint grf_reg_count_1
:3;
582 GLuint kernel_start_pointer_1
:26;
587 GLuint grf_reg_count_2
:3;
589 GLuint kernel_start_pointer_2
:26;
594 GLuint grf_reg_count_3
:3;
596 GLuint kernel_start_pointer_3
:26;
600 struct brw_sampler_default_color
{
604 struct gen5_sampler_default_color
{
613 struct brw_sampler_state
618 GLuint shadow_function
:3;
624 GLuint min_mag_neq
:1;
625 GLuint lod_preclamp
:1;
626 GLuint default_color_mode
:1;
633 GLuint r_wrap_mode
:3;
634 GLuint t_wrap_mode
:3;
635 GLuint s_wrap_mode
:3;
636 GLuint cube_control_mode
:1;
646 GLuint default_color_pointer
:27;
651 GLuint non_normalized_coord
:1;
653 GLuint address_round
:6;
655 GLuint chroma_key_mode
:1;
656 GLuint chroma_key_index
:2;
657 GLuint chroma_key_enable
:1;
658 GLuint monochrome_filter_width
:3;
659 GLuint monochrome_filter_height
:3;
663 struct gen7_sampler_state
667 GLuint aniso_algorithm
:1;
674 GLuint lod_preclamp
:1;
675 GLuint default_color_mode
:1;
682 GLuint cube_control_mode
:1;
683 GLuint shadow_function
:3;
692 GLuint default_color_pointer
:27;
697 GLuint r_wrap_mode
:3;
698 GLuint t_wrap_mode
:3;
699 GLuint s_wrap_mode
:3;
701 GLuint non_normalized_coord
:1;
702 GLuint trilinear_quality
:2;
703 GLuint address_round
:6;
705 GLuint chroma_key_mode
:1;
706 GLuint chroma_key_index
:2;
707 GLuint chroma_key_enable
:1;
712 struct brw_clipper_viewport
720 struct brw_cc_viewport
726 struct brw_sf_viewport
737 /* scissor coordinates are inclusive */
746 struct gen6_sf_viewport
{
755 struct gen7_sf_clip_viewport
{
777 struct brw_vertex_element_state
781 GLuint src_offset
:11;
786 GLuint vertex_buffer_index
:5;
793 GLuint vfcomponent3
:4;
794 GLuint vfcomponent2
:4;
795 GLuint vfcomponent1
:4;
796 GLuint vfcomponent0
:4;
800 struct brw_urb_immediate
{
803 GLuint swizzle_control
:2;
808 GLuint response_length
:4;
812 GLuint end_of_thread
:1;
815 /* Instruction format for the execution units:
818 struct brw_instruction
824 GLuint access_mode
:1;
825 GLuint mask_control
:1;
826 GLuint dependency_control
:2;
827 GLuint compression_control
:2; /* gen6: quarter control */
828 GLuint thread_control
:2;
829 GLuint predicate_control
:4;
830 GLuint predicate_inverse
:1;
831 GLuint execution_size
:3;
833 * Conditional Modifier for most instructions. On Gen6+, this is also
834 * used for the SEND instruction's Message Target/SFID.
836 GLuint destreg__conditionalmod
:4;
837 GLuint acc_wr_control
:1;
838 GLuint cmpt_control
:1;
839 GLuint debug_control
:1;
846 GLuint dest_reg_file
:2;
847 GLuint dest_reg_type
:3;
848 GLuint src0_reg_file
:2;
849 GLuint src0_reg_type
:3;
850 GLuint src1_reg_file
:2;
851 GLuint src1_reg_type
:3;
852 GLuint nibctrl
:1; /* gen7+ */
853 GLuint dest_subreg_nr
:5;
854 GLuint dest_reg_nr
:8;
855 GLuint dest_horiz_stride
:2;
856 GLuint dest_address_mode
:1;
861 GLuint dest_reg_file
:2;
862 GLuint dest_reg_type
:3;
863 GLuint src0_reg_file
:2;
864 GLuint src0_reg_type
:3;
865 GLuint src1_reg_file
:2; /* 0x00000c00 */
866 GLuint src1_reg_type
:3; /* 0x00007000 */
867 GLuint nibctrl
:1; /* gen7+ */
868 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
869 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
870 GLuint dest_horiz_stride
:2;
871 GLuint dest_address_mode
:1;
876 GLuint dest_reg_file
:2;
877 GLuint dest_reg_type
:3;
878 GLuint src0_reg_file
:2;
879 GLuint src0_reg_type
:3;
880 GLuint src1_reg_file
:2;
881 GLuint src1_reg_type
:3;
882 GLuint nibctrl
:1; /* gen7+ */
883 GLuint dest_writemask
:4;
884 GLuint dest_subreg_nr
:1;
885 GLuint dest_reg_nr
:8;
886 GLuint dest_horiz_stride
:2;
887 GLuint dest_address_mode
:1;
892 GLuint dest_reg_file
:2;
893 GLuint dest_reg_type
:3;
894 GLuint src0_reg_file
:2;
895 GLuint src0_reg_type
:3;
896 GLuint src1_reg_file
:2;
897 GLuint src1_reg_type
:3;
898 GLuint nibctrl
:1; /* gen7+ */
899 GLuint dest_writemask
:4;
900 GLint dest_indirect_offset
:6;
901 GLuint dest_subreg_nr
:3;
902 GLuint dest_horiz_stride
:2;
903 GLuint dest_address_mode
:1;
907 GLuint dest_reg_file
:2;
908 GLuint dest_reg_type
:3;
909 GLuint src0_reg_file
:2;
910 GLuint src0_reg_type
:3;
911 GLuint src1_reg_file
:2;
912 GLuint src1_reg_type
:3;
919 GLuint dest_reg_file
:1; /* gen6, not gen7+ */
920 GLuint flag_subreg_num
:1;
921 GLuint flag_reg_nr
:1; /* gen7+ */
924 GLuint src0_negate
:1;
926 GLuint src1_negate
:1;
928 GLuint src2_negate
:1;
929 GLuint src_type
:2; /* gen7+ */
930 GLuint dst_type
:2; /* gen7+ */
932 GLuint nibctrl
:1; /* gen7+ */
934 GLuint dest_writemask
:4;
935 GLuint dest_subreg_nr
:3;
936 GLuint dest_reg_nr
:8;
946 GLuint src0_subreg_nr
:5;
947 GLuint src0_reg_nr
:8;
949 GLuint src0_negate
:1;
950 GLuint src0_address_mode
:1;
951 GLuint src0_horiz_stride
:2;
953 GLuint src0_vert_stride
:4;
954 GLuint flag_subreg_nr
:1;
955 GLuint flag_reg_nr
:1; /* gen7+ */
961 GLint src0_indirect_offset
:10;
962 GLuint src0_subreg_nr
:3;
964 GLuint src0_negate
:1;
965 GLuint src0_address_mode
:1;
966 GLuint src0_horiz_stride
:2;
968 GLuint src0_vert_stride
:4;
969 GLuint flag_subreg_nr
:1;
970 GLuint flag_reg_nr
:1; /* gen7+ */
978 GLuint src0_subreg_nr
:1;
979 GLuint src0_reg_nr
:8;
981 GLuint src0_negate
:1;
982 GLuint src0_address_mode
:1;
986 GLuint src0_vert_stride
:4;
987 GLuint flag_subreg_nr
:1;
988 GLuint flag_reg_nr
:1; /* gen7+ */
996 GLint src0_indirect_offset
:6;
997 GLuint src0_subreg_nr
:3;
999 GLuint src0_negate
:1;
1000 GLuint src0_address_mode
:1;
1001 GLuint src0_swz_z
:2;
1002 GLuint src0_swz_w
:2;
1004 GLuint src0_vert_stride
:4;
1005 GLuint flag_subreg_nr
:1;
1006 GLuint flag_reg_nr
:1; /* gen7+ */
1010 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
1012 * Does not apply to Gen6+. The SFID/message target moved to bits
1013 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1018 GLuint end_of_thread
:1;
1021 } send_gen5
; /* for Ironlake only */
1024 GLuint src0_rep_ctrl
:1;
1025 GLuint src0_swizzle
:8;
1026 GLuint src0_subreg_nr
:3;
1027 GLuint src0_reg_nr
:8;
1029 GLuint src1_rep_ctrl
:1;
1030 GLuint src1_swizzle
:8;
1031 GLuint src1_subreg_nr_low
:2;
1041 GLuint src1_subreg_nr
:5;
1042 GLuint src1_reg_nr
:8;
1044 GLuint src1_negate
:1;
1045 GLuint src1_address_mode
:1;
1046 GLuint src1_horiz_stride
:2;
1047 GLuint src1_width
:3;
1048 GLuint src1_vert_stride
:4;
1054 GLuint src1_swz_x
:2;
1055 GLuint src1_swz_y
:2;
1056 GLuint src1_subreg_nr
:1;
1057 GLuint src1_reg_nr
:8;
1059 GLuint src1_negate
:1;
1060 GLuint src1_address_mode
:1;
1061 GLuint src1_swz_z
:2;
1062 GLuint src1_swz_w
:2;
1064 GLuint src1_vert_stride
:4;
1070 GLint src1_indirect_offset
:10;
1071 GLuint src1_subreg_nr
:3;
1073 GLuint src1_negate
:1;
1074 GLuint src1_address_mode
:1;
1075 GLuint src1_horiz_stride
:2;
1076 GLuint src1_width
:3;
1077 GLuint src1_vert_stride
:4;
1083 GLuint src1_swz_x
:2;
1084 GLuint src1_swz_y
:2;
1085 GLint src1_indirect_offset
:6;
1086 GLuint src1_subreg_nr
:3;
1088 GLuint src1_negate
:1;
1090 GLuint src1_swz_z
:2;
1091 GLuint src1_swz_w
:2;
1093 GLuint src1_vert_stride
:4;
1100 GLint jump_count
:16; /* note: signed */
1105 /* This is also used for gen7 IF/ELSE instructions */
1108 /* Signed jump distance to the ip to jump to if all channels
1109 * are disabled after the break or continue. It should point
1110 * to the end of the innermost control flow block, as that's
1111 * where some channel could get re-enabled.
1115 /* Signed jump distance to the location to resume execution
1116 * of this channel if it's enabled for the break or continue.
1122 * \defgroup SEND instructions / Message Descriptors
1128 * Generic Message Descriptor for Gen4 SEND instructions. The structs
1129 * below expand function_control to something specific for their
1130 * message. Due to struct packing issues, they duplicate these bits.
1132 * See the G45 PRM, Volume 4, Table 14-15.
1135 GLuint function_control
:16;
1136 GLuint response_length
:4;
1137 GLuint msg_length
:4;
1138 GLuint msg_target
:4;
1140 GLuint end_of_thread
:1;
1144 * Generic Message Descriptor for Gen5-7 SEND instructions.
1146 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
1147 * of the information on the SEND instruction is missing from the public
1150 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1151 * According to the SEND instruction description:
1152 * "The MSb of the message description, the EOT field, always comes from
1153 * bit 127 of the instruction word"...which is bit 31 of this field.
1156 GLuint function_control
:19;
1157 GLuint header_present
:1;
1158 GLuint response_length
:5;
1159 GLuint msg_length
:4;
1161 GLuint end_of_thread
:1;
1164 /** G45 PRM, Volume 4, Section 6.1.1.1 */
1172 GLuint response_length
:4;
1173 GLuint msg_length
:4;
1174 GLuint msg_target
:4;
1176 GLuint end_of_thread
:1;
1179 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1188 GLuint header_present
:1;
1189 GLuint response_length
:5;
1190 GLuint msg_length
:4;
1192 GLuint end_of_thread
:1;
1195 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1197 GLuint binding_table_index
:8;
1199 GLuint return_format
:2;
1201 GLuint response_length
:4;
1202 GLuint msg_length
:4;
1203 GLuint msg_target
:4;
1205 GLuint end_of_thread
:1;
1208 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1210 GLuint binding_table_index
:8;
1213 GLuint response_length
:4;
1214 GLuint msg_length
:4;
1215 GLuint msg_target
:4;
1217 GLuint end_of_thread
:1;
1220 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1222 GLuint binding_table_index
:8;
1227 GLuint header_present
:1;
1228 GLuint response_length
:5;
1229 GLuint msg_length
:4;
1231 GLuint end_of_thread
:1;
1235 GLuint binding_table_index
:8;
1239 GLuint header_present
:1;
1240 GLuint response_length
:5;
1241 GLuint msg_length
:4;
1243 GLuint end_of_thread
:1;
1246 struct brw_urb_immediate urb
;
1251 GLuint swizzle_control
:2;
1257 GLuint header_present
:1;
1258 GLuint response_length
:5;
1259 GLuint msg_length
:4;
1261 GLuint end_of_thread
:1;
1267 GLuint swizzle_control
:1;
1269 GLuint per_slot_offset
:1;
1271 GLuint header_present
:1;
1272 GLuint response_length
:5;
1273 GLuint msg_length
:4;
1275 GLuint end_of_thread
:1;
1278 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1280 GLuint binding_table_index
:8;
1281 GLuint msg_control
:4;
1283 GLuint target_cache
:2;
1284 GLuint response_length
:4;
1285 GLuint msg_length
:4;
1286 GLuint msg_target
:4;
1288 GLuint end_of_thread
:1;
1291 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1293 GLuint binding_table_index
:8;
1294 GLuint msg_control
:3;
1296 GLuint target_cache
:2;
1297 GLuint response_length
:4;
1298 GLuint msg_length
:4;
1299 GLuint msg_target
:4;
1301 GLuint end_of_thread
:1;
1304 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1306 GLuint binding_table_index
:8;
1307 GLuint msg_control
:3;
1309 GLuint target_cache
:2;
1311 GLuint header_present
:1;
1312 GLuint response_length
:5;
1313 GLuint msg_length
:4;
1315 GLuint end_of_thread
:1;
1318 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
1320 GLuint binding_table_index
:8;
1321 GLuint msg_control
:3;
1322 GLuint last_render_target
:1;
1324 GLuint send_commit_msg
:1;
1325 GLuint response_length
:4;
1326 GLuint msg_length
:4;
1327 GLuint msg_target
:4;
1329 GLuint end_of_thread
:1;
1332 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1334 GLuint binding_table_index
:8;
1335 GLuint msg_control
:3;
1336 GLuint last_render_target
:1;
1338 GLuint send_commit_msg
:1;
1340 GLuint header_present
:1;
1341 GLuint response_length
:5;
1342 GLuint msg_length
:4;
1344 GLuint end_of_thread
:1;
1348 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1350 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1353 GLuint binding_table_index
:8;
1354 GLuint msg_control
:5;
1357 GLuint header_present
:1;
1358 GLuint response_length
:5;
1359 GLuint msg_length
:4;
1361 GLuint end_of_thread
:1;
1362 } gen6_dp_sampler_const_cache
;
1365 * Message for the Sandybridge Render Cache Data Port.
1367 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1368 * Section 3.9.2.1.1: Message Descriptor.
1370 * "Slot Group Select" and "Last Render Target" are part of the
1371 * 5-bit message control for Render Target Write messages. See
1372 * Section 3.9.9.2.1 of the same volume.
1375 GLuint binding_table_index
:8;
1376 GLuint msg_control
:3;
1377 GLuint slot_group_select
:1;
1378 GLuint last_render_target
:1;
1380 GLuint send_commit_msg
:1;
1382 GLuint header_present
:1;
1383 GLuint response_length
:5;
1384 GLuint msg_length
:4;
1386 GLuint end_of_thread
:1;
1390 * Message for any of the Gen7 Data Port caches.
1392 * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
1393 * Data Port Messages / Message Descriptor. Once again, "Slot Group
1394 * Select" and "Last Render Target" are part of the 6-bit message
1395 * control for Render Target Writes.
1398 GLuint binding_table_index
:8;
1399 GLuint msg_control
:3;
1400 GLuint slot_group_select
:1;
1401 GLuint last_render_target
:1;
1402 GLuint msg_control_pad
:1;
1405 GLuint header_present
:1;
1406 GLuint response_length
:5;
1407 GLuint msg_length
:4;
1409 GLuint end_of_thread
:1;
1414 GLuint src1_subreg_nr_high
:1;
1415 GLuint src1_reg_nr
:8;
1417 GLuint src2_rep_ctrl
:1;
1418 GLuint src2_swizzle
:8;
1419 GLuint src2_subreg_nr
:3;
1420 GLuint src2_reg_nr
:8;
1430 struct brw_compact_instruction
{
1432 unsigned opcode
:7; /* 0- 6 */
1433 unsigned debug_control
:1; /* 7- 7 */
1434 unsigned control_index
:5; /* 8-12 */
1435 unsigned data_type_index
:5; /* 13-17 */
1436 unsigned sub_reg_index
:5; /* 18-22 */
1437 unsigned acc_wr_control
:1; /* 23-23 */
1438 unsigned conditionalmod
:4; /* 24-27 */
1439 unsigned flag_subreg_nr
:1; /* 28-28 */
1440 unsigned cmpt_ctrl
:1; /* 29-29 */
1441 unsigned src0_index
:2; /* 30-31 */
1445 unsigned src0_index
:3; /* 32-24 */
1446 unsigned src1_index
:5; /* 35-39 */
1447 unsigned dst_reg_nr
:8; /* 40-47 */
1448 unsigned src0_reg_nr
:8; /* 48-55 */
1449 unsigned src1_reg_nr
:8; /* 56-63 */