iris: Tag each submitted batch with a syncobj
[mesa.git] / src / gallium / drivers / iris / iris_batch.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_batch.c
25 *
26 * Batchbuffer and command submission module.
27 *
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
31 *
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
38 */
39
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
44
45 #include "drm-uapi/i915_drm.h"
46
47 #include "util/hash_table.h"
48 #include "util/set.h"
49 #include "main/macros.h"
50
51 #include <errno.h>
52 #include <xf86drm.h>
53
54 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
55
56 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
57 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
58 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
59 */
60 #define BATCH_RESERVED 16
61
62 static void
63 iris_batch_reset(struct iris_batch *batch);
64
65 static unsigned
66 num_fences(struct iris_batch *batch)
67 {
68 return util_dynarray_num_elements(&batch->exec_fences,
69 struct drm_i915_gem_exec_fence);
70 }
71
72 /**
73 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
74 */
75 static void
76 dump_fence_list(struct iris_batch *batch)
77 {
78 fprintf(stderr, "Fence list (length %u): ", num_fences(batch));
79
80 util_dynarray_foreach(&batch->exec_fences,
81 struct drm_i915_gem_exec_fence, f) {
82 fprintf(stderr, "%s%u%s ",
83 (f->flags & I915_EXEC_FENCE_WAIT) ? "..." : "",
84 f->handle,
85 (f->flags & I915_EXEC_FENCE_SIGNAL) ? "!" : "");
86 }
87
88 fprintf(stderr, "\n");
89 }
90
91 /**
92 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
93 */
94 static void
95 dump_validation_list(struct iris_batch *batch)
96 {
97 fprintf(stderr, "Validation list (length %d):\n", batch->exec_count);
98
99 for (int i = 0; i < batch->exec_count; i++) {
100 uint64_t flags = batch->validation_list[i].flags;
101 assert(batch->validation_list[i].handle ==
102 batch->exec_bos[i]->gem_handle);
103 fprintf(stderr, "[%2d]: %2d %-14s %p %-7s @ 0x%016llx (%"PRIu64"B) - %d refs\n",
104 i,
105 batch->validation_list[i].handle,
106 batch->exec_bos[i]->name,
107 batch->exec_bos[i],
108 (flags & EXEC_OBJECT_WRITE) ? "(write)" : "",
109 batch->validation_list[i].offset,
110 batch->exec_bos[i]->size,
111 batch->exec_bos[i]->refcount);
112 }
113 }
114
115 /**
116 * Return BO information to the batch decoder (for debugging).
117 */
118 static struct gen_batch_decode_bo
119 decode_get_bo(void *v_batch, uint64_t address)
120 {
121 struct iris_batch *batch = v_batch;
122
123 for (int i = 0; i < batch->exec_count; i++) {
124 struct iris_bo *bo = batch->exec_bos[i];
125 /* The decoder zeroes out the top 16 bits, so we need to as well */
126 uint64_t bo_address = bo->gtt_offset & (~0ull >> 16);
127
128 if (address >= bo_address && address < bo_address + bo->size) {
129 return (struct gen_batch_decode_bo) {
130 .addr = address,
131 .size = bo->size,
132 .map = iris_bo_map(batch->dbg, bo, MAP_READ) +
133 (address - bo_address),
134 };
135 }
136 }
137
138 return (struct gen_batch_decode_bo) { };
139 }
140
141 /**
142 * Decode the current batch.
143 */
144 static void
145 decode_batch(struct iris_batch *batch)
146 {
147 void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
148 gen_print_batch(&batch->decoder, map, batch->primary_batch_size,
149 batch->exec_bos[0]->gtt_offset);
150 }
151
152 static bool
153 uint_key_compare(const void *a, const void *b)
154 {
155 return a == b;
156 }
157
158 static uint32_t
159 uint_key_hash(const void *key)
160 {
161 return (uintptr_t) key;
162 }
163
164 void
165 iris_init_batch(struct iris_batch *batch,
166 struct iris_screen *screen,
167 struct iris_vtable *vtbl,
168 struct pipe_debug_callback *dbg,
169 struct iris_batch **all_batches,
170 const char *name,
171 uint8_t engine)
172 {
173 batch->screen = screen;
174 batch->vtbl = vtbl;
175 batch->dbg = dbg;
176 batch->name = name;
177
178 /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
179 assert((engine & ~I915_EXEC_RING_MASK) == 0);
180 assert(util_bitcount(engine) == 1);
181 batch->engine = engine;
182
183 batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
184 assert(batch->hw_ctx_id);
185
186 util_dynarray_init(&batch->exec_fences, ralloc_context(NULL));
187 util_dynarray_init(&batch->syncpts, ralloc_context(NULL));
188
189 batch->exec_count = 0;
190 batch->exec_array_size = 100;
191 batch->exec_bos =
192 malloc(batch->exec_array_size * sizeof(batch->exec_bos[0]));
193 batch->validation_list =
194 malloc(batch->exec_array_size * sizeof(batch->validation_list[0]));
195
196 batch->cache.render = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
197 _mesa_key_pointer_equal);
198 batch->cache.depth = _mesa_set_create(NULL, _mesa_hash_pointer,
199 _mesa_key_pointer_equal);
200
201 memset(batch->other_batches, 0, sizeof(batch->other_batches));
202
203 for (int i = 0, j = 0; i < IRIS_BATCH_COUNT; i++) {
204 if (all_batches[i] != batch)
205 batch->other_batches[j++] = all_batches[i];
206 }
207
208 if (unlikely(INTEL_DEBUG)) {
209 batch->state_sizes =
210 _mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);
211
212 const unsigned decode_flags =
213 GEN_BATCH_DECODE_FULL |
214 ((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
215 GEN_BATCH_DECODE_OFFSETS |
216 GEN_BATCH_DECODE_FLOATS;
217
218 gen_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
219 stderr, decode_flags, NULL,
220 decode_get_bo, NULL, batch);
221 batch->decoder.max_vbo_decoded_lines = 32;
222 }
223
224 iris_batch_reset(batch);
225 }
226
227 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
228
229 static struct drm_i915_gem_exec_object2 *
230 find_validation_entry(struct iris_batch *batch, struct iris_bo *bo)
231 {
232 unsigned index = READ_ONCE(bo->index);
233
234 if (index < batch->exec_count && batch->exec_bos[index] == bo)
235 return &batch->validation_list[index];
236
237 /* May have been shared between multiple active batches */
238 for (index = 0; index < batch->exec_count; index++) {
239 if (batch->exec_bos[index] == bo)
240 return &batch->validation_list[index];
241 }
242
243 return NULL;
244 }
245
246 /**
247 * Add a buffer to the current batch's validation list.
248 *
249 * You must call this on any BO you wish to use in this batch, to ensure
250 * that it's resident when the GPU commands execute.
251 */
252 void
253 iris_use_pinned_bo(struct iris_batch *batch,
254 struct iris_bo *bo,
255 bool writable)
256 {
257 assert(bo->kflags & EXEC_OBJECT_PINNED);
258
259 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
260 * about the order of any writes to that buffer, and marking it writable
261 * would introduce data dependencies between multiple batches which share
262 * the buffer.
263 */
264 if (bo == batch->screen->workaround_bo)
265 writable = false;
266
267 struct drm_i915_gem_exec_object2 *existing_entry =
268 find_validation_entry(batch, bo);
269
270 if (existing_entry) {
271 /* The BO is already in the validation list; mark it writable */
272 if (writable)
273 existing_entry->flags |= EXEC_OBJECT_WRITE;
274
275 return;
276 }
277
278 /* This is the first time our batch has seen this BO. Before we use it,
279 * we may need to flush and synchronize with other batches.
280 */
281 for (int b = 0; b < ARRAY_SIZE(batch->other_batches); b++) {
282 struct drm_i915_gem_exec_object2 *other_entry =
283 find_validation_entry(batch->other_batches[b], bo);
284
285 /* If the buffer is referenced by another batch, and either batch
286 * intends to write it, then flush the other batch and synchronize.
287 *
288 * Consider these cases:
289 *
290 * 1. They read, we read => No synchronization required.
291 * 2. They read, we write => Synchronize (they need the old value)
292 * 3. They write, we read => Synchronize (we need their new value)
293 * 4. They write, we write => Synchronize (order writes)
294 *
295 * The read/read case is very common, as multiple batches usually
296 * share a streaming state buffer or shader assembly buffer, and
297 * we want to avoid synchronizing in this case.
298 */
299 if (other_entry &&
300 ((other_entry->flags & EXEC_OBJECT_WRITE) || writable)) {
301 iris_batch_flush(batch->other_batches[b]);
302 }
303 }
304
305 /* Now, take a reference and add it to the validation list. */
306 iris_bo_reference(bo);
307
308 if (batch->exec_count == batch->exec_array_size) {
309 batch->exec_array_size *= 2;
310 batch->exec_bos =
311 realloc(batch->exec_bos,
312 batch->exec_array_size * sizeof(batch->exec_bos[0]));
313 batch->validation_list =
314 realloc(batch->validation_list,
315 batch->exec_array_size * sizeof(batch->validation_list[0]));
316 }
317
318 batch->validation_list[batch->exec_count] =
319 (struct drm_i915_gem_exec_object2) {
320 .handle = bo->gem_handle,
321 .offset = bo->gtt_offset,
322 .flags = bo->kflags | (writable ? EXEC_OBJECT_WRITE : 0),
323 };
324
325 bo->index = batch->exec_count;
326 batch->exec_bos[batch->exec_count] = bo;
327 batch->aperture_space += bo->size;
328
329 batch->exec_count++;
330 }
331
332 static void
333 create_batch(struct iris_batch *batch)
334 {
335 struct iris_screen *screen = batch->screen;
336 struct iris_bufmgr *bufmgr = screen->bufmgr;
337
338 batch->bo = iris_bo_alloc(bufmgr, "command buffer",
339 BATCH_SZ + BATCH_RESERVED, IRIS_MEMZONE_OTHER);
340 batch->bo->kflags |= EXEC_OBJECT_CAPTURE;
341 batch->map = iris_bo_map(NULL, batch->bo, MAP_READ | MAP_WRITE);
342 batch->map_next = batch->map;
343
344 iris_use_pinned_bo(batch, batch->bo, false);
345 }
346
347 static void
348 iris_batch_reset(struct iris_batch *batch)
349 {
350 struct iris_screen *screen = batch->screen;
351
352 iris_bo_unreference(batch->bo);
353 batch->primary_batch_size = 0;
354 batch->contains_draw = false;
355
356 create_batch(batch);
357 assert(batch->bo->index == 0);
358
359 struct iris_syncpt *syncpt = iris_create_syncpt(screen);
360 iris_batch_add_syncpt(batch, syncpt, I915_EXEC_FENCE_SIGNAL);
361 iris_syncpt_reference(screen, &syncpt, NULL);
362
363 if (batch->state_sizes)
364 _mesa_hash_table_clear(batch->state_sizes, NULL);
365
366 iris_cache_sets_clear(batch);
367 }
368
369 void
370 iris_batch_free(struct iris_batch *batch)
371 {
372 struct iris_screen *screen = batch->screen;
373 struct iris_bufmgr *bufmgr = screen->bufmgr;
374
375 for (int i = 0; i < batch->exec_count; i++) {
376 iris_bo_unreference(batch->exec_bos[i]);
377 }
378 free(batch->exec_bos);
379 free(batch->validation_list);
380
381 ralloc_free(batch->exec_fences.mem_ctx);
382
383 util_dynarray_foreach(&batch->syncpts, struct iris_syncpt *, s)
384 iris_syncpt_reference(screen, s, NULL);
385 ralloc_free(batch->syncpts.mem_ctx);
386
387 iris_bo_unreference(batch->bo);
388 batch->bo = NULL;
389 batch->map = NULL;
390 batch->map_next = NULL;
391
392 iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
393
394 _mesa_hash_table_destroy(batch->cache.render, NULL);
395 _mesa_set_destroy(batch->cache.depth, NULL);
396
397 if (batch->state_sizes) {
398 _mesa_hash_table_destroy(batch->state_sizes, NULL);
399 gen_batch_decode_ctx_finish(&batch->decoder);
400 }
401 }
402
403 /**
404 * If we've chained to a secondary batch, or are getting near to the end,
405 * then flush. This should only be called between draws.
406 */
407 void
408 iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate)
409 {
410 if (batch->bo != batch->exec_bos[0] ||
411 iris_batch_bytes_used(batch) + estimate >= BATCH_SZ) {
412 iris_batch_flush(batch);
413 }
414 }
415
416 void
417 iris_chain_to_new_batch(struct iris_batch *batch)
418 {
419 /* We only support chaining a single time. */
420 assert(batch->bo == batch->exec_bos[0]);
421
422 uint32_t *cmd = batch->map_next;
423 uint64_t *addr = batch->map_next + 4;
424 batch->map_next += 8;
425
426 /* No longer held by batch->bo, still held by validation list */
427 iris_bo_unreference(batch->bo);
428 batch->primary_batch_size = iris_batch_bytes_used(batch);
429 create_batch(batch);
430
431 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
432 *cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
433 *addr = batch->bo->gtt_offset;
434 }
435
436 /**
437 * Terminate a batch with MI_BATCH_BUFFER_END.
438 */
439 static void
440 iris_finish_batch(struct iris_batch *batch)
441 {
442 // XXX: ISP DIS
443
444 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
445 uint32_t *map = batch->map_next;
446
447 map[0] = (0xA << 23);
448
449 batch->map_next += 4;
450
451 if (batch->bo == batch->exec_bos[0])
452 batch->primary_batch_size = iris_batch_bytes_used(batch);
453 }
454
455 /**
456 * Submit the batch to the GPU via execbuffer2.
457 */
458 static int
459 submit_batch(struct iris_batch *batch)
460 {
461 iris_bo_unmap(batch->bo);
462
463 /* The requirement for using I915_EXEC_NO_RELOC are:
464 *
465 * The addresses written in the objects must match the corresponding
466 * reloc.gtt_offset which in turn must match the corresponding
467 * execobject.offset.
468 *
469 * Any render targets written to in the batch must be flagged with
470 * EXEC_OBJECT_WRITE.
471 *
472 * To avoid stalling, execobject.offset should match the current
473 * address of that object within the active context.
474 */
475 struct drm_i915_gem_execbuffer2 execbuf = {
476 .buffers_ptr = (uintptr_t) batch->validation_list,
477 .buffer_count = batch->exec_count,
478 .batch_start_offset = 0,
479 /* This must be QWord aligned. */
480 .batch_len = ALIGN(batch->primary_batch_size, 8),
481 .flags = batch->engine |
482 I915_EXEC_NO_RELOC |
483 I915_EXEC_BATCH_FIRST |
484 I915_EXEC_HANDLE_LUT,
485 .rsvd1 = batch->hw_ctx_id, /* rsvd1 is actually the context ID */
486 };
487
488 if (num_fences(batch)) {
489 execbuf.flags |= I915_EXEC_FENCE_ARRAY;
490 execbuf.num_cliprects = num_fences(batch);
491 execbuf.cliprects_ptr =
492 (uintptr_t)util_dynarray_begin(&batch->exec_fences);
493 }
494
495 int ret = drm_ioctl(batch->screen->fd,
496 DRM_IOCTL_I915_GEM_EXECBUFFER2,
497 &execbuf);
498 if (ret != 0) {
499 ret = -errno;
500 DBG("execbuf FAILED: errno = %d\n", -ret);
501 fprintf(stderr, "execbuf FAILED: errno = %d\n", -ret);
502 abort();
503 } else {
504 DBG("execbuf succeeded\n");
505 }
506
507 for (int i = 0; i < batch->exec_count; i++) {
508 struct iris_bo *bo = batch->exec_bos[i];
509
510 bo->idle = false;
511 bo->index = -1;
512
513 iris_bo_unreference(bo);
514 }
515
516 return ret;
517 }
518
519 /**
520 * Flush the batch buffer, submitting it to the GPU and resetting it so
521 * we're ready to emit the next batch.
522 *
523 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
524 * ownership of the fd.
525 *
526 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
527 * take ownership of the returned fd.
528 */
529 void
530 _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
531 {
532 struct iris_screen *screen = batch->screen;
533
534 if (iris_batch_bytes_used(batch) == 0)
535 return;
536
537 iris_finish_batch(batch);
538
539 if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
540 int bytes_for_commands = iris_batch_bytes_used(batch);
541 int second_bytes = 0;
542 if (batch->bo != batch->exec_bos[0]) {
543 second_bytes = bytes_for_commands;
544 bytes_for_commands += batch->primary_batch_size;
545 }
546 fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) "
547 "(cmds), %4d BOs (%0.1fMb aperture)\n",
548 file, line, batch->name, batch->hw_ctx_id,
549 batch->primary_batch_size, second_bytes,
550 100.0f * bytes_for_commands / BATCH_SZ,
551 batch->exec_count,
552 (float) batch->aperture_space / (1024 * 1024));
553 dump_fence_list(batch);
554 dump_validation_list(batch);
555 }
556
557 if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
558 decode_batch(batch);
559 }
560
561 int ret = submit_batch(batch);
562
563 if (ret >= 0) {
564 //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
565 //iris_check_for_reset(ice);
566
567 if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
568 dbg_printf("waiting for idle\n");
569 iris_bo_wait_rendering(batch->bo);
570 }
571 } else {
572 #ifdef DEBUG
573 const bool color = INTEL_DEBUG & DEBUG_COLOR;
574 fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
575 color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
576 abort();
577 #endif
578 }
579
580 batch->exec_count = 0;
581 batch->aperture_space = 0;
582
583 util_dynarray_foreach(&batch->syncpts, struct iris_syncpt *, s)
584 iris_syncpt_reference(screen, s, NULL);
585 util_dynarray_clear(&batch->syncpts);
586
587 util_dynarray_clear(&batch->exec_fences);
588
589 /* Start a new batch buffer. */
590 iris_batch_reset(batch);
591 }
592
593 /**
594 * Does the current batch refer to the given BO?
595 *
596 * (In other words, is the BO in the current batch's validation list?)
597 */
598 bool
599 iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
600 {
601 return find_validation_entry(batch, bo) != NULL;
602 }