2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
45 #include "drm-uapi/i915_drm.h"
47 #include "util/hash_table.h"
49 #include "main/macros.h"
54 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
56 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
57 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
58 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
60 #define BATCH_RESERVED 16
63 iris_batch_reset(struct iris_batch
*batch
);
66 num_fences(struct iris_batch
*batch
)
68 return util_dynarray_num_elements(&batch
->exec_fences
,
69 struct drm_i915_gem_exec_fence
);
73 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
76 dump_fence_list(struct iris_batch
*batch
)
78 fprintf(stderr
, "Fence list (length %u): ", num_fences(batch
));
80 util_dynarray_foreach(&batch
->exec_fences
,
81 struct drm_i915_gem_exec_fence
, f
) {
82 fprintf(stderr
, "%s%u%s ",
83 (f
->flags
& I915_EXEC_FENCE_WAIT
) ? "..." : "",
85 (f
->flags
& I915_EXEC_FENCE_SIGNAL
) ? "!" : "");
88 fprintf(stderr
, "\n");
92 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
95 dump_validation_list(struct iris_batch
*batch
)
97 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
99 for (int i
= 0; i
< batch
->exec_count
; i
++) {
100 uint64_t flags
= batch
->validation_list
[i
].flags
;
101 assert(batch
->validation_list
[i
].handle
==
102 batch
->exec_bos
[i
]->gem_handle
);
103 fprintf(stderr
, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64
"B)\t %2d refs %s\n",
105 batch
->validation_list
[i
].handle
,
106 batch
->exec_bos
[i
]->name
,
107 batch
->validation_list
[i
].offset
,
108 batch
->exec_bos
[i
]->size
,
109 batch
->exec_bos
[i
]->refcount
,
110 (flags
& EXEC_OBJECT_WRITE
) ? " (write)" : "");
115 * Return BO information to the batch decoder (for debugging).
117 static struct gen_batch_decode_bo
118 decode_get_bo(void *v_batch
, uint64_t address
)
120 struct iris_batch
*batch
= v_batch
;
122 for (int i
= 0; i
< batch
->exec_count
; i
++) {
123 struct iris_bo
*bo
= batch
->exec_bos
[i
];
124 /* The decoder zeroes out the top 16 bits, so we need to as well */
125 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
127 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
128 return (struct gen_batch_decode_bo
) {
131 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
132 (address
- bo_address
),
137 return (struct gen_batch_decode_bo
) { };
141 * Decode the current batch.
144 decode_batch(struct iris_batch
*batch
)
146 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
147 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
148 batch
->exec_bos
[0]->gtt_offset
);
152 uint_key_compare(const void *a
, const void *b
)
158 uint_key_hash(const void *key
)
160 return (uintptr_t) key
;
164 iris_init_batch(struct iris_batch
*batch
,
165 struct iris_screen
*screen
,
166 struct iris_vtable
*vtbl
,
167 struct pipe_debug_callback
*dbg
,
168 struct iris_batch
*all_batches
,
169 enum iris_batch_name name
,
172 batch
->screen
= screen
;
177 /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
178 assert((engine
& ~I915_EXEC_RING_MASK
) == 0);
179 assert(util_bitcount(engine
) == 1);
180 batch
->engine
= engine
;
182 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
183 assert(batch
->hw_ctx_id
);
185 util_dynarray_init(&batch
->exec_fences
, ralloc_context(NULL
));
186 util_dynarray_init(&batch
->syncpts
, ralloc_context(NULL
));
188 batch
->exec_count
= 0;
189 batch
->exec_array_size
= 100;
191 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
192 batch
->validation_list
=
193 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
195 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
196 _mesa_key_pointer_equal
);
197 batch
->cache
.depth
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
198 _mesa_key_pointer_equal
);
200 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
202 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
203 if (&all_batches
[i
] != batch
)
204 batch
->other_batches
[j
++] = &all_batches
[i
];
207 if (unlikely(INTEL_DEBUG
)) {
209 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
211 const unsigned decode_flags
=
212 GEN_BATCH_DECODE_FULL
|
213 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
214 GEN_BATCH_DECODE_OFFSETS
|
215 GEN_BATCH_DECODE_FLOATS
;
217 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
218 stderr
, decode_flags
, NULL
,
219 decode_get_bo
, NULL
, batch
);
220 batch
->decoder
.max_vbo_decoded_lines
= 32;
223 iris_batch_reset(batch
);
226 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
228 static struct drm_i915_gem_exec_object2
*
229 find_validation_entry(struct iris_batch
*batch
, struct iris_bo
*bo
)
231 unsigned index
= READ_ONCE(bo
->index
);
233 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
234 return &batch
->validation_list
[index
];
236 /* May have been shared between multiple active batches */
237 for (index
= 0; index
< batch
->exec_count
; index
++) {
238 if (batch
->exec_bos
[index
] == bo
)
239 return &batch
->validation_list
[index
];
246 * Add a buffer to the current batch's validation list.
248 * You must call this on any BO you wish to use in this batch, to ensure
249 * that it's resident when the GPU commands execute.
252 iris_use_pinned_bo(struct iris_batch
*batch
,
256 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
258 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
259 * about the order of any writes to that buffer, and marking it writable
260 * would introduce data dependencies between multiple batches which share
263 if (bo
== batch
->screen
->workaround_bo
)
266 struct drm_i915_gem_exec_object2
*existing_entry
=
267 find_validation_entry(batch
, bo
);
269 if (existing_entry
) {
270 /* The BO is already in the validation list; mark it writable */
272 existing_entry
->flags
|= EXEC_OBJECT_WRITE
;
277 if (bo
!= batch
->bo
) {
278 /* This is the first time our batch has seen this BO. Before we use it,
279 * we may need to flush and synchronize with other batches.
281 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
282 struct drm_i915_gem_exec_object2
*other_entry
=
283 find_validation_entry(batch
->other_batches
[b
], bo
);
285 /* If the buffer is referenced by another batch, and either batch
286 * intends to write it, then flush the other batch and synchronize.
288 * Consider these cases:
290 * 1. They read, we read => No synchronization required.
291 * 2. They read, we write => Synchronize (they need the old value)
292 * 3. They write, we read => Synchronize (we need their new value)
293 * 4. They write, we write => Synchronize (order writes)
295 * The read/read case is very common, as multiple batches usually
296 * share a streaming state buffer or shader assembly buffer, and
297 * we want to avoid synchronizing in this case.
300 ((other_entry
->flags
& EXEC_OBJECT_WRITE
) || writable
)) {
301 iris_batch_flush(batch
->other_batches
[b
]);
302 iris_batch_add_syncpt(batch
, batch
->other_batches
[b
]->last_syncpt
,
303 I915_EXEC_FENCE_WAIT
);
308 /* Now, take a reference and add it to the validation list. */
309 iris_bo_reference(bo
);
311 if (batch
->exec_count
== batch
->exec_array_size
) {
312 batch
->exec_array_size
*= 2;
314 realloc(batch
->exec_bos
,
315 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
316 batch
->validation_list
=
317 realloc(batch
->validation_list
,
318 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
321 batch
->validation_list
[batch
->exec_count
] =
322 (struct drm_i915_gem_exec_object2
) {
323 .handle
= bo
->gem_handle
,
324 .offset
= bo
->gtt_offset
,
325 .flags
= bo
->kflags
| (writable
? EXEC_OBJECT_WRITE
: 0),
328 bo
->index
= batch
->exec_count
;
329 batch
->exec_bos
[batch
->exec_count
] = bo
;
330 batch
->aperture_space
+= bo
->size
;
336 create_batch(struct iris_batch
*batch
)
338 struct iris_screen
*screen
= batch
->screen
;
339 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
341 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
342 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
343 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
344 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
345 batch
->map_next
= batch
->map
;
347 iris_use_pinned_bo(batch
, batch
->bo
, false);
351 iris_batch_reset(struct iris_batch
*batch
)
353 struct iris_screen
*screen
= batch
->screen
;
355 iris_bo_unreference(batch
->bo
);
356 batch
->primary_batch_size
= 0;
357 batch
->contains_draw
= false;
360 assert(batch
->bo
->index
== 0);
362 struct iris_syncpt
*syncpt
= iris_create_syncpt(screen
);
363 iris_batch_add_syncpt(batch
, syncpt
, I915_EXEC_FENCE_SIGNAL
);
364 iris_syncpt_reference(screen
, &syncpt
, NULL
);
366 if (batch
->state_sizes
)
367 _mesa_hash_table_clear(batch
->state_sizes
, NULL
);
369 iris_cache_sets_clear(batch
);
373 iris_batch_free(struct iris_batch
*batch
)
375 struct iris_screen
*screen
= batch
->screen
;
376 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
378 for (int i
= 0; i
< batch
->exec_count
; i
++) {
379 iris_bo_unreference(batch
->exec_bos
[i
]);
381 free(batch
->exec_bos
);
382 free(batch
->validation_list
);
384 ralloc_free(batch
->exec_fences
.mem_ctx
);
386 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
387 iris_syncpt_reference(screen
, s
, NULL
);
388 ralloc_free(batch
->syncpts
.mem_ctx
);
390 iris_syncpt_reference(screen
, &batch
->last_syncpt
, NULL
);
392 iris_bo_unreference(batch
->bo
);
395 batch
->map_next
= NULL
;
397 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
399 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
400 _mesa_set_destroy(batch
->cache
.depth
, NULL
);
402 if (batch
->state_sizes
) {
403 _mesa_hash_table_destroy(batch
->state_sizes
, NULL
);
404 gen_batch_decode_ctx_finish(&batch
->decoder
);
409 * If we've chained to a secondary batch, or are getting near to the end,
410 * then flush. This should only be called between draws.
413 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
415 if (batch
->bo
!= batch
->exec_bos
[0] ||
416 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
417 iris_batch_flush(batch
);
422 iris_chain_to_new_batch(struct iris_batch
*batch
)
424 /* We only support chaining a single time. */
425 assert(batch
->bo
== batch
->exec_bos
[0]);
427 uint32_t *cmd
= batch
->map_next
;
428 uint64_t *addr
= batch
->map_next
+ 4;
429 batch
->map_next
+= 8;
431 /* No longer held by batch->bo, still held by validation list */
432 iris_bo_unreference(batch
->bo
);
433 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
436 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
437 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
438 *addr
= batch
->bo
->gtt_offset
;
442 * Terminate a batch with MI_BATCH_BUFFER_END.
445 iris_finish_batch(struct iris_batch
*batch
)
449 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
450 uint32_t *map
= batch
->map_next
;
452 map
[0] = (0xA << 23);
454 batch
->map_next
+= 4;
456 if (batch
->bo
== batch
->exec_bos
[0])
457 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
461 * Submit the batch to the GPU via execbuffer2.
464 submit_batch(struct iris_batch
*batch
)
466 iris_bo_unmap(batch
->bo
);
468 /* The requirement for using I915_EXEC_NO_RELOC are:
470 * The addresses written in the objects must match the corresponding
471 * reloc.gtt_offset which in turn must match the corresponding
474 * Any render targets written to in the batch must be flagged with
477 * To avoid stalling, execobject.offset should match the current
478 * address of that object within the active context.
480 struct drm_i915_gem_execbuffer2 execbuf
= {
481 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
482 .buffer_count
= batch
->exec_count
,
483 .batch_start_offset
= 0,
484 /* This must be QWord aligned. */
485 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
486 .flags
= batch
->engine
|
488 I915_EXEC_BATCH_FIRST
|
489 I915_EXEC_HANDLE_LUT
,
490 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
493 if (num_fences(batch
)) {
494 execbuf
.flags
|= I915_EXEC_FENCE_ARRAY
;
495 execbuf
.num_cliprects
= num_fences(batch
);
496 execbuf
.cliprects_ptr
=
497 (uintptr_t)util_dynarray_begin(&batch
->exec_fences
);
500 int ret
= drm_ioctl(batch
->screen
->fd
,
501 DRM_IOCTL_I915_GEM_EXECBUFFER2
,
505 DBG("execbuf FAILED: errno = %d\n", -ret
);
506 fprintf(stderr
, "execbuf FAILED: errno = %d\n", -ret
);
509 DBG("execbuf succeeded\n");
512 for (int i
= 0; i
< batch
->exec_count
; i
++) {
513 struct iris_bo
*bo
= batch
->exec_bos
[i
];
518 iris_bo_unreference(bo
);
525 batch_name_to_string(enum iris_batch_name name
)
527 const char *names
[IRIS_BATCH_COUNT
] = {
528 [IRIS_BATCH_RENDER
] = "render",
529 [IRIS_BATCH_COMPUTE
] = "compute",
535 * Flush the batch buffer, submitting it to the GPU and resetting it so
536 * we're ready to emit the next batch.
538 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
539 * ownership of the fd.
541 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
542 * take ownership of the returned fd.
545 _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
)
547 struct iris_screen
*screen
= batch
->screen
;
549 if (iris_batch_bytes_used(batch
) == 0)
552 iris_finish_batch(batch
);
554 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
555 int bytes_for_commands
= iris_batch_bytes_used(batch
);
556 int second_bytes
= 0;
557 if (batch
->bo
!= batch
->exec_bos
[0]) {
558 second_bytes
= bytes_for_commands
;
559 bytes_for_commands
+= batch
->primary_batch_size
;
561 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) "
562 "(cmds), %4d BOs (%0.1fMb aperture)\n",
563 file
, line
, batch_name_to_string(batch
->name
), batch
->hw_ctx_id
,
564 batch
->primary_batch_size
, second_bytes
,
565 100.0f
* bytes_for_commands
/ BATCH_SZ
,
567 (float) batch
->aperture_space
/ (1024 * 1024));
568 dump_fence_list(batch
);
569 dump_validation_list(batch
);
572 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
576 int ret
= submit_batch(batch
);
579 //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
580 //iris_check_for_reset(ice);
582 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
583 dbg_printf("waiting for idle\n");
584 iris_bo_wait_rendering(batch
->bo
);
588 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
589 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
590 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
595 batch
->exec_count
= 0;
596 batch
->aperture_space
= 0;
598 struct iris_syncpt
*syncpt
=
599 ((struct iris_syncpt
**) util_dynarray_begin(&batch
->syncpts
))[0];
600 iris_syncpt_reference(screen
, &batch
->last_syncpt
, syncpt
);
602 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
603 iris_syncpt_reference(screen
, s
, NULL
);
604 util_dynarray_clear(&batch
->syncpts
);
606 util_dynarray_clear(&batch
->exec_fences
);
608 /* Start a new batch buffer. */
609 iris_batch_reset(batch
);
613 * Does the current batch refer to the given BO?
615 * (In other words, is the BO in the current batch's validation list?)
618 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
620 return find_validation_entry(batch
, bo
) != NULL
;