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20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
45 #include "drm-uapi/i915_drm.h"
47 #include "util/hash_table.h"
49 #include "main/macros.h"
54 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
56 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
57 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
58 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
60 #define BATCH_RESERVED 16
63 iris_batch_reset(struct iris_batch
*batch
);
66 num_fences(struct iris_batch
*batch
)
68 return util_dynarray_num_elements(&batch
->exec_fences
,
69 struct drm_i915_gem_exec_fence
);
73 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
76 dump_fence_list(struct iris_batch
*batch
)
78 fprintf(stderr
, "Fence list (length %u): ", num_fences(batch
));
80 util_dynarray_foreach(&batch
->exec_fences
,
81 struct drm_i915_gem_exec_fence
, f
) {
82 fprintf(stderr
, "%s%u%s ",
83 (f
->flags
& I915_EXEC_FENCE_WAIT
) ? "..." : "",
85 (f
->flags
& I915_EXEC_FENCE_SIGNAL
) ? "!" : "");
88 fprintf(stderr
, "\n");
92 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
95 dump_validation_list(struct iris_batch
*batch
)
97 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
99 for (int i
= 0; i
< batch
->exec_count
; i
++) {
100 uint64_t flags
= batch
->validation_list
[i
].flags
;
101 assert(batch
->validation_list
[i
].handle
==
102 batch
->exec_bos
[i
]->gem_handle
);
103 fprintf(stderr
, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64
"B)\t %2d refs %s\n",
105 batch
->validation_list
[i
].handle
,
106 batch
->exec_bos
[i
]->name
,
107 batch
->validation_list
[i
].offset
,
108 batch
->exec_bos
[i
]->size
,
109 batch
->exec_bos
[i
]->refcount
,
110 (flags
& EXEC_OBJECT_WRITE
) ? " (write)" : "");
115 * Return BO information to the batch decoder (for debugging).
117 static struct gen_batch_decode_bo
118 decode_get_bo(void *v_batch
, bool ppgtt
, uint64_t address
)
120 struct iris_batch
*batch
= v_batch
;
124 for (int i
= 0; i
< batch
->exec_count
; i
++) {
125 struct iris_bo
*bo
= batch
->exec_bos
[i
];
126 /* The decoder zeroes out the top 16 bits, so we need to as well */
127 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
129 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
130 return (struct gen_batch_decode_bo
) {
133 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
134 (address
- bo_address
),
139 return (struct gen_batch_decode_bo
) { };
143 * Decode the current batch.
146 decode_batch(struct iris_batch
*batch
)
148 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
149 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
150 batch
->exec_bos
[0]->gtt_offset
, false);
154 iris_init_batch(struct iris_batch
*batch
,
155 struct iris_screen
*screen
,
156 struct iris_vtable
*vtbl
,
157 struct pipe_debug_callback
*dbg
,
158 struct iris_batch
*all_batches
,
159 enum iris_batch_name name
,
163 batch
->screen
= screen
;
168 /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
169 assert((engine
& ~I915_EXEC_RING_MASK
) == 0);
170 assert(util_bitcount(engine
) == 1);
171 batch
->engine
= engine
;
173 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
174 assert(batch
->hw_ctx_id
);
176 iris_hw_context_set_priority(screen
->bufmgr
, batch
->hw_ctx_id
, priority
);
178 util_dynarray_init(&batch
->exec_fences
, ralloc_context(NULL
));
179 util_dynarray_init(&batch
->syncpts
, ralloc_context(NULL
));
181 batch
->exec_count
= 0;
182 batch
->exec_array_size
= 100;
184 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
185 batch
->validation_list
=
186 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
188 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
189 _mesa_key_pointer_equal
);
190 batch
->cache
.depth
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
191 _mesa_key_pointer_equal
);
193 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
195 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
196 if (&all_batches
[i
] != batch
)
197 batch
->other_batches
[j
++] = &all_batches
[i
];
200 if (unlikely(INTEL_DEBUG
)) {
201 const unsigned decode_flags
=
202 GEN_BATCH_DECODE_FULL
|
203 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
204 GEN_BATCH_DECODE_OFFSETS
|
205 GEN_BATCH_DECODE_FLOATS
;
207 /* TODO: track state size so we can print the right # of entries */
208 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
209 stderr
, decode_flags
, NULL
,
210 decode_get_bo
, NULL
, batch
);
211 batch
->decoder
.max_vbo_decoded_lines
= 32;
214 iris_batch_reset(batch
);
217 static struct drm_i915_gem_exec_object2
*
218 find_validation_entry(struct iris_batch
*batch
, struct iris_bo
*bo
)
220 unsigned index
= READ_ONCE(bo
->index
);
222 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
223 return &batch
->validation_list
[index
];
225 /* May have been shared between multiple active batches */
226 for (index
= 0; index
< batch
->exec_count
; index
++) {
227 if (batch
->exec_bos
[index
] == bo
)
228 return &batch
->validation_list
[index
];
235 * Add a buffer to the current batch's validation list.
237 * You must call this on any BO you wish to use in this batch, to ensure
238 * that it's resident when the GPU commands execute.
241 iris_use_pinned_bo(struct iris_batch
*batch
,
245 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
247 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
248 * about the order of any writes to that buffer, and marking it writable
249 * would introduce data dependencies between multiple batches which share
252 if (bo
== batch
->screen
->workaround_bo
)
255 struct drm_i915_gem_exec_object2
*existing_entry
=
256 find_validation_entry(batch
, bo
);
258 if (existing_entry
) {
259 /* The BO is already in the validation list; mark it writable */
261 existing_entry
->flags
|= EXEC_OBJECT_WRITE
;
266 if (bo
!= batch
->bo
) {
267 /* This is the first time our batch has seen this BO. Before we use it,
268 * we may need to flush and synchronize with other batches.
270 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
271 struct drm_i915_gem_exec_object2
*other_entry
=
272 find_validation_entry(batch
->other_batches
[b
], bo
);
274 /* If the buffer is referenced by another batch, and either batch
275 * intends to write it, then flush the other batch and synchronize.
277 * Consider these cases:
279 * 1. They read, we read => No synchronization required.
280 * 2. They read, we write => Synchronize (they need the old value)
281 * 3. They write, we read => Synchronize (we need their new value)
282 * 4. They write, we write => Synchronize (order writes)
284 * The read/read case is very common, as multiple batches usually
285 * share a streaming state buffer or shader assembly buffer, and
286 * we want to avoid synchronizing in this case.
289 ((other_entry
->flags
& EXEC_OBJECT_WRITE
) || writable
)) {
290 iris_batch_flush(batch
->other_batches
[b
]);
291 iris_batch_add_syncpt(batch
, batch
->other_batches
[b
]->last_syncpt
,
292 I915_EXEC_FENCE_WAIT
);
297 /* Now, take a reference and add it to the validation list. */
298 iris_bo_reference(bo
);
300 if (batch
->exec_count
== batch
->exec_array_size
) {
301 batch
->exec_array_size
*= 2;
303 realloc(batch
->exec_bos
,
304 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
305 batch
->validation_list
=
306 realloc(batch
->validation_list
,
307 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
310 batch
->validation_list
[batch
->exec_count
] =
311 (struct drm_i915_gem_exec_object2
) {
312 .handle
= bo
->gem_handle
,
313 .offset
= bo
->gtt_offset
,
314 .flags
= bo
->kflags
| (writable
? EXEC_OBJECT_WRITE
: 0),
317 bo
->index
= batch
->exec_count
;
318 batch
->exec_bos
[batch
->exec_count
] = bo
;
319 batch
->aperture_space
+= bo
->size
;
325 create_batch(struct iris_batch
*batch
)
327 struct iris_screen
*screen
= batch
->screen
;
328 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
330 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
331 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
332 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
333 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
334 batch
->map_next
= batch
->map
;
336 iris_use_pinned_bo(batch
, batch
->bo
, false);
340 iris_batch_reset(struct iris_batch
*batch
)
342 struct iris_screen
*screen
= batch
->screen
;
344 iris_bo_unreference(batch
->bo
);
345 batch
->primary_batch_size
= 0;
346 batch
->contains_draw
= false;
349 assert(batch
->bo
->index
== 0);
351 struct iris_syncpt
*syncpt
= iris_create_syncpt(screen
);
352 iris_batch_add_syncpt(batch
, syncpt
, I915_EXEC_FENCE_SIGNAL
);
353 iris_syncpt_reference(screen
, &syncpt
, NULL
);
355 iris_cache_sets_clear(batch
);
359 iris_batch_free(struct iris_batch
*batch
)
361 struct iris_screen
*screen
= batch
->screen
;
362 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
364 for (int i
= 0; i
< batch
->exec_count
; i
++) {
365 iris_bo_unreference(batch
->exec_bos
[i
]);
367 free(batch
->exec_bos
);
368 free(batch
->validation_list
);
370 ralloc_free(batch
->exec_fences
.mem_ctx
);
372 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
373 iris_syncpt_reference(screen
, s
, NULL
);
374 ralloc_free(batch
->syncpts
.mem_ctx
);
376 iris_syncpt_reference(screen
, &batch
->last_syncpt
, NULL
);
378 iris_bo_unreference(batch
->bo
);
381 batch
->map_next
= NULL
;
383 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
385 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
386 _mesa_set_destroy(batch
->cache
.depth
, NULL
);
388 if (unlikely(INTEL_DEBUG
))
389 gen_batch_decode_ctx_finish(&batch
->decoder
);
393 * If we've chained to a secondary batch, or are getting near to the end,
394 * then flush. This should only be called between draws.
397 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
399 if (batch
->bo
!= batch
->exec_bos
[0] ||
400 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
401 iris_batch_flush(batch
);
406 iris_chain_to_new_batch(struct iris_batch
*batch
)
408 /* We only support chaining a single time. */
409 assert(batch
->bo
== batch
->exec_bos
[0]);
411 uint32_t *cmd
= batch
->map_next
;
412 uint64_t *addr
= batch
->map_next
+ 4;
413 batch
->map_next
+= 12;
415 /* No longer held by batch->bo, still held by validation list */
416 iris_bo_unreference(batch
->bo
);
417 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
420 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
421 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
422 *addr
= batch
->bo
->gtt_offset
;
426 * Terminate a batch with MI_BATCH_BUFFER_END.
429 iris_finish_batch(struct iris_batch
*batch
)
431 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
432 uint32_t *map
= batch
->map_next
;
434 map
[0] = (0xA << 23);
436 batch
->map_next
+= 4;
438 if (batch
->bo
== batch
->exec_bos
[0])
439 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
443 * Submit the batch to the GPU via execbuffer2.
446 submit_batch(struct iris_batch
*batch
)
448 iris_bo_unmap(batch
->bo
);
450 /* The requirement for using I915_EXEC_NO_RELOC are:
452 * The addresses written in the objects must match the corresponding
453 * reloc.gtt_offset which in turn must match the corresponding
456 * Any render targets written to in the batch must be flagged with
459 * To avoid stalling, execobject.offset should match the current
460 * address of that object within the active context.
462 struct drm_i915_gem_execbuffer2 execbuf
= {
463 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
464 .buffer_count
= batch
->exec_count
,
465 .batch_start_offset
= 0,
466 /* This must be QWord aligned. */
467 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
468 .flags
= batch
->engine
|
470 I915_EXEC_BATCH_FIRST
|
471 I915_EXEC_HANDLE_LUT
,
472 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
475 if (num_fences(batch
)) {
476 execbuf
.flags
|= I915_EXEC_FENCE_ARRAY
;
477 execbuf
.num_cliprects
= num_fences(batch
);
478 execbuf
.cliprects_ptr
=
479 (uintptr_t)util_dynarray_begin(&batch
->exec_fences
);
482 int ret
= drm_ioctl(batch
->screen
->fd
,
483 DRM_IOCTL_I915_GEM_EXECBUFFER2
,
487 DBG("execbuf FAILED: errno = %d\n", -ret
);
488 fprintf(stderr
, "execbuf FAILED: errno = %d\n", -ret
);
491 DBG("execbuf succeeded\n");
494 for (int i
= 0; i
< batch
->exec_count
; i
++) {
495 struct iris_bo
*bo
= batch
->exec_bos
[i
];
500 iris_bo_unreference(bo
);
507 batch_name_to_string(enum iris_batch_name name
)
509 const char *names
[IRIS_BATCH_COUNT
] = {
510 [IRIS_BATCH_RENDER
] = "render",
511 [IRIS_BATCH_COMPUTE
] = "compute",
517 * Flush the batch buffer, submitting it to the GPU and resetting it so
518 * we're ready to emit the next batch.
520 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
521 * ownership of the fd.
523 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
524 * take ownership of the returned fd.
527 _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
)
529 struct iris_screen
*screen
= batch
->screen
;
531 if (iris_batch_bytes_used(batch
) == 0)
534 iris_finish_batch(batch
);
536 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
537 int bytes_for_commands
= iris_batch_bytes_used(batch
);
538 int second_bytes
= 0;
539 if (batch
->bo
!= batch
->exec_bos
[0]) {
540 second_bytes
= bytes_for_commands
;
541 bytes_for_commands
+= batch
->primary_batch_size
;
543 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) "
544 "(cmds), %4d BOs (%0.1fMb aperture)\n",
545 file
, line
, batch_name_to_string(batch
->name
), batch
->hw_ctx_id
,
546 batch
->primary_batch_size
, second_bytes
,
547 100.0f
* bytes_for_commands
/ BATCH_SZ
,
549 (float) batch
->aperture_space
/ (1024 * 1024));
550 dump_fence_list(batch
);
551 dump_validation_list(batch
);
554 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
558 int ret
= submit_batch(batch
);
561 //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
562 //iris_check_for_reset(ice);
564 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
565 dbg_printf("waiting for idle\n");
566 iris_bo_wait_rendering(batch
->bo
);
570 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
571 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
572 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
577 batch
->exec_count
= 0;
578 batch
->aperture_space
= 0;
580 struct iris_syncpt
*syncpt
=
581 ((struct iris_syncpt
**) util_dynarray_begin(&batch
->syncpts
))[0];
582 iris_syncpt_reference(screen
, &batch
->last_syncpt
, syncpt
);
584 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
585 iris_syncpt_reference(screen
, s
, NULL
);
586 util_dynarray_clear(&batch
->syncpts
);
588 util_dynarray_clear(&batch
->exec_fences
);
590 /* Start a new batch buffer. */
591 iris_batch_reset(batch
);
595 * Does the current batch refer to the given BO?
597 * (In other words, is the BO in the current batch's validation list?)
600 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
602 return find_validation_entry(batch
, bo
) != NULL
;