2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
45 #include "drm-uapi/i915_drm.h"
47 #include "common/gen_aux_map.h"
48 #include "intel/common/gen_gem.h"
49 #include "util/hash_table.h"
51 #include "main/macros.h"
64 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
66 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
67 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
68 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
70 #define BATCH_RESERVED 16
73 iris_batch_reset(struct iris_batch
*batch
);
76 num_fences(struct iris_batch
*batch
)
78 return util_dynarray_num_elements(&batch
->exec_fences
,
79 struct drm_i915_gem_exec_fence
);
83 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
86 dump_fence_list(struct iris_batch
*batch
)
88 fprintf(stderr
, "Fence list (length %u): ", num_fences(batch
));
90 util_dynarray_foreach(&batch
->exec_fences
,
91 struct drm_i915_gem_exec_fence
, f
) {
92 fprintf(stderr
, "%s%u%s ",
93 (f
->flags
& I915_EXEC_FENCE_WAIT
) ? "..." : "",
95 (f
->flags
& I915_EXEC_FENCE_SIGNAL
) ? "!" : "");
98 fprintf(stderr
, "\n");
102 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
105 dump_validation_list(struct iris_batch
*batch
)
107 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
109 for (int i
= 0; i
< batch
->exec_count
; i
++) {
110 uint64_t flags
= batch
->validation_list
[i
].flags
;
111 assert(batch
->validation_list
[i
].handle
==
112 batch
->exec_bos
[i
]->gem_handle
);
113 fprintf(stderr
, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64
"B)\t %2d refs %s\n",
115 batch
->validation_list
[i
].handle
,
116 batch
->exec_bos
[i
]->name
,
117 batch
->validation_list
[i
].offset
,
118 batch
->exec_bos
[i
]->size
,
119 batch
->exec_bos
[i
]->refcount
,
120 (flags
& EXEC_OBJECT_WRITE
) ? " (write)" : "");
125 * Return BO information to the batch decoder (for debugging).
127 static struct gen_batch_decode_bo
128 decode_get_bo(void *v_batch
, bool ppgtt
, uint64_t address
)
130 struct iris_batch
*batch
= v_batch
;
134 for (int i
= 0; i
< batch
->exec_count
; i
++) {
135 struct iris_bo
*bo
= batch
->exec_bos
[i
];
136 /* The decoder zeroes out the top 16 bits, so we need to as well */
137 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
139 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
140 return (struct gen_batch_decode_bo
) {
143 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
144 (address
- bo_address
),
149 return (struct gen_batch_decode_bo
) { };
153 decode_get_state_size(void *v_batch
,
155 UNUSED
uint64_t base_address
)
157 struct iris_batch
*batch
= v_batch
;
158 unsigned size
= (uintptr_t)
159 _mesa_hash_table_u64_search(batch
->state_sizes
, address
);
165 * Decode the current batch.
168 decode_batch(struct iris_batch
*batch
)
170 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
171 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
172 batch
->exec_bos
[0]->gtt_offset
, false);
176 iris_init_batch(struct iris_batch
*batch
,
177 struct iris_screen
*screen
,
178 struct iris_vtable
*vtbl
,
179 struct pipe_debug_callback
*dbg
,
180 struct pipe_device_reset_callback
*reset
,
181 struct hash_table_u64
*state_sizes
,
182 struct iris_batch
*all_batches
,
183 enum iris_batch_name name
,
186 batch
->screen
= screen
;
189 batch
->reset
= reset
;
190 batch
->state_sizes
= state_sizes
;
193 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
194 assert(batch
->hw_ctx_id
);
196 iris_hw_context_set_priority(screen
->bufmgr
, batch
->hw_ctx_id
, priority
);
198 util_dynarray_init(&batch
->exec_fences
, ralloc_context(NULL
));
199 util_dynarray_init(&batch
->syncpts
, ralloc_context(NULL
));
201 batch
->exec_count
= 0;
202 batch
->exec_array_size
= 100;
204 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
205 batch
->validation_list
=
206 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
208 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
209 _mesa_key_pointer_equal
);
210 batch
->cache
.depth
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
211 _mesa_key_pointer_equal
);
213 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
215 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
216 if (&all_batches
[i
] != batch
)
217 batch
->other_batches
[j
++] = &all_batches
[i
];
220 if (unlikely(INTEL_DEBUG
)) {
221 const unsigned decode_flags
=
222 GEN_BATCH_DECODE_FULL
|
223 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
224 GEN_BATCH_DECODE_OFFSETS
|
225 GEN_BATCH_DECODE_FLOATS
;
227 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
228 stderr
, decode_flags
, NULL
,
229 decode_get_bo
, decode_get_state_size
, batch
);
230 batch
->decoder
.dynamic_base
= IRIS_MEMZONE_DYNAMIC_START
;
231 batch
->decoder
.instruction_base
= IRIS_MEMZONE_SHADER_START
;
232 batch
->decoder
.max_vbo_decoded_lines
= 32;
235 iris_batch_reset(batch
);
238 static struct drm_i915_gem_exec_object2
*
239 find_validation_entry(struct iris_batch
*batch
, struct iris_bo
*bo
)
241 unsigned index
= READ_ONCE(bo
->index
);
243 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
244 return &batch
->validation_list
[index
];
246 /* May have been shared between multiple active batches */
247 for (index
= 0; index
< batch
->exec_count
; index
++) {
248 if (batch
->exec_bos
[index
] == bo
)
249 return &batch
->validation_list
[index
];
256 ensure_exec_obj_space(struct iris_batch
*batch
, uint32_t count
)
258 while (batch
->exec_count
+ count
> batch
->exec_array_size
) {
259 batch
->exec_array_size
*= 2;
261 realloc(batch
->exec_bos
,
262 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
263 batch
->validation_list
=
264 realloc(batch
->validation_list
,
265 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
270 * Add a buffer to the current batch's validation list.
272 * You must call this on any BO you wish to use in this batch, to ensure
273 * that it's resident when the GPU commands execute.
276 iris_use_pinned_bo(struct iris_batch
*batch
,
280 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
282 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
283 * about the order of any writes to that buffer, and marking it writable
284 * would introduce data dependencies between multiple batches which share
287 if (bo
== batch
->screen
->workaround_bo
)
290 struct drm_i915_gem_exec_object2
*existing_entry
=
291 find_validation_entry(batch
, bo
);
293 if (existing_entry
) {
294 /* The BO is already in the validation list; mark it writable */
296 existing_entry
->flags
|= EXEC_OBJECT_WRITE
;
301 if (bo
!= batch
->bo
) {
302 /* This is the first time our batch has seen this BO. Before we use it,
303 * we may need to flush and synchronize with other batches.
305 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
306 struct drm_i915_gem_exec_object2
*other_entry
=
307 find_validation_entry(batch
->other_batches
[b
], bo
);
309 /* If the buffer is referenced by another batch, and either batch
310 * intends to write it, then flush the other batch and synchronize.
312 * Consider these cases:
314 * 1. They read, we read => No synchronization required.
315 * 2. They read, we write => Synchronize (they need the old value)
316 * 3. They write, we read => Synchronize (we need their new value)
317 * 4. They write, we write => Synchronize (order writes)
319 * The read/read case is very common, as multiple batches usually
320 * share a streaming state buffer or shader assembly buffer, and
321 * we want to avoid synchronizing in this case.
324 ((other_entry
->flags
& EXEC_OBJECT_WRITE
) || writable
)) {
325 iris_batch_flush(batch
->other_batches
[b
]);
326 iris_batch_add_syncpt(batch
, batch
->other_batches
[b
]->last_syncpt
,
327 I915_EXEC_FENCE_WAIT
);
332 /* Now, take a reference and add it to the validation list. */
333 iris_bo_reference(bo
);
335 ensure_exec_obj_space(batch
, 1);
337 batch
->validation_list
[batch
->exec_count
] =
338 (struct drm_i915_gem_exec_object2
) {
339 .handle
= bo
->gem_handle
,
340 .offset
= bo
->gtt_offset
,
341 .flags
= bo
->kflags
| (writable
? EXEC_OBJECT_WRITE
: 0),
344 bo
->index
= batch
->exec_count
;
345 batch
->exec_bos
[batch
->exec_count
] = bo
;
346 batch
->aperture_space
+= bo
->size
;
352 create_batch(struct iris_batch
*batch
)
354 struct iris_screen
*screen
= batch
->screen
;
355 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
357 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
358 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
359 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
360 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
361 batch
->map_next
= batch
->map
;
363 iris_use_pinned_bo(batch
, batch
->bo
, false);
367 iris_batch_maybe_noop(struct iris_batch
*batch
)
369 /* We only insert the NOOP at the beginning of the batch. */
370 assert(iris_batch_bytes_used(batch
) == 0);
372 if (batch
->noop_enabled
) {
373 /* Emit MI_BATCH_BUFFER_END to prevent any further command to be
376 uint32_t *map
= batch
->map_next
;
378 map
[0] = (0xA << 23);
380 batch
->map_next
+= 4;
385 iris_batch_reset(struct iris_batch
*batch
)
387 struct iris_screen
*screen
= batch
->screen
;
389 iris_bo_unreference(batch
->bo
);
390 batch
->primary_batch_size
= 0;
391 batch
->total_chained_batch_size
= 0;
392 batch
->contains_draw
= false;
393 batch
->decoder
.surface_base
= batch
->last_surface_base_address
;
396 assert(batch
->bo
->index
== 0);
398 struct iris_syncpt
*syncpt
= iris_create_syncpt(screen
);
399 iris_batch_add_syncpt(batch
, syncpt
, I915_EXEC_FENCE_SIGNAL
);
400 iris_syncpt_reference(screen
, &syncpt
, NULL
);
402 iris_cache_sets_clear(batch
);
404 iris_batch_maybe_noop(batch
);
408 iris_batch_free(struct iris_batch
*batch
)
410 struct iris_screen
*screen
= batch
->screen
;
411 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
413 for (int i
= 0; i
< batch
->exec_count
; i
++) {
414 iris_bo_unreference(batch
->exec_bos
[i
]);
416 free(batch
->exec_bos
);
417 free(batch
->validation_list
);
419 ralloc_free(batch
->exec_fences
.mem_ctx
);
421 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
422 iris_syncpt_reference(screen
, s
, NULL
);
423 ralloc_free(batch
->syncpts
.mem_ctx
);
425 iris_syncpt_reference(screen
, &batch
->last_syncpt
, NULL
);
427 iris_bo_unreference(batch
->bo
);
430 batch
->map_next
= NULL
;
432 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
434 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
435 _mesa_set_destroy(batch
->cache
.depth
, NULL
);
437 if (unlikely(INTEL_DEBUG
))
438 gen_batch_decode_ctx_finish(&batch
->decoder
);
442 * If we've chained to a secondary batch, or are getting near to the end,
443 * then flush. This should only be called between draws.
446 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
448 if (batch
->bo
!= batch
->exec_bos
[0] ||
449 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
450 iris_batch_flush(batch
);
455 record_batch_sizes(struct iris_batch
*batch
)
457 unsigned batch_size
= iris_batch_bytes_used(batch
);
459 VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch
->map
, batch_size
));
461 if (batch
->bo
== batch
->exec_bos
[0])
462 batch
->primary_batch_size
= batch_size
;
464 batch
->total_chained_batch_size
+= batch_size
;
468 iris_chain_to_new_batch(struct iris_batch
*batch
)
470 uint32_t *cmd
= batch
->map_next
;
471 uint64_t *addr
= batch
->map_next
+ 4;
472 batch
->map_next
+= 12;
474 record_batch_sizes(batch
);
476 /* No longer held by batch->bo, still held by validation list */
477 iris_bo_unreference(batch
->bo
);
480 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
481 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
482 *addr
= batch
->bo
->gtt_offset
;
486 add_aux_map_bos_to_batch(struct iris_batch
*batch
)
488 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(batch
->screen
->bufmgr
);
492 uint32_t count
= gen_aux_map_get_num_buffers(aux_map_ctx
);
493 ensure_exec_obj_space(batch
, count
);
494 gen_aux_map_fill_bos(aux_map_ctx
,
495 (void**)&batch
->exec_bos
[batch
->exec_count
], count
);
496 for (uint32_t i
= 0; i
< count
; i
++) {
497 struct iris_bo
*bo
= batch
->exec_bos
[batch
->exec_count
];
498 iris_bo_reference(bo
);
499 batch
->validation_list
[batch
->exec_count
] =
500 (struct drm_i915_gem_exec_object2
) {
501 .handle
= bo
->gem_handle
,
502 .offset
= bo
->gtt_offset
,
505 batch
->aperture_space
+= bo
->size
;
511 * Terminate a batch with MI_BATCH_BUFFER_END.
514 iris_finish_batch(struct iris_batch
*batch
)
516 add_aux_map_bos_to_batch(batch
);
518 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
519 uint32_t *map
= batch
->map_next
;
521 map
[0] = (0xA << 23);
523 batch
->map_next
+= 4;
525 record_batch_sizes(batch
);
529 * Replace our current GEM context with a new one (in case it got banned).
532 replace_hw_ctx(struct iris_batch
*batch
)
534 struct iris_screen
*screen
= batch
->screen
;
535 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
537 uint32_t new_ctx
= iris_clone_hw_context(bufmgr
, batch
->hw_ctx_id
);
541 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
542 batch
->hw_ctx_id
= new_ctx
;
544 /* Notify the context that state must be re-initialized. */
545 iris_lost_context_state(batch
);
550 enum pipe_reset_status
551 iris_batch_check_for_reset(struct iris_batch
*batch
)
553 struct iris_screen
*screen
= batch
->screen
;
554 enum pipe_reset_status status
= PIPE_NO_RESET
;
555 struct drm_i915_reset_stats stats
= { .ctx_id
= batch
->hw_ctx_id
};
557 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
))
558 DBG("DRM_IOCTL_I915_GET_RESET_STATS failed: %s\n", strerror(errno
));
560 if (stats
.batch_active
!= 0) {
561 /* A reset was observed while a batch from this hardware context was
562 * executing. Assume that this context was at fault.
564 status
= PIPE_GUILTY_CONTEXT_RESET
;
565 } else if (stats
.batch_pending
!= 0) {
566 /* A reset was observed while a batch from this context was in progress,
567 * but the batch was not executing. In this case, assume that the
568 * context was not at fault.
570 status
= PIPE_INNOCENT_CONTEXT_RESET
;
573 if (status
!= PIPE_NO_RESET
) {
574 /* Our context is likely banned, or at least in an unknown state.
575 * Throw it away and start with a fresh context. Ideally this may
576 * catch the problem before our next execbuf fails with -EIO.
578 replace_hw_ctx(batch
);
585 * Submit the batch to the GPU via execbuffer2.
588 submit_batch(struct iris_batch
*batch
)
590 iris_bo_unmap(batch
->bo
);
592 /* The requirement for using I915_EXEC_NO_RELOC are:
594 * The addresses written in the objects must match the corresponding
595 * reloc.gtt_offset which in turn must match the corresponding
598 * Any render targets written to in the batch must be flagged with
601 * To avoid stalling, execobject.offset should match the current
602 * address of that object within the active context.
604 struct drm_i915_gem_execbuffer2 execbuf
= {
605 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
606 .buffer_count
= batch
->exec_count
,
607 .batch_start_offset
= 0,
608 /* This must be QWord aligned. */
609 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
610 .flags
= I915_EXEC_RENDER
|
612 I915_EXEC_BATCH_FIRST
|
613 I915_EXEC_HANDLE_LUT
,
614 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
617 if (num_fences(batch
)) {
618 execbuf
.flags
|= I915_EXEC_FENCE_ARRAY
;
619 execbuf
.num_cliprects
= num_fences(batch
);
620 execbuf
.cliprects_ptr
=
621 (uintptr_t)util_dynarray_begin(&batch
->exec_fences
);
625 if (!batch
->screen
->no_hw
&&
626 gen_ioctl(batch
->screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
))
629 for (int i
= 0; i
< batch
->exec_count
; i
++) {
630 struct iris_bo
*bo
= batch
->exec_bos
[i
];
635 iris_bo_unreference(bo
);
642 batch_name_to_string(enum iris_batch_name name
)
644 const char *names
[IRIS_BATCH_COUNT
] = {
645 [IRIS_BATCH_RENDER
] = "render",
646 [IRIS_BATCH_COMPUTE
] = "compute",
652 * Flush the batch buffer, submitting it to the GPU and resetting it so
653 * we're ready to emit the next batch.
655 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
656 * ownership of the fd.
658 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
659 * take ownership of the returned fd.
662 _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
)
664 struct iris_screen
*screen
= batch
->screen
;
666 if (iris_batch_bytes_used(batch
) == 0)
669 iris_finish_batch(batch
);
671 if (unlikely(INTEL_DEBUG
&
672 (DEBUG_BATCH
| DEBUG_SUBMIT
| DEBUG_PIPE_CONTROL
))) {
673 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
674 "(cmds), %4d BOs (%0.1fMb aperture)\n",
675 file
, line
, batch_name_to_string(batch
->name
), batch
->hw_ctx_id
,
676 batch
->total_chained_batch_size
,
677 100.0f
* batch
->total_chained_batch_size
/ BATCH_SZ
,
679 (float) batch
->aperture_space
/ (1024 * 1024));
681 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
682 dump_fence_list(batch
);
683 dump_validation_list(batch
);
686 if (INTEL_DEBUG
& DEBUG_BATCH
) {
691 int ret
= submit_batch(batch
);
693 batch
->exec_count
= 0;
694 batch
->aperture_space
= 0;
696 struct iris_syncpt
*syncpt
=
697 ((struct iris_syncpt
**) util_dynarray_begin(&batch
->syncpts
))[0];
698 iris_syncpt_reference(screen
, &batch
->last_syncpt
, syncpt
);
700 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
701 iris_syncpt_reference(screen
, s
, NULL
);
702 util_dynarray_clear(&batch
->syncpts
);
704 util_dynarray_clear(&batch
->exec_fences
);
706 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
707 dbg_printf("waiting for idle\n");
708 iris_bo_wait_rendering(batch
->bo
); /* if execbuf failed; this is a nop */
711 /* Start a new batch buffer. */
712 iris_batch_reset(batch
);
714 /* EIO means our context is banned. In this case, try and replace it
715 * with a new logical context, and inform iris_context that all state
716 * has been lost and needs to be re-initialized. If this succeeds,
717 * dubiously claim success...
719 if (ret
== -EIO
&& replace_hw_ctx(batch
)) {
720 if (batch
->reset
->reset
) {
721 /* Tell the state tracker the device is lost and it was our fault. */
722 batch
->reset
->reset(batch
->reset
->data
, PIPE_GUILTY_CONTEXT_RESET
);
730 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
731 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
732 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
739 * Does the current batch refer to the given BO?
741 * (In other words, is the BO in the current batch's validation list?)
744 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
746 return find_validation_entry(batch
, bo
) != NULL
;
750 * Updates the state of the noop feature.
753 iris_batch_prepare_noop(struct iris_batch
*batch
, bool noop_enable
, uint64_t dirty_flags
)
755 if (batch
->noop_enabled
== noop_enable
)
758 batch
->noop_enabled
= noop_enable
;
760 iris_batch_flush(batch
);
762 /* If the batch was empty, flush had no effect, so insert our noop. */
763 if (iris_batch_bytes_used(batch
) == 0)
764 iris_batch_maybe_noop(batch
);
766 /* We only need to update the entire state if we transition from noop ->
769 return !batch
->noop_enabled
? dirty_flags
: 0;