2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
45 #include "drm-uapi/i915_drm.h"
47 #include "common/gen_aux_map.h"
48 #include "intel/common/gen_gem.h"
49 #include "util/hash_table.h"
51 #include "main/macros.h"
64 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
67 iris_batch_reset(struct iris_batch
*batch
);
70 num_fences(struct iris_batch
*batch
)
72 return util_dynarray_num_elements(&batch
->exec_fences
,
73 struct drm_i915_gem_exec_fence
);
77 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
80 dump_fence_list(struct iris_batch
*batch
)
82 fprintf(stderr
, "Fence list (length %u): ", num_fences(batch
));
84 util_dynarray_foreach(&batch
->exec_fences
,
85 struct drm_i915_gem_exec_fence
, f
) {
86 fprintf(stderr
, "%s%u%s ",
87 (f
->flags
& I915_EXEC_FENCE_WAIT
) ? "..." : "",
89 (f
->flags
& I915_EXEC_FENCE_SIGNAL
) ? "!" : "");
92 fprintf(stderr
, "\n");
96 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
99 dump_validation_list(struct iris_batch
*batch
)
101 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
103 for (int i
= 0; i
< batch
->exec_count
; i
++) {
104 uint64_t flags
= batch
->validation_list
[i
].flags
;
105 assert(batch
->validation_list
[i
].handle
==
106 batch
->exec_bos
[i
]->gem_handle
);
107 fprintf(stderr
, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64
"B)\t %2d refs %s\n",
109 batch
->validation_list
[i
].handle
,
110 batch
->exec_bos
[i
]->name
,
111 batch
->validation_list
[i
].offset
,
112 batch
->exec_bos
[i
]->size
,
113 batch
->exec_bos
[i
]->refcount
,
114 (flags
& EXEC_OBJECT_WRITE
) ? " (write)" : "");
119 * Return BO information to the batch decoder (for debugging).
121 static struct gen_batch_decode_bo
122 decode_get_bo(void *v_batch
, bool ppgtt
, uint64_t address
)
124 struct iris_batch
*batch
= v_batch
;
128 for (int i
= 0; i
< batch
->exec_count
; i
++) {
129 struct iris_bo
*bo
= batch
->exec_bos
[i
];
130 /* The decoder zeroes out the top 16 bits, so we need to as well */
131 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
133 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
134 return (struct gen_batch_decode_bo
) {
137 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
138 (address
- bo_address
),
143 return (struct gen_batch_decode_bo
) { };
147 decode_get_state_size(void *v_batch
,
149 UNUSED
uint64_t base_address
)
151 struct iris_batch
*batch
= v_batch
;
152 unsigned size
= (uintptr_t)
153 _mesa_hash_table_u64_search(batch
->state_sizes
, address
);
159 * Decode the current batch.
162 decode_batch(struct iris_batch
*batch
)
164 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
165 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
166 batch
->exec_bos
[0]->gtt_offset
, false);
170 iris_init_batch(struct iris_batch
*batch
,
171 struct iris_screen
*screen
,
172 struct iris_vtable
*vtbl
,
173 struct pipe_debug_callback
*dbg
,
174 struct pipe_device_reset_callback
*reset
,
175 struct hash_table_u64
*state_sizes
,
176 struct iris_batch
*all_batches
,
177 enum iris_batch_name name
,
180 batch
->screen
= screen
;
183 batch
->reset
= reset
;
184 batch
->state_sizes
= state_sizes
;
187 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
188 assert(batch
->hw_ctx_id
);
190 iris_hw_context_set_priority(screen
->bufmgr
, batch
->hw_ctx_id
, priority
);
192 util_dynarray_init(&batch
->exec_fences
, ralloc_context(NULL
));
193 util_dynarray_init(&batch
->syncpts
, ralloc_context(NULL
));
195 batch
->exec_count
= 0;
196 batch
->exec_array_size
= 100;
198 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
199 batch
->validation_list
=
200 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
202 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
203 _mesa_key_pointer_equal
);
204 batch
->cache
.depth
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
205 _mesa_key_pointer_equal
);
207 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
209 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
210 if (&all_batches
[i
] != batch
)
211 batch
->other_batches
[j
++] = &all_batches
[i
];
214 if (unlikely(INTEL_DEBUG
)) {
215 const unsigned decode_flags
=
216 GEN_BATCH_DECODE_FULL
|
217 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
218 GEN_BATCH_DECODE_OFFSETS
|
219 GEN_BATCH_DECODE_FLOATS
;
221 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
222 stderr
, decode_flags
, NULL
,
223 decode_get_bo
, decode_get_state_size
, batch
);
224 batch
->decoder
.dynamic_base
= IRIS_MEMZONE_DYNAMIC_START
;
225 batch
->decoder
.instruction_base
= IRIS_MEMZONE_SHADER_START
;
226 batch
->decoder
.max_vbo_decoded_lines
= 32;
229 iris_batch_reset(batch
);
232 static struct drm_i915_gem_exec_object2
*
233 find_validation_entry(struct iris_batch
*batch
, struct iris_bo
*bo
)
235 unsigned index
= READ_ONCE(bo
->index
);
237 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
238 return &batch
->validation_list
[index
];
240 /* May have been shared between multiple active batches */
241 for (index
= 0; index
< batch
->exec_count
; index
++) {
242 if (batch
->exec_bos
[index
] == bo
)
243 return &batch
->validation_list
[index
];
250 ensure_exec_obj_space(struct iris_batch
*batch
, uint32_t count
)
252 while (batch
->exec_count
+ count
> batch
->exec_array_size
) {
253 batch
->exec_array_size
*= 2;
255 realloc(batch
->exec_bos
,
256 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
257 batch
->validation_list
=
258 realloc(batch
->validation_list
,
259 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
264 * Add a buffer to the current batch's validation list.
266 * You must call this on any BO you wish to use in this batch, to ensure
267 * that it's resident when the GPU commands execute.
270 iris_use_pinned_bo(struct iris_batch
*batch
,
274 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
276 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
277 * about the order of any writes to that buffer, and marking it writable
278 * would introduce data dependencies between multiple batches which share
281 if (bo
== batch
->screen
->workaround_bo
)
284 struct drm_i915_gem_exec_object2
*existing_entry
=
285 find_validation_entry(batch
, bo
);
287 if (existing_entry
) {
288 /* The BO is already in the validation list; mark it writable */
290 existing_entry
->flags
|= EXEC_OBJECT_WRITE
;
295 if (bo
!= batch
->bo
) {
296 /* This is the first time our batch has seen this BO. Before we use it,
297 * we may need to flush and synchronize with other batches.
299 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
300 struct drm_i915_gem_exec_object2
*other_entry
=
301 find_validation_entry(batch
->other_batches
[b
], bo
);
303 /* If the buffer is referenced by another batch, and either batch
304 * intends to write it, then flush the other batch and synchronize.
306 * Consider these cases:
308 * 1. They read, we read => No synchronization required.
309 * 2. They read, we write => Synchronize (they need the old value)
310 * 3. They write, we read => Synchronize (we need their new value)
311 * 4. They write, we write => Synchronize (order writes)
313 * The read/read case is very common, as multiple batches usually
314 * share a streaming state buffer or shader assembly buffer, and
315 * we want to avoid synchronizing in this case.
318 ((other_entry
->flags
& EXEC_OBJECT_WRITE
) || writable
)) {
319 iris_batch_flush(batch
->other_batches
[b
]);
320 iris_batch_add_syncpt(batch
, batch
->other_batches
[b
]->last_syncpt
,
321 I915_EXEC_FENCE_WAIT
);
326 /* Now, take a reference and add it to the validation list. */
327 iris_bo_reference(bo
);
329 ensure_exec_obj_space(batch
, 1);
331 batch
->validation_list
[batch
->exec_count
] =
332 (struct drm_i915_gem_exec_object2
) {
333 .handle
= bo
->gem_handle
,
334 .offset
= bo
->gtt_offset
,
335 .flags
= bo
->kflags
| (writable
? EXEC_OBJECT_WRITE
: 0),
338 bo
->index
= batch
->exec_count
;
339 batch
->exec_bos
[batch
->exec_count
] = bo
;
340 batch
->aperture_space
+= bo
->size
;
346 create_batch(struct iris_batch
*batch
)
348 struct iris_screen
*screen
= batch
->screen
;
349 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
351 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
352 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
353 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
354 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
355 batch
->map_next
= batch
->map
;
357 iris_use_pinned_bo(batch
, batch
->bo
, false);
361 iris_batch_maybe_noop(struct iris_batch
*batch
)
363 /* We only insert the NOOP at the beginning of the batch. */
364 assert(iris_batch_bytes_used(batch
) == 0);
366 if (batch
->noop_enabled
) {
367 /* Emit MI_BATCH_BUFFER_END to prevent any further command to be
370 uint32_t *map
= batch
->map_next
;
372 map
[0] = (0xA << 23);
374 batch
->map_next
+= 4;
379 iris_batch_reset(struct iris_batch
*batch
)
381 struct iris_screen
*screen
= batch
->screen
;
383 iris_bo_unreference(batch
->bo
);
384 batch
->primary_batch_size
= 0;
385 batch
->total_chained_batch_size
= 0;
386 batch
->contains_draw
= false;
387 batch
->decoder
.surface_base
= batch
->last_surface_base_address
;
390 assert(batch
->bo
->index
== 0);
392 struct iris_syncpt
*syncpt
= iris_create_syncpt(screen
);
393 iris_batch_add_syncpt(batch
, syncpt
, I915_EXEC_FENCE_SIGNAL
);
394 iris_syncpt_reference(screen
, &syncpt
, NULL
);
396 iris_cache_sets_clear(batch
);
398 iris_batch_maybe_noop(batch
);
402 iris_batch_free(struct iris_batch
*batch
)
404 struct iris_screen
*screen
= batch
->screen
;
405 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
407 for (int i
= 0; i
< batch
->exec_count
; i
++) {
408 iris_bo_unreference(batch
->exec_bos
[i
]);
410 free(batch
->exec_bos
);
411 free(batch
->validation_list
);
413 ralloc_free(batch
->exec_fences
.mem_ctx
);
415 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
416 iris_syncpt_reference(screen
, s
, NULL
);
417 ralloc_free(batch
->syncpts
.mem_ctx
);
419 iris_syncpt_reference(screen
, &batch
->last_syncpt
, NULL
);
421 iris_bo_unreference(batch
->bo
);
424 batch
->map_next
= NULL
;
426 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
428 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
429 _mesa_set_destroy(batch
->cache
.depth
, NULL
);
431 if (unlikely(INTEL_DEBUG
))
432 gen_batch_decode_ctx_finish(&batch
->decoder
);
436 * If we've chained to a secondary batch, or are getting near to the end,
437 * then flush. This should only be called between draws.
440 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
442 if (batch
->bo
!= batch
->exec_bos
[0] ||
443 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
444 iris_batch_flush(batch
);
449 record_batch_sizes(struct iris_batch
*batch
)
451 unsigned batch_size
= iris_batch_bytes_used(batch
);
453 VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch
->map
, batch_size
));
455 if (batch
->bo
== batch
->exec_bos
[0])
456 batch
->primary_batch_size
= batch_size
;
458 batch
->total_chained_batch_size
+= batch_size
;
462 iris_chain_to_new_batch(struct iris_batch
*batch
)
464 uint32_t *cmd
= batch
->map_next
;
465 uint64_t *addr
= batch
->map_next
+ 4;
466 batch
->map_next
+= 12;
468 record_batch_sizes(batch
);
470 /* No longer held by batch->bo, still held by validation list */
471 iris_bo_unreference(batch
->bo
);
474 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
475 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
476 *addr
= batch
->bo
->gtt_offset
;
480 add_aux_map_bos_to_batch(struct iris_batch
*batch
)
482 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(batch
->screen
->bufmgr
);
486 uint32_t count
= gen_aux_map_get_num_buffers(aux_map_ctx
);
487 ensure_exec_obj_space(batch
, count
);
488 gen_aux_map_fill_bos(aux_map_ctx
,
489 (void**)&batch
->exec_bos
[batch
->exec_count
], count
);
490 for (uint32_t i
= 0; i
< count
; i
++) {
491 struct iris_bo
*bo
= batch
->exec_bos
[batch
->exec_count
];
492 iris_bo_reference(bo
);
493 batch
->validation_list
[batch
->exec_count
] =
494 (struct drm_i915_gem_exec_object2
) {
495 .handle
= bo
->gem_handle
,
496 .offset
= bo
->gtt_offset
,
499 batch
->aperture_space
+= bo
->size
;
505 * Terminate a batch with MI_BATCH_BUFFER_END.
508 iris_finish_batch(struct iris_batch
*batch
)
510 add_aux_map_bos_to_batch(batch
);
512 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
513 uint32_t *map
= batch
->map_next
;
515 map
[0] = (0xA << 23);
517 batch
->map_next
+= 4;
519 record_batch_sizes(batch
);
523 * Replace our current GEM context with a new one (in case it got banned).
526 replace_hw_ctx(struct iris_batch
*batch
)
528 struct iris_screen
*screen
= batch
->screen
;
529 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
531 uint32_t new_ctx
= iris_clone_hw_context(bufmgr
, batch
->hw_ctx_id
);
535 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
536 batch
->hw_ctx_id
= new_ctx
;
538 /* Notify the context that state must be re-initialized. */
539 iris_lost_context_state(batch
);
544 enum pipe_reset_status
545 iris_batch_check_for_reset(struct iris_batch
*batch
)
547 struct iris_screen
*screen
= batch
->screen
;
548 enum pipe_reset_status status
= PIPE_NO_RESET
;
549 struct drm_i915_reset_stats stats
= { .ctx_id
= batch
->hw_ctx_id
};
551 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
))
552 DBG("DRM_IOCTL_I915_GET_RESET_STATS failed: %s\n", strerror(errno
));
554 if (stats
.batch_active
!= 0) {
555 /* A reset was observed while a batch from this hardware context was
556 * executing. Assume that this context was at fault.
558 status
= PIPE_GUILTY_CONTEXT_RESET
;
559 } else if (stats
.batch_pending
!= 0) {
560 /* A reset was observed while a batch from this context was in progress,
561 * but the batch was not executing. In this case, assume that the
562 * context was not at fault.
564 status
= PIPE_INNOCENT_CONTEXT_RESET
;
567 if (status
!= PIPE_NO_RESET
) {
568 /* Our context is likely banned, or at least in an unknown state.
569 * Throw it away and start with a fresh context. Ideally this may
570 * catch the problem before our next execbuf fails with -EIO.
572 replace_hw_ctx(batch
);
579 * Submit the batch to the GPU via execbuffer2.
582 submit_batch(struct iris_batch
*batch
)
584 iris_bo_unmap(batch
->bo
);
586 /* The requirement for using I915_EXEC_NO_RELOC are:
588 * The addresses written in the objects must match the corresponding
589 * reloc.gtt_offset which in turn must match the corresponding
592 * Any render targets written to in the batch must be flagged with
595 * To avoid stalling, execobject.offset should match the current
596 * address of that object within the active context.
598 struct drm_i915_gem_execbuffer2 execbuf
= {
599 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
600 .buffer_count
= batch
->exec_count
,
601 .batch_start_offset
= 0,
602 /* This must be QWord aligned. */
603 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
604 .flags
= I915_EXEC_RENDER
|
606 I915_EXEC_BATCH_FIRST
|
607 I915_EXEC_HANDLE_LUT
,
608 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
611 if (num_fences(batch
)) {
612 execbuf
.flags
|= I915_EXEC_FENCE_ARRAY
;
613 execbuf
.num_cliprects
= num_fences(batch
);
614 execbuf
.cliprects_ptr
=
615 (uintptr_t)util_dynarray_begin(&batch
->exec_fences
);
619 if (!batch
->screen
->no_hw
&&
620 gen_ioctl(batch
->screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
))
623 for (int i
= 0; i
< batch
->exec_count
; i
++) {
624 struct iris_bo
*bo
= batch
->exec_bos
[i
];
629 iris_bo_unreference(bo
);
636 batch_name_to_string(enum iris_batch_name name
)
638 const char *names
[IRIS_BATCH_COUNT
] = {
639 [IRIS_BATCH_RENDER
] = "render",
640 [IRIS_BATCH_COMPUTE
] = "compute",
646 * Flush the batch buffer, submitting it to the GPU and resetting it so
647 * we're ready to emit the next batch.
649 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
650 * ownership of the fd.
652 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
653 * take ownership of the returned fd.
656 _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
)
658 struct iris_screen
*screen
= batch
->screen
;
660 if (iris_batch_bytes_used(batch
) == 0)
663 iris_finish_batch(batch
);
665 if (unlikely(INTEL_DEBUG
&
666 (DEBUG_BATCH
| DEBUG_SUBMIT
| DEBUG_PIPE_CONTROL
))) {
667 const char *basefile
= strstr(file
, "iris/");
671 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
672 "(cmds), %4d BOs (%0.1fMb aperture)\n",
673 file
, line
, batch_name_to_string(batch
->name
), batch
->hw_ctx_id
,
674 batch
->total_chained_batch_size
,
675 100.0f
* batch
->total_chained_batch_size
/ BATCH_SZ
,
677 (float) batch
->aperture_space
/ (1024 * 1024));
679 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
680 dump_fence_list(batch
);
681 dump_validation_list(batch
);
684 if (INTEL_DEBUG
& DEBUG_BATCH
) {
689 int ret
= submit_batch(batch
);
691 batch
->exec_count
= 0;
692 batch
->aperture_space
= 0;
694 struct iris_syncpt
*syncpt
=
695 ((struct iris_syncpt
**) util_dynarray_begin(&batch
->syncpts
))[0];
696 iris_syncpt_reference(screen
, &batch
->last_syncpt
, syncpt
);
698 util_dynarray_foreach(&batch
->syncpts
, struct iris_syncpt
*, s
)
699 iris_syncpt_reference(screen
, s
, NULL
);
700 util_dynarray_clear(&batch
->syncpts
);
702 util_dynarray_clear(&batch
->exec_fences
);
704 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
705 dbg_printf("waiting for idle\n");
706 iris_bo_wait_rendering(batch
->bo
); /* if execbuf failed; this is a nop */
709 /* Start a new batch buffer. */
710 iris_batch_reset(batch
);
712 /* EIO means our context is banned. In this case, try and replace it
713 * with a new logical context, and inform iris_context that all state
714 * has been lost and needs to be re-initialized. If this succeeds,
715 * dubiously claim success...
717 if (ret
== -EIO
&& replace_hw_ctx(batch
)) {
718 if (batch
->reset
->reset
) {
719 /* Tell the state tracker the device is lost and it was our fault. */
720 batch
->reset
->reset(batch
->reset
->data
, PIPE_GUILTY_CONTEXT_RESET
);
728 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
729 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
730 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
737 * Does the current batch refer to the given BO?
739 * (In other words, is the BO in the current batch's validation list?)
742 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
744 return find_validation_entry(batch
, bo
) != NULL
;
748 * Updates the state of the noop feature.
751 iris_batch_prepare_noop(struct iris_batch
*batch
, bool noop_enable
, uint64_t dirty_flags
)
753 if (batch
->noop_enabled
== noop_enable
)
756 batch
->noop_enabled
= noop_enable
;
758 iris_batch_flush(batch
);
760 /* If the batch was empty, flush had no effect, so insert our noop. */
761 if (iris_batch_bytes_used(batch
) == 0)
762 iris_batch_maybe_noop(batch
);
764 /* We only need to update the entire state if we transition from noop ->
767 return !batch
->noop_enabled
? dirty_flags
: 0;