2 * Copyright © 2017 Intel Corporation
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20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
44 #include "drm-uapi/i915_drm.h"
46 #include "util/hash_table.h"
48 #include "main/macros.h"
53 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
55 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
56 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
57 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
59 #define BATCH_RESERVED 16
62 iris_batch_reset(struct iris_batch
*batch
);
65 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
68 dump_validation_list(struct iris_batch
*batch
)
70 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
72 for (int i
= 0; i
< batch
->exec_count
; i
++) {
73 uint64_t flags
= batch
->validation_list
[i
].flags
;
74 assert(batch
->validation_list
[i
].handle
==
75 batch
->exec_bos
[i
]->gem_handle
);
76 fprintf(stderr
, "[%2d]: %2d %-14s %p %-7s @ 0x%016llx (%"PRIu64
"B) - %d refs\n",
78 batch
->validation_list
[i
].handle
,
79 batch
->exec_bos
[i
]->name
,
81 (flags
& EXEC_OBJECT_WRITE
) ? "(write)" : "",
82 batch
->validation_list
[i
].offset
,
83 batch
->exec_bos
[i
]->size
,
84 batch
->exec_bos
[i
]->refcount
);
89 * Return BO information to the batch decoder (for debugging).
91 static struct gen_batch_decode_bo
92 decode_get_bo(void *v_batch
, uint64_t address
)
94 struct iris_batch
*batch
= v_batch
;
96 for (int i
= 0; i
< batch
->exec_count
; i
++) {
97 struct iris_bo
*bo
= batch
->exec_bos
[i
];
98 /* The decoder zeroes out the top 16 bits, so we need to as well */
99 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
101 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
102 return (struct gen_batch_decode_bo
) {
105 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
106 (address
- bo_address
),
111 return (struct gen_batch_decode_bo
) { };
115 * Decode the current batch.
118 decode_batch(struct iris_batch
*batch
)
120 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
121 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
122 batch
->exec_bos
[0]->gtt_offset
);
126 uint_key_compare(const void *a
, const void *b
)
132 uint_key_hash(const void *key
)
134 return (uintptr_t) key
;
138 iris_init_batch(struct iris_batch
*batch
,
139 struct iris_screen
*screen
,
140 struct iris_vtable
*vtbl
,
141 struct pipe_debug_callback
*dbg
,
142 struct iris_batch
**all_batches
,
146 batch
->screen
= screen
;
151 /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
152 assert((engine
& ~I915_EXEC_RING_MASK
) == 0);
153 assert(util_bitcount(engine
) == 1);
154 batch
->engine
= engine
;
156 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
157 assert(batch
->hw_ctx_id
);
159 batch
->exec_count
= 0;
160 batch
->exec_array_size
= 100;
162 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
163 batch
->validation_list
=
164 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
166 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
167 _mesa_key_pointer_equal
);
168 batch
->cache
.depth
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
169 _mesa_key_pointer_equal
);
171 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
173 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
174 if (all_batches
[i
] != batch
)
175 batch
->other_batches
[j
++] = all_batches
[i
];
178 if (unlikely(INTEL_DEBUG
)) {
180 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
182 const unsigned decode_flags
=
183 GEN_BATCH_DECODE_FULL
|
184 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
185 GEN_BATCH_DECODE_OFFSETS
|
186 GEN_BATCH_DECODE_FLOATS
;
188 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
189 stderr
, decode_flags
, NULL
,
190 decode_get_bo
, NULL
, batch
);
191 batch
->decoder
.max_vbo_decoded_lines
= 32;
194 iris_batch_reset(batch
);
197 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
200 add_exec_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
202 unsigned index
= READ_ONCE(bo
->index
);
204 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
207 /* May have been shared between multiple active batches */
208 for (index
= 0; index
< batch
->exec_count
; index
++) {
209 if (batch
->exec_bos
[index
] == bo
)
213 /* This is the first time our batch has seen this BO. Before we use it,
214 * we need to see if other batches reference it - if so, we should flush
217 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
218 if (iris_batch_references(batch
->other_batches
[b
], bo
))
219 iris_batch_flush(batch
->other_batches
[b
]);
222 /* Now, take a reference and add it to the validation list. */
223 iris_bo_reference(bo
);
225 if (batch
->exec_count
== batch
->exec_array_size
) {
226 batch
->exec_array_size
*= 2;
228 realloc(batch
->exec_bos
,
229 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
230 batch
->validation_list
=
231 realloc(batch
->validation_list
,
232 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
235 batch
->validation_list
[batch
->exec_count
] =
236 (struct drm_i915_gem_exec_object2
) {
237 .handle
= bo
->gem_handle
,
238 .offset
= bo
->gtt_offset
,
242 bo
->index
= batch
->exec_count
;
243 batch
->exec_bos
[batch
->exec_count
] = bo
;
244 batch
->aperture_space
+= bo
->size
;
246 return batch
->exec_count
++;
250 create_batch(struct iris_batch
*batch
)
252 struct iris_screen
*screen
= batch
->screen
;
253 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
255 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
256 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
257 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
258 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
259 batch
->map_next
= batch
->map
;
261 add_exec_bo(batch
, batch
->bo
);
265 iris_batch_reset(struct iris_batch
*batch
)
267 if (batch
->last_bo
!= NULL
) {
268 iris_bo_unreference(batch
->last_bo
);
269 batch
->last_bo
= NULL
;
271 batch
->last_bo
= batch
->bo
;
272 batch
->primary_batch_size
= 0;
273 batch
->contains_draw
= false;
276 assert(batch
->bo
->index
== 0);
278 if (batch
->state_sizes
)
279 _mesa_hash_table_clear(batch
->state_sizes
, NULL
);
281 iris_cache_sets_clear(batch
);
285 iris_batch_free(struct iris_batch
*batch
)
287 struct iris_screen
*screen
= batch
->screen
;
288 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
290 for (int i
= 0; i
< batch
->exec_count
; i
++) {
291 iris_bo_unreference(batch
->exec_bos
[i
]);
293 free(batch
->exec_bos
);
294 free(batch
->validation_list
);
295 iris_bo_unreference(batch
->bo
);
298 batch
->map_next
= NULL
;
300 iris_bo_unreference(batch
->last_bo
);
302 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
304 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
305 _mesa_set_destroy(batch
->cache
.depth
, NULL
);
307 if (batch
->state_sizes
) {
308 _mesa_hash_table_destroy(batch
->state_sizes
, NULL
);
309 gen_batch_decode_ctx_finish(&batch
->decoder
);
314 * If we've chained to a secondary batch, or are getting near to the end,
315 * then flush. This should only be called between draws.
318 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
320 if (batch
->bo
!= batch
->exec_bos
[0] ||
321 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
322 iris_batch_flush(batch
);
327 iris_chain_to_new_batch(struct iris_batch
*batch
)
329 /* We only support chaining a single time. */
330 assert(batch
->bo
== batch
->exec_bos
[0]);
332 uint32_t *cmd
= batch
->map_next
;
333 uint64_t *addr
= batch
->map_next
+ 4;
334 batch
->map_next
+= 8;
336 /* No longer held by batch->bo, still held by validation list */
337 iris_bo_unreference(batch
->bo
);
338 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
341 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
342 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
343 *addr
= batch
->bo
->gtt_offset
;
347 * Terminate a batch with MI_BATCH_BUFFER_END.
350 iris_finish_batch(struct iris_batch
*batch
)
354 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
355 uint32_t *map
= batch
->map_next
;
357 map
[0] = (0xA << 23);
359 batch
->map_next
+= 4;
361 if (batch
->bo
== batch
->exec_bos
[0])
362 batch
->primary_batch_size
= iris_batch_bytes_used(batch
);
366 * Submit the batch to the GPU via execbuffer2.
369 submit_batch(struct iris_batch
*batch
, int in_fence_fd
, int *out_fence_fd
)
371 iris_bo_unmap(batch
->bo
);
373 /* The requirement for using I915_EXEC_NO_RELOC are:
375 * The addresses written in the objects must match the corresponding
376 * reloc.gtt_offset which in turn must match the corresponding
379 * Any render targets written to in the batch must be flagged with
382 * To avoid stalling, execobject.offset should match the current
383 * address of that object within the active context.
385 struct drm_i915_gem_execbuffer2 execbuf
= {
386 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
387 .buffer_count
= batch
->exec_count
,
388 .batch_start_offset
= 0,
389 /* This must be QWord aligned. */
390 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
391 .flags
= batch
->engine
|
393 I915_EXEC_BATCH_FIRST
|
394 I915_EXEC_HANDLE_LUT
,
395 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
398 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
400 if (in_fence_fd
!= -1) {
401 execbuf
.rsvd2
= in_fence_fd
;
402 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
405 if (out_fence_fd
!= NULL
) {
406 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
408 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
411 int ret
= drm_ioctl(batch
->screen
->fd
, cmd
, &execbuf
);
414 DBG("execbuf FAILED: errno = %d\n", -ret
);
415 fprintf(stderr
, "execbuf FAILED: errno = %d\n", -ret
);
418 DBG("execbuf succeeded\n");
421 for (int i
= 0; i
< batch
->exec_count
; i
++) {
422 struct iris_bo
*bo
= batch
->exec_bos
[i
];
428 if (ret
== 0 && out_fence_fd
!= NULL
)
429 *out_fence_fd
= execbuf
.rsvd2
>> 32;
435 * Flush the batch buffer, submitting it to the GPU and resetting it so
436 * we're ready to emit the next batch.
438 * \param in_fence_fd is ignored if -1. Otherwise, this function takes
439 * ownership of the fd.
441 * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
442 * take ownership of the returned fd.
445 _iris_batch_flush_fence(struct iris_batch
*batch
,
446 int in_fence_fd
, int *out_fence_fd
,
447 const char *file
, int line
)
449 if (iris_batch_bytes_used(batch
) == 0)
452 iris_finish_batch(batch
);
454 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
455 int bytes_for_commands
= iris_batch_bytes_used(batch
);
456 int second_bytes
= 0;
457 if (batch
->bo
!= batch
->exec_bos
[0]) {
458 second_bytes
= bytes_for_commands
;
459 bytes_for_commands
+= batch
->primary_batch_size
;
461 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) "
462 "(cmds), %4d BOs (%0.1fMb aperture)\n",
463 file
, line
, batch
->name
, batch
->hw_ctx_id
,
464 batch
->primary_batch_size
, second_bytes
,
465 100.0f
* bytes_for_commands
/ BATCH_SZ
,
467 (float) batch
->aperture_space
/ (1024 * 1024));
468 dump_validation_list(batch
);
471 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
475 int ret
= submit_batch(batch
, in_fence_fd
, out_fence_fd
);
480 //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
481 //iris_check_for_reset(ice);
483 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
484 dbg_printf("waiting for idle\n");
485 iris_bo_wait_rendering(batch
->bo
);
489 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
490 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
491 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
496 /* Clean up after the batch we submitted and prepare for a new one. */
497 for (int i
= 0; i
< batch
->exec_count
; i
++) {
498 iris_bo_unreference(batch
->exec_bos
[i
]);
499 batch
->exec_bos
[i
] = NULL
;
501 batch
->exec_count
= 0;
502 batch
->aperture_space
= 0;
504 /* Start a new batch buffer. */
505 iris_batch_reset(batch
);
511 * Does the current batch refer to the given BO?
513 * (In other words, is the BO in the current batch's validation list?)
516 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
518 unsigned index
= READ_ONCE(bo
->index
);
519 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
522 for (int i
= 0; i
< batch
->exec_count
; i
++) {
523 if (batch
->exec_bos
[i
] == bo
)
530 * Add a buffer to the current batch's validation list.
532 * You must call this on any BO you wish to use in this batch, to ensure
533 * that it's resident when the GPU commands execute.
536 iris_use_pinned_bo(struct iris_batch
*batch
,
540 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
541 unsigned index
= add_exec_bo(batch
, bo
);
543 batch
->validation_list
[index
].flags
|= EXEC_OBJECT_WRITE
;