src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30
  31 #include "util/u_dynarray.h"
  32
  33 #include "drm-uapi/i915_drm.h"
  34 #include "common/gen_decoder.h"
  35
  36 #include "iris_fence.h"
  37
  38 /* The kernel assumes batchbuffers are smaller than 256kB. */
  39 #define MAX_BATCH_SIZE (256 * 1024)
  40
  41 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
  42  * or 12 bytes for MI_BATCH_BUFFER_START (when chaining).  Plus, we may
  43  * need an extra 4 bytes to pad out to the nearest QWord.  So reserve 16.
  44  */
  45 #define BATCH_RESERVED 16
  46
  47 /* Our target batch size - flush approximately at this point. */
  48 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
  49
  50 enum iris_batch_name {
  51    IRIS_BATCH_RENDER,
  52    IRIS_BATCH_COMPUTE,
  53 };
  54
  55 #define IRIS_BATCH_COUNT 2
  56
  57 struct iris_address {
  58    struct iris_bo *bo;
  59    uint64_t offset;
  60    bool write;
  61 };
  62
  63 struct iris_batch {
  64    struct iris_screen *screen;
  65    struct iris_vtable *vtbl;
  66    struct pipe_debug_callback *dbg;
  67    struct pipe_device_reset_callback *reset;
  68
  69    /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
  70    enum iris_batch_name name;
  71
  72    /** Current batchbuffer being queued up. */
  73    struct iris_bo *bo;
  74    void *map;
  75    void *map_next;
  76
  77    /** Size of the primary batch being submitted to execbuf (in bytes). */
  78    unsigned primary_batch_size;
  79
  80    /** Total size of all chained batches (in bytes). */
  81    unsigned total_chained_batch_size;
  82
  83    /** Last Surface State Base Address set in this hardware context. */
  84    uint64_t last_surface_base_address;
  85
  86    uint32_t hw_ctx_id;
  87
  88    /** The validation list */
  89    struct drm_i915_gem_exec_object2 *validation_list;
  90    struct iris_bo **exec_bos;
  91    int exec_count;
  92    int exec_array_size;
  93
  94    /** Whether INTEL_BLACKHOLE_RENDER is enabled in the batch (aka first
  95     * instruction is a MI_BATCH_BUFFER_END).
  96     */
  97    bool noop_enabled;
  98
  99    /**
 100     * A list of iris_syncpts associated with this batch.
 101     *
 102     * The first list entry will always be a signalling sync-point, indicating
 103     * that this batch has completed.  The others are likely to be sync-points
 104     * to wait on before executing the batch.
 105     */
 106    struct util_dynarray syncpts;
 107
 108    /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
 109    struct util_dynarray exec_fences;
 110
 111    /** The amount of aperture space (in bytes) used by all exec_bos */
 112    int aperture_space;
 113
 114    /** A sync-point for the last batch that was submitted. */
 115    struct iris_syncpt *last_syncpt;
 116
 117    /** List of other batches which we might need to flush to use a BO */
 118    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
 119
 120    struct {
 121       /**
 122        * Set of struct brw_bo * that have been rendered to within this
 123        * batchbuffer and would need flushing before being used from another
 124        * cache domain that isn't coherent with it (i.e. the sampler).
 125        */
 126       struct hash_table *render;
 127
 128       /**
 129        * Set of struct brw_bo * that have been used as a depth buffer within
 130        * this batchbuffer and would need flushing before being used from
 131        * another cache domain that isn't coherent with it (i.e. the sampler).
 132        */
 133       struct set *depth;
 134    } cache;
 135
 136    struct gen_batch_decode_ctx decoder;
 137    struct hash_table_u64 *state_sizes;
 138
 139    /** Have we emitted any draw calls to this batch? */
 140    bool contains_draw;
 141
 142    uint32_t last_aux_map_state;
 143 };
 144
 145 void iris_init_batch(struct iris_batch *batch,
 146                      struct iris_screen *screen,
 147                      struct iris_vtable *vtbl,
 148                      struct pipe_debug_callback *dbg,
 149                      struct pipe_device_reset_callback *reset,
 150                      struct hash_table_u64 *state_sizes,
 151                      struct iris_batch *all_batches,
 152                      enum iris_batch_name name,
 153                      int priority);
 154 void iris_chain_to_new_batch(struct iris_batch *batch);
 155 void iris_batch_free(struct iris_batch *batch);
 156 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 157
 158 void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
 159 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
 160
 161 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 162
 163 uint64_t iris_batch_prepare_noop(struct iris_batch *batch,
 164                                  bool noop_enable,
 165                                  uint64_t dirty_flags);
 166
 167 #define RELOC_WRITE EXEC_OBJECT_WRITE
 168
 169 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 170                         bool writable);
 171
 172 enum pipe_reset_status iris_batch_check_for_reset(struct iris_batch *batch);
 173
 174 static inline unsigned
 175 iris_batch_bytes_used(struct iris_batch *batch)
 176 {
 177    return batch->map_next - batch->map;
 178 }
 179
 180 /**
 181  * Ensure the current command buffer has \param size bytes of space
 182  * remaining.  If not, this creates a secondary batch buffer and emits
 183  * a jump from the primary batch to the start of the secondary.
 184  *
 185  * Most callers want iris_get_command_space() instead.
 186  */
 187 static inline void
 188 iris_require_command_space(struct iris_batch *batch, unsigned size)
 189 {
 190    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 191
 192    if (required_bytes >= BATCH_SZ) {
 193       iris_chain_to_new_batch(batch);
 194    }
 195 }
 196
 197 /**
 198  * Allocate space in the current command buffer, and return a pointer
 199  * to the mapped area so the caller can write commands there.
 200  *
 201  * This should be called whenever emitting commands.
 202  */
 203 static inline void *
 204 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 205 {
 206    iris_require_command_space(batch, bytes);
 207    void *map = batch->map_next;
 208    batch->map_next += bytes;
 209    return map;
 210 }
 211
 212 /**
 213  * Helper to emit GPU commands - allocates space, copies them there.
 214  */
 215 static inline void
 216 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 217 {
 218    void *map = iris_get_command_space(batch, size);
 219    memcpy(map, data, size);
 220 }
 221
 222 /**
 223  * Get a pointer to the batch's signalling syncpt.  Does not refcount.
 224  */
 225 static inline struct iris_syncpt *
 226 iris_batch_get_signal_syncpt(struct iris_batch *batch)
 227 {
 228    /* The signalling syncpt is the first one in the list. */
 229    struct iris_syncpt *syncpt =
 230       ((struct iris_syncpt **) util_dynarray_begin(&batch->syncpts))[0];
 231    return syncpt;
 232 }
 233
 234
 235 /**
 236  * Take a reference to the batch's signalling syncpt.
 237  *
 238  * Callers can use this to wait for the the current batch under construction
 239  * to complete (after flushing it).
 240  */
 241 static inline void
 242 iris_batch_reference_signal_syncpt(struct iris_batch *batch,
 243                                    struct iris_syncpt **out_syncpt)
 244 {
 245    struct iris_syncpt *syncpt = iris_batch_get_signal_syncpt(batch);
 246    iris_syncpt_reference(batch->screen, out_syncpt, syncpt);
 247 }
 248
 249 /**
 250  * Record the size of a piece of state for use in INTEL_DEBUG=bat printing.
 251  */
 252 static inline void
 253 iris_record_state_size(struct hash_table_u64 *ht,
 254                        uint32_t offset_from_base,
 255                        uint32_t size)
 256 {
 257    if (ht) {
 258       _mesa_hash_table_u64_insert(ht, offset_from_base,
 259                                   (void *)(uintptr_t) size);
 260    }
 261 }
 262
 263 #endif