2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef IRIS_BATCH_DOT_H
25 #define IRIS_BATCH_DOT_H
31 #include "util/u_dynarray.h"
33 #include "drm-uapi/i915_drm.h"
34 #include "common/gen_decoder.h"
36 #include "iris_fence.h"
38 /* The kernel assumes batchbuffers are smaller than 256kB. */
39 #define MAX_BATCH_SIZE (256 * 1024)
41 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
42 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
43 * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
45 #define BATCH_RESERVED 16
47 /* Our target batch size - flush approximately at this point. */
48 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
50 enum iris_batch_name
{
55 #define IRIS_BATCH_COUNT 2
64 struct iris_screen
*screen
;
65 struct pipe_debug_callback
*dbg
;
66 struct pipe_device_reset_callback
*reset
;
68 /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
69 enum iris_batch_name name
;
71 /** Current batchbuffer being queued up. */
76 /** Size of the primary batch being submitted to execbuf (in bytes). */
77 unsigned primary_batch_size
;
79 /** Total size of all chained batches (in bytes). */
80 unsigned total_chained_batch_size
;
82 /** Last Surface State Base Address set in this hardware context. */
83 uint64_t last_surface_base_address
;
87 /** The validation list */
88 struct drm_i915_gem_exec_object2
*validation_list
;
89 struct iris_bo
**exec_bos
;
93 /** Whether INTEL_BLACKHOLE_RENDER is enabled in the batch (aka first
94 * instruction is a MI_BATCH_BUFFER_END).
99 * A list of iris_syncpts associated with this batch.
101 * The first list entry will always be a signalling sync-point, indicating
102 * that this batch has completed. The others are likely to be sync-points
103 * to wait on before executing the batch.
105 struct util_dynarray syncpts
;
107 /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
108 struct util_dynarray exec_fences
;
110 /** The amount of aperture space (in bytes) used by all exec_bos */
113 /** A sync-point for the last batch that was submitted. */
114 struct iris_syncpt
*last_syncpt
;
116 /** List of other batches which we might need to flush to use a BO */
117 struct iris_batch
*other_batches
[IRIS_BATCH_COUNT
- 1];
121 * Set of struct brw_bo * that have been rendered to within this
122 * batchbuffer and would need flushing before being used from another
123 * cache domain that isn't coherent with it (i.e. the sampler).
125 struct hash_table
*render
;
128 * Set of struct brw_bo * that have been used as a depth buffer within
129 * this batchbuffer and would need flushing before being used from
130 * another cache domain that isn't coherent with it (i.e. the sampler).
135 struct gen_batch_decode_ctx decoder
;
136 struct hash_table_u64
*state_sizes
;
138 /** Have we emitted any draw calls to this batch? */
141 uint32_t last_aux_map_state
;
144 void iris_init_batch(struct iris_batch
*batch
,
145 struct iris_screen
*screen
,
146 struct pipe_debug_callback
*dbg
,
147 struct pipe_device_reset_callback
*reset
,
148 struct hash_table_u64
*state_sizes
,
149 struct iris_batch
*all_batches
,
150 enum iris_batch_name name
,
152 void iris_chain_to_new_batch(struct iris_batch
*batch
);
153 void iris_batch_free(struct iris_batch
*batch
);
154 void iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
);
156 void _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
);
157 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
159 bool iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
);
161 uint64_t iris_batch_prepare_noop(struct iris_batch
*batch
,
163 uint64_t dirty_flags
);
165 #define RELOC_WRITE EXEC_OBJECT_WRITE
167 void iris_use_pinned_bo(struct iris_batch
*batch
, struct iris_bo
*bo
,
170 enum pipe_reset_status
iris_batch_check_for_reset(struct iris_batch
*batch
);
172 static inline unsigned
173 iris_batch_bytes_used(struct iris_batch
*batch
)
175 return batch
->map_next
- batch
->map
;
179 * Ensure the current command buffer has \param size bytes of space
180 * remaining. If not, this creates a secondary batch buffer and emits
181 * a jump from the primary batch to the start of the secondary.
183 * Most callers want iris_get_command_space() instead.
186 iris_require_command_space(struct iris_batch
*batch
, unsigned size
)
188 const unsigned required_bytes
= iris_batch_bytes_used(batch
) + size
;
190 if (required_bytes
>= BATCH_SZ
) {
191 iris_chain_to_new_batch(batch
);
196 * Allocate space in the current command buffer, and return a pointer
197 * to the mapped area so the caller can write commands there.
199 * This should be called whenever emitting commands.
202 iris_get_command_space(struct iris_batch
*batch
, unsigned bytes
)
204 iris_require_command_space(batch
, bytes
);
205 void *map
= batch
->map_next
;
206 batch
->map_next
+= bytes
;
211 * Helper to emit GPU commands - allocates space, copies them there.
214 iris_batch_emit(struct iris_batch
*batch
, const void *data
, unsigned size
)
216 void *map
= iris_get_command_space(batch
, size
);
217 memcpy(map
, data
, size
);
221 * Get a pointer to the batch's signalling syncpt. Does not refcount.
223 static inline struct iris_syncpt
*
224 iris_batch_get_signal_syncpt(struct iris_batch
*batch
)
226 /* The signalling syncpt is the first one in the list. */
227 struct iris_syncpt
*syncpt
=
228 ((struct iris_syncpt
**) util_dynarray_begin(&batch
->syncpts
))[0];
234 * Take a reference to the batch's signalling syncpt.
236 * Callers can use this to wait for the the current batch under construction
237 * to complete (after flushing it).
240 iris_batch_reference_signal_syncpt(struct iris_batch
*batch
,
241 struct iris_syncpt
**out_syncpt
)
243 struct iris_syncpt
*syncpt
= iris_batch_get_signal_syncpt(batch
);
244 iris_syncpt_reference(batch
->screen
, out_syncpt
, syncpt
);
248 * Record the size of a piece of state for use in INTEL_DEBUG=bat printing.
251 iris_record_state_size(struct hash_table_u64
*ht
,
252 uint32_t offset_from_base
,
256 _mesa_hash_table_u64_insert(ht
, offset_from_base
,
257 (void *)(uintptr_t) size
);