src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30
  31 #include "util/u_dynarray.h"
  32
  33 #include "i915_drm.h"
  34 #include "common/gen_decoder.h"
  35
  36 /* The kernel assumes batchbuffers are smaller than 256kB. */
  37 #define MAX_BATCH_SIZE (256 * 1024)
  38
  39 /* Our target batch size - flush approximately at this point. */
  40 #define BATCH_SZ (20 * 1024)
  41
  42 enum iris_batch_name {
  43    IRIS_BATCH_RENDER,
  44    IRIS_BATCH_COMPUTE,
  45 };
  46
  47 #define IRIS_BATCH_COUNT 2
  48
  49 struct iris_address {
  50    struct iris_bo *bo;
  51    uint64_t offset;
  52    bool write;
  53 };
  54
  55 struct iris_batch {
  56    struct iris_screen *screen;
  57    struct iris_vtable *vtbl;
  58    struct pipe_debug_callback *dbg;
  59
  60    /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
  61    enum iris_batch_name name;
  62
  63    /** Current batchbuffer being queued up. */
  64    struct iris_bo *bo;
  65    void *map;
  66    void *map_next;
  67    /** Size of the primary batch if we've moved on to a secondary. */
  68    unsigned primary_batch_size;
  69
  70    /** Last Surface State Base Address set in this hardware context. */
  71    uint64_t last_surface_base_address;
  72
  73    uint32_t hw_ctx_id;
  74
  75    /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
  76    uint8_t engine;
  77
  78    /** The validation list */
  79    struct drm_i915_gem_exec_object2 *validation_list;
  80    struct iris_bo **exec_bos;
  81    int exec_count;
  82    int exec_array_size;
  83
  84    /**
  85     * A list of iris_syncpts associated with this batch.
  86     *
  87     * The first list entry will always be a signalling sync-point, indicating
  88     * that this batch has completed.  The others are likely to be sync-points
  89     * to wait on before executing the batch.
  90     */
  91    struct util_dynarray syncpts;
  92
  93    /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
  94    struct util_dynarray exec_fences;
  95
  96    /** The amount of aperture space (in bytes) used by all exec_bos */
  97    int aperture_space;
  98
  99    /** A sync-point for the last batch that was submitted. */
 100    struct iris_syncpt *last_syncpt;
 101
 102    /** List of other batches which we might need to flush to use a BO */
 103    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
 104
 105    struct {
 106       /**
 107        * Set of struct brw_bo * that have been rendered to within this
 108        * batchbuffer and would need flushing before being used from another
 109        * cache domain that isn't coherent with it (i.e. the sampler).
 110        */
 111       struct hash_table *render;
 112
 113       /**
 114        * Set of struct brw_bo * that have been used as a depth buffer within
 115        * this batchbuffer and would need flushing before being used from
 116        * another cache domain that isn't coherent with it (i.e. the sampler).
 117        */
 118       struct set *depth;
 119    } cache;
 120
 121    /** Map from batch offset to iris_alloc_state data (with DEBUG_BATCH) */
 122    // XXX: unused
 123    struct hash_table *state_sizes;
 124    struct gen_batch_decode_ctx decoder;
 125
 126    /** Have we emitted any draw calls to this batch? */
 127    bool contains_draw;
 128 };
 129
 130 void iris_init_batch(struct iris_batch *batch,
 131                      struct iris_screen *screen,
 132                      struct iris_vtable *vtbl,
 133                      struct pipe_debug_callback *dbg,
 134                      struct iris_batch *all_batches,
 135                      enum iris_batch_name name,
 136                      uint8_t ring);
 137 void iris_chain_to_new_batch(struct iris_batch *batch);
 138 void iris_batch_free(struct iris_batch *batch);
 139 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 140
 141 void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
 142 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
 143
 144 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 145
 146 #define RELOC_WRITE EXEC_OBJECT_WRITE
 147
 148 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 149                         bool writable);
 150
 151 static inline unsigned
 152 iris_batch_bytes_used(struct iris_batch *batch)
 153 {
 154    return batch->map_next - batch->map;
 155 }
 156
 157 /**
 158  * Ensure the current command buffer has \param size bytes of space
 159  * remaining.  If not, this creates a secondary batch buffer and emits
 160  * a jump from the primary batch to the start of the secondary.
 161  *
 162  * Most callers want iris_get_command_space() instead.
 163  */
 164 static inline void
 165 iris_require_command_space(struct iris_batch *batch, unsigned size)
 166 {
 167    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 168
 169    if (required_bytes >= BATCH_SZ) {
 170       iris_chain_to_new_batch(batch);
 171    }
 172 }
 173
 174 /**
 175  * Allocate space in the current command buffer, and return a pointer
 176  * to the mapped area so the caller can write commands there.
 177  *
 178  * This should be called whenever emitting commands.
 179  */
 180 static inline void *
 181 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 182 {
 183    iris_require_command_space(batch, bytes);
 184    void *map = batch->map_next;
 185    batch->map_next += bytes;
 186    return map;
 187 }
 188
 189 /**
 190  * Helper to emit GPU commands - allocates space, copies them there.
 191  */
 192 static inline void
 193 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 194 {
 195    void *map = iris_get_command_space(batch, size);
 196    memcpy(map, data, size);
 197 }
 198
 199 #endif