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24 #ifndef IRIS_BATCH_DOT_H
25 #define IRIS_BATCH_DOT_H
31 #include "util/u_dynarray.h"
33 #include "drm-uapi/i915_drm.h"
34 #include "common/gen_decoder.h"
36 #include "iris_fence.h"
37 #include "iris_fine_fence.h"
41 /* The kernel assumes batchbuffers are smaller than 256kB. */
42 #define MAX_BATCH_SIZE (256 * 1024)
44 /* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
45 * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus another
46 * 24 bytes for the seqno write (using PIPE_CONTROL).
48 #define BATCH_RESERVED 36
50 /* Our target batch size - flush approximately at this point. */
51 #define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
53 enum iris_batch_name
{
58 #define IRIS_BATCH_COUNT 2
61 struct iris_screen
*screen
;
62 struct pipe_debug_callback
*dbg
;
63 struct pipe_device_reset_callback
*reset
;
65 /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
66 enum iris_batch_name name
;
68 /** Current batchbuffer being queued up. */
73 /** Size of the primary batch being submitted to execbuf (in bytes). */
74 unsigned primary_batch_size
;
76 /** Total size of all chained batches (in bytes). */
77 unsigned total_chained_batch_size
;
79 /** Last Surface State Base Address set in this hardware context. */
80 uint64_t last_surface_base_address
;
84 /** The validation list */
85 struct drm_i915_gem_exec_object2
*validation_list
;
86 struct iris_bo
**exec_bos
;
90 /** Whether INTEL_BLACKHOLE_RENDER is enabled in the batch (aka first
91 * instruction is a MI_BATCH_BUFFER_END).
96 * A list of iris_syncobjs associated with this batch.
98 * The first list entry will always be a signalling sync-point, indicating
99 * that this batch has completed. The others are likely to be sync-points
100 * to wait on before executing the batch.
102 struct util_dynarray syncobjs
;
104 /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
105 struct util_dynarray exec_fences
;
107 /** The amount of aperture space (in bytes) used by all exec_bos */
111 /** Uploader to use for sequence numbers */
112 struct u_upload_mgr
*uploader
;
114 /** GPU buffer and CPU map where our seqno's will be written. */
115 struct iris_state_ref ref
;
118 /** The sequence number to write the next time we add a fence. */
122 /** A seqno (and syncobj) for the last batch that was submitted. */
123 struct iris_fine_fence
*last_fence
;
125 /** List of other batches which we might need to flush to use a BO */
126 struct iris_batch
*other_batches
[IRIS_BATCH_COUNT
- 1];
130 * Set of struct brw_bo * that have been rendered to within this
131 * batchbuffer and would need flushing before being used from another
132 * cache domain that isn't coherent with it (i.e. the sampler).
134 struct hash_table
*render
;
137 * Set of struct brw_bo * that have been used as a depth buffer within
138 * this batchbuffer and would need flushing before being used from
139 * another cache domain that isn't coherent with it (i.e. the sampler).
144 struct gen_batch_decode_ctx decoder
;
145 struct hash_table_u64
*state_sizes
;
147 /** Have we emitted any draw calls to this batch? */
150 uint32_t last_aux_map_state
;
153 void iris_init_batch(struct iris_context
*ice
,
154 enum iris_batch_name name
,
156 void iris_chain_to_new_batch(struct iris_batch
*batch
);
157 void iris_batch_free(struct iris_batch
*batch
);
158 void iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
);
160 void _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
);
161 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
163 bool iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
);
165 bool iris_batch_prepare_noop(struct iris_batch
*batch
, bool noop_enable
);
167 #define RELOC_WRITE EXEC_OBJECT_WRITE
169 void iris_use_pinned_bo(struct iris_batch
*batch
, struct iris_bo
*bo
,
172 enum pipe_reset_status
iris_batch_check_for_reset(struct iris_batch
*batch
);
174 static inline unsigned
175 iris_batch_bytes_used(struct iris_batch
*batch
)
177 return batch
->map_next
- batch
->map
;
181 * Ensure the current command buffer has \param size bytes of space
182 * remaining. If not, this creates a secondary batch buffer and emits
183 * a jump from the primary batch to the start of the secondary.
185 * Most callers want iris_get_command_space() instead.
188 iris_require_command_space(struct iris_batch
*batch
, unsigned size
)
190 const unsigned required_bytes
= iris_batch_bytes_used(batch
) + size
;
192 if (required_bytes
>= BATCH_SZ
) {
193 iris_chain_to_new_batch(batch
);
198 * Allocate space in the current command buffer, and return a pointer
199 * to the mapped area so the caller can write commands there.
201 * This should be called whenever emitting commands.
204 iris_get_command_space(struct iris_batch
*batch
, unsigned bytes
)
206 iris_require_command_space(batch
, bytes
);
207 void *map
= batch
->map_next
;
208 batch
->map_next
+= bytes
;
213 * Helper to emit GPU commands - allocates space, copies them there.
216 iris_batch_emit(struct iris_batch
*batch
, const void *data
, unsigned size
)
218 void *map
= iris_get_command_space(batch
, size
);
219 memcpy(map
, data
, size
);
223 * Get a pointer to the batch's signalling syncobj. Does not refcount.
225 static inline struct iris_syncobj
*
226 iris_batch_get_signal_syncobj(struct iris_batch
*batch
)
228 /* The signalling syncobj is the first one in the list. */
229 struct iris_syncobj
*syncobj
=
230 ((struct iris_syncobj
**) util_dynarray_begin(&batch
->syncobjs
))[0];
236 * Take a reference to the batch's signalling syncobj.
238 * Callers can use this to wait for the the current batch under construction
239 * to complete (after flushing it).
242 iris_batch_reference_signal_syncobj(struct iris_batch
*batch
,
243 struct iris_syncobj
**out_syncobj
)
245 struct iris_syncobj
*syncobj
= iris_batch_get_signal_syncobj(batch
);
246 iris_syncobj_reference(batch
->screen
, out_syncobj
, syncobj
);
250 * Record the size of a piece of state for use in INTEL_DEBUG=bat printing.
253 iris_record_state_size(struct hash_table_u64
*ht
,
254 uint32_t offset_from_base
,
258 _mesa_hash_table_u64_insert(ht
, offset_from_base
,
259 (void *)(uintptr_t) size
);